Raw API

ETHERNET Exported Types

struct ETH_EEE_InitTypeDef

ETH EEE (Energy Efficient Ethernet) Configuration Structure.

Public Members

u32 EnableTx

TX LPI Enable: 1=Enable MAC to enter TX LPI, 0=Disable

u32 EnableRx

RX LPI Enable: 1=Enable MAC to respond to PHY LPI, 0=Disable

u8 Tw_WakeTime

Tw: Wake-up time (Unit: 1us). Must be >= PHY spec (Typ: 30us)

u8 Tr_LpiInterval

Tr: LPI refresh time (Unit: 1us). Minimum duration for LPI signal

u8 Td_TxDelay

Td: Decision delay (Unit: 8us). Idle time before entering LPI

u8 Tp_PauseTime

Tp: Pause time (Unit: 1us). Default: 10us

u16 TxTrafficThresh

TX Traffic Threshold (Bytes). Formula: Round[(10us * Rate)/8]. For 100Mbps: Set 0x7D (125 Bytes)

ETH_EEE_SleepPolicy SleepPolicy

Auto-sleep policy selection.

ETH_EEE_WakePolicy WakePolicy

Auto-wake policy selection.

enum ETH_EEE_SleepPolicy

EEE Auto-Sleep Policies (Enter LPI Mode) enumeration. These values map directly to ETH_EEE_CR1 register bits. Multiple policies can be ORed together if supported by hardware logic.

Values:

/* Enter LPI based on low traffic rate (requires Threshold) */
ETH_EEE_SLEEP_LOW_TRAFFIC = BIT_EEE_REQ_SET0

/* Enter LPI immediately when TX queue is empty (Recommended) */
ETH_EEE_SLEEP_QUEUE_EMPTY = BIT_EEE_REQ_SET1

/* Enter LPI when Flow Control Pause frame is received */
ETH_EEE_SLEEP_ON_PAUSE = BIT_EEE_REQ_SET2

/* Mask of all sleep policy bits. */
ETH_EEE_SLEEP_ALL_MASK = (BIT_EEE_REQ_SET0 | BIT_EEE_REQ_SET1 | BIT_EEE_REQ_SET2)
enum ETH_EEE_WakePolicy

EEE Auto-Wake Policies (Exit LPI Mode) enumeration. These values map directly to ETH_EEE_CR1 register bits. Multiple policies can be ORed together.

Values:

/* Wake up on any new data in TX queue */
ETH_EEE_WAKE_ANY_DATA = BIT_EEE_WAKE_SET0

/* Wake up only on high priority data */
ETH_EEE_WAKE_HIGH_PRIO = BIT_EEE_WAKE_SET1

/* Mask of all wake policy bits. */
ETH_EEE_WAKE_ALL_MASK = (BIT_EEE_WAKE_SET0 | BIT_EEE_WAKE_SET1)
struct ETH_InitTypeDef

ETH Init Structure. Contains configuration for both MAC and PHY, plus runtime buffers.

Public Members

struct eth_phy_dev *phy_dev

Pointer to the associated PHY device instance.

union ETH_InitTypeDef.eth_mac_config_u MacConfig

MAC core and flow control configuration.

union ETH_InitTypeDef.eth_vlan_config_u VlanConfig

VLAN tag handling configuration.

ETH_EEE_InitTypeDef *EEE_Config

Pointer to EEE configuration structure, NULL to disable EEE.

uint32_t PktFilter

Additional packet filter control word.

uint8_t DMA_TxThreshold

TX FIFO start-of-transmission threshold (see eth_tx_threshold).

uint8_t DMA_RxThreshold

RX FIFO almost-full threshold (see eth_rx_threshold).

uint8_t DMA_TxTriggerLevel

TX interrupt trigger packet count (see eth_trigger_level).

uint8_t DMA_RxTriggerLevel

RX interrupt trigger packet count (see eth_trigger_level).

uint16_t ETH_IntMask

Interrupt mask, written to ETH_IMR.

uint8_t ETH_MacAddr[6]

Local MAC address (6 bytes).

uint8_t *ETH_TxPktBuf

Pointer to TX packet buffer memory.

uint8_t *ETH_RxPktBuf

Pointer to RX packet buffer memory.

ETH_TxDescTypeDef *ETH_TxDesc

Pointer to TX descriptor ring.

ETH_RxDescTypeDef *ETH_RxDesc

Pointer to RX descriptor ring.

uint16_t ETH_TxDescNum

Number of TX descriptors (1-4096).

uint16_t ETH_RxDescNum

Number of RX descriptors (1-4096).

uint16_t ETH_TxDescCurrentNum

Index of the TX descriptor currently in use.

uint16_t ETH_RxDescCurrentNum

Index of the RX descriptor currently in use.

uint16_t ETH_RxFrameStartDescIdx

Descriptor index of the first segment of the current RX frame.

u32 ETH_RxFrameLen

Total length of the current received frame in bytes.

u32 ETH_TxFrameLen

Length of the last transmitted frame in bytes.

u32 ETH_RxSegmentCount

Number of descriptors used by the current received frame.

u16 ETH_TxBufSize

Size of each TX buffer in bytes.

u16 ETH_RxBufSize

Size of each RX buffer in bytes.

union ETH_InitTypeDef.eth_mac_config_u
uint32_t Raw

Raw 32-bit value for MAC configuration register.

struct ETH_InitTypeDef.eth_mac_config_u.eth_mac_config_bits Bits

Named bitfield access for MAC configuration.

struct ETH_InitTypeDef.eth_mac_config_u.eth_mac_config_bits
uint32_t MacMode

Operating mode (see eth_mode).

uint32_t Loopback

Loopback mode (see eth_loopback_mode).

uint32_t IFGTime

Inter-frame gap setting (see eth_ifg_time).

uint32_t RefClkDir

Reference clock direction (see eth_refclk_dir).

uint32_t RefClkPhase

Reference clock sampling phase (see eth_refclk_phase).

uint32_t RxJumbo

Jumbo frame RX enable (see eth_rx_jumbo_cfg).

uint32_t PktFilterConfig

Packet filter mode (see eth_packet_filter_mode).

uint32_t AutoNego

Auto-negotiation enable (see eth_auto_nego).

uint32_t Speed

Forced link speed when AutoNego=0 (see eth_speed).

uint32_t Duplex

Forced duplex mode when AutoNego=0 (see eth_duplex).

uint32_t FlowCtrl

Flow control mode (see eth_flow_ctrl_mode).

uint32_t FlowForce

Force flow control settings (see eth_flow_force).

uint32_t EEEEnable

1 = enable Energy Efficient Ethernet (EEE).

uint32_t Reserved

Reserved.

union ETH_InitTypeDef.eth_vlan_config_u
uint32_t Raw

Raw 32-bit value for VLAN configuration register.

struct ETH_InitTypeDef.eth_vlan_config_u.eth_vlan_config_bits Bits

Named bitfield access for VLAN configuration.

struct ETH_InitTypeDef.eth_vlan_config_u.eth_vlan_config_bits
uint32_t RxStrip

RX VLAN tag stripping enable (see eth_vlan_strip).

uint32_t TxTagType

TX VLAN tag type: 0=C-TAG, 1=S-TAG (see eth_vlan_type).

uint32_t STagPID

S-TAG Protocol ID for QinQ frames (default 0x88A8).

uint32_t Reserved

Reserved.

struct ETH_LoopBackTest

Ethernet hardware loopback test control and status.

Public Members

uint32_t DataPattern

Test data pattern byte value.

uint32_t DisableTxCRC

1 = disable CRC insertion on TX.

uint32_t PktNumSel

Packet count select: 0=100 packets, 1=1 packet, 2=5 packets.

uint32_t PktLenSel

Packet length select: 0=random, 1=64B fixed.

uint32_t Status_Fail

Test status: 1 = failure detected.

uint32_t Status_Done

Test status: 1 = test finished.

uint32_t DataPatSel

Data pattern source: 0=random, 1=fixed.

uint32_t Enable

1 = enable loopback test function.

uint32_t Reserved

Reserved.

struct ETH_PktMetaDef

Ethernet packet metadata structure covering all TX/RX descriptor features. Strictly 4-byte aligned to prevent compiler padding and optimize cache. Currently only length and VLAN features are implemented in TX/RX functions.

Public Members

u32 pkt_len

TX/RX: Packet length in bytes.

u8 tx_keep

TX: 1 = skip switch lookup, transmit directly.

u8 tx_blu

TX: 1 = L2 bridging lookup only (when tx_keep=0).

u8 tx_dislrn

TX: 1 = disable source MAC address learning.

u8 tx_lgsen

TX: 1 = enable large send offload (TSO/LSO).

u16 tx_lgmss

TX: Maximum segment size for large send offload.

u8 csum_ip

TX/RX: IP checksum offload control (TX) or error status (RX).

u8 csum_l4

TX/RX: L4 (TCP/UDP) checksum offload control (TX) or error status (RX).

u8 cpu_tag_en

TX/RX: 1 = CPU tag present or to be inserted.

u8 cputag_psel

TX: CPU tag port selection.

u8 cputag_pri

TX: CPU tag priority value (0-7).

u8 vlan_valid

TX/RX: 1 = VLAN info in this descriptor is valid.

u16 vlan_tci

TX/RX: VLAN tag control information (PCP, DEI, VID).

u8 vlan_act

TX: VLAN egress action (see eth_vlan_action).

u8 pppoe_valid

TX/RX: 1 = PPPoE info in this descriptor is valid.

u8 pppoe_act

TX: PPPoE egress action.

u8 pppoe_idx

TX: PPPoE session table index.

u8 src_ext_port

TX/RX: Source extension port number.

u8 dst_port_mask

TX/RX: Destination port mask for multicast/forwarding.

u8 strm_id

TX/RX: PON stream ID.

u8 rx_pkt_type

RX: Received packet type (see eth_packet_type).

u8 rx_reason

RX: Trap or drop reason code.

u8 rx_int_prio

RX: Internal priority assigned by the switch.

u8 rx_crc_err

RX: 1 = CRC error detected in received frame.

u8 reserved[3]

Padding for 4-byte alignment.

struct ETH_RxDescTypeDef

Rx Descriptor Structure.

Public Members

uint32_t dw1

Word 0: receive status and frame length.

uint32_t addr

Word 1: buffer address.

uint32_t dw2

Word 2: extended receive status (VLAN, PON).

uint32_t dw3

Word 3: source/destination port and reason code.

struct ETH_TxDescTypeDef

Tx Descriptor Structure.

Public Members

uint32_t dw1

Word 0: status and command flags.

uint32_t addr

Word 1: buffer address.

uint32_t dw2

Word 2: VLAN tag and timestamp info.

uint32_t dw3

Word 3: destination port info.

uint32_t dw4

Word 4: large send (LSO) configuration.

typedef struct ETH_InitTypeDef *PETH_InitTypeDef
enum eth_auto_nego

Auto-negotiation (NWay) enable/disable.

Values:

/* Disable auto-negotiation; use forced mode. */
ETH_NWAY_DISABLE = 0

/* Enable auto-negotiation (NWay). */
ETH_NWAY_ENABLE = 1
typedef void (*eth_callback_t)(u32 event, u32 data)

Function pointer type for the ETH event callback.

enum eth_duplex

Ethernet link duplex mode.

Values:

/* Half-duplex mode. */
ETH_HALF_DUPLEX = 0

/* Full-duplex mode. */
ETH_FULL_DUPLEX = 1
enum eth_flow_ctrl_mode

Ethernet flow control mode.

Values:

/* Flow control disabled. */
ETH_FLOW_OFF = 0

/* TX flow control only: send PAUSE frames. */
ETH_FLOW_TX_ONLY = 1

/* RX flow control only: respect received PAUSE frames. */
ETH_FLOW_RX_ONLY = 2

/* Full flow control: both TX and RX enabled. */
ETH_FLOW_FULL = 3
enum eth_flow_force

Flow control force mode, used when auto-negotiation is disabled.

Values:

/* Flow control from auto-negotiation result. */
ETH_FLOW_AUTO = 0

/* Force flow control settings regardless of NWay. */
ETH_FLOW_FORCE = 1
enum eth_ifg_time

Inter-frame gap (IFG) time between consecutive transmissions.

Values:

/* IFG setting 0: minimum inter-frame gap. */
ETH_IFG_0 = 0

/* IFG setting 1. */
ETH_IFG_1 = 1

/* IFG setting 2. */
ETH_IFG_2 = 2

/* IFG setting 3: standard (9.6 us for 10 Mbps, 960 ns for 100 Mbps). */
ETH_IFG_3 = 3

/* IFG setting 4. */
ETH_IFG_4 = 4

/* IFG setting 5. */
ETH_IFG_5 = 5

/* IFG setting 6. */
ETH_IFG_6 = 6

/* IFG setting 7: maximum inter-frame gap. */
ETH_IFG_7 = 7
enum eth_loopback_mode

Loopback Modes for debugging.

Values:

/* Normal operation, no loopback. */
ETH_LPB_NONE = 0x0

/* External line loopback: RX data echoed to TX. */
ETH_LPB_R2T_EXT = 0x1

/* Internal loopback: TX data fed back to RX. */
ETH_LPB_T2R_INT = 0x3
enum eth_mac_clk_src

Where the MAC gets its 50MHz clock.

Values:

/* Divided down from an on-chip PLL. */
ETH_MAC_CLK_INT50M = 0x00

/* 50MHz from the EXT_CLK50M_IN pin. */
ETH_MAC_CLK_EXT50M = 0x01
enum eth_mode

Ethernet operating mode.

Values:

/* Operates as MAC connected to external PHY (MDIO master). */
ETH_MAC_MODE

/* Operates as PHY connected to external MAC (MDIO slave). */
ETH_PHY_MODE
enum eth_packet_filter_mode

Ethernet packet reception filter mode.

Values:

/* Accept unicast (physical match) and broadcast. Standard mode for most applications. */
ETH_FILTER_DEFAULT_UNICAST = 0

/* Accept unicast, broadcast, and multicast. Required for IPv6, PTP, or video streaming. */
ETH_FILTER_WITH_MULTICAST

/* Accept only packets matching this MAC address, ignoring broadcast. Used in strict security scenarios. */
ETH_FILTER_STRICT_UNICAST

/* Accept all valid packets regardless of destination MAC. Used for packet sniffing or software bridging. */
ETH_FILTER_PROMISCUOUS

/* Accept all packets including error/runt frames. For hardware debugging; WARNING: High CPU load. */
ETH_FILTER_DIAGNOSTIC_ALL
enum eth_packet_type

Defines the type of ethernet packet.

Values:

/* Pure Ethernet frame (non-IP). */
ETH_PKT_ETHERNET = 0

/* IPv4 packet. */
ETH_PKT_IPV4 = 1

/* IPv4 over PPTP. */
ETH_PKT_IPV4_PPTP = 2

/* IPv4 with ICMP payload. */
ETH_PKT_IPV4_ICMP = 3

/* IPv4 with IGMP payload. */
ETH_PKT_IPV4_IGMP = 4

/* IPv4 with TCP payload. */
ETH_PKT_IPV4_TCP = 5

/* IPv4 with UDP payload. */
ETH_PKT_IPV4_UDP = 6

/* IPv6 packet. */
ETH_PKT_IPV6 = 7

/* IPv6 with ICMPv6 payload. */
ETH_PKT_ICMPV6 = 8

/* IPv6 with TCP payload. */
ETH_PKT_IPV6_TCP = 9

/* IPv6 with UDP payload. */
ETH_PKT_IPV6_UDP = 10
enum eth_phy_clk

Clock the MAC outputs to the PHY on the EXT_CLK_OUT pin.

Values:

/* 50MHz. */
ETH_PHY_CLK_50M = 0x0b

/* 25MHz. */
ETH_PHY_CLK_25M = 0x0c
struct eth_phy_dev

PHY Device Instance.

Public Members

const struct eth_mdio_ops *bus

Associated MDIO Bus

const struct eth_phy_ops *ops

Driver operations

Current Link Configuration

uint8_t addr

PHY Address (0-31)

Registered link state change callback, NULL if not set.

void *cb_user_data

User-supplied context pointer passed to link_cb.

struct eth_phy_ops

PHY Driver Operation Table (VTable)

Public Members

int (*init)(struct eth_phy_dev *dev)

Initialize the PHY (Check ID, basic setup)

int (*reset)(struct eth_phy_dev *dev)

Perform Software Reset (Register reset)

Configure Link Parameters (Speed, Duplex, Auto-Neg, Pause)

Get Current Link Status.

int (*autoneg_restart)(struct eth_phy_dev *dev)

Restart Auto-Negotiation.

int (*cfg_refclock)(struct eth_phy_dev *dev, enum eth_refclk_dir dir)

Configure reference clock(REF_CLK) direction.

int (*cfg_eee)(struct eth_phy_dev *dev, uint32_t new_state)

Configure EEE (Energy Efficient Ethernet)

int (*get_eee_cap)(struct eth_phy_dev *dev, phy_eee_capability_t *cap)

Get PHY EEE Capabilities.

int (*set_loopback)(struct eth_phy_dev *dev, bool enable)

Enable/Disable Loopback Mode.

Register Link State Callback.

enum eth_phy_rx_setup

PHY RX data setup time relative to the clock edge.

Values:

/* PHY RX setup time: 8 ns. */
ETH_PHY_RX_SETUP_TIME_8NS = 0x8

/* PHY RX setup time: 10 ns (default). */
ETH_PHY_RX_SETUP_TIME_10NS = 0x9

/* PHY RX setup time: 12 ns. */
ETH_PHY_RX_SETUP_TIME_12NS = 0x6

/* PHY RX setup time: 14 ns. */
ETH_PHY_RX_SETUP_TIME_14NS = 0x7

/* PHY RX setup time: 16 ns. */
ETH_PHY_RX_SETUP_TIME_16NS = 0x4

/* PHY RX setup time: 18 ns. */
ETH_PHY_RX_SETUP_TIME_18NS = 0x5
enum eth_phy_tx_setup

PHY TX data setup time relative to the clock edge.

Values:

/* PHY TX setup time: 6 ns. */
ETH_PHY_TX_SETUP_TIME_6NS = 0x6

/* PHY TX setup time: 8 ns. */
ETH_PHY_TX_SETUP_TIME_8NS = 0x5

/* PHY TX setup time: 10 ns (default). */
ETH_PHY_TX_SETUP_TIME_10NS = 0x4

/* PHY TX setup time: 12 ns. */
ETH_PHY_TX_SETUP_TIME_12NS = 0x3

/* PHY TX setup time: 14 ns. */
ETH_PHY_TX_SETUP_TIME_14NS = 0x2

/* PHY TX setup time: 16 ns. */
ETH_PHY_TX_SETUP_TIME_16NS = 0x1

/* PHY TX setup time: 18 ns. */
ETH_PHY_TX_SETUP_TIME_18NS = 0x0
enum eth_phy_type

Supported PHY Transceivers.

Values:

/* Realtek RTL8201 PHY. */
ETH_PHY_RTL8201 = 0

/* Realtek RTL8211 PHY. */
ETH_PHY_RTL8211 = 1

/* Realtek RTL8721F integrated PHY. */
ETH_PHY_RTL8721F = 2

/* Realtek RTL8721G integrated PHY. */
ETH_PHY_RTL8721G = 3

/* Microchip LAN8720 PHY. */
ETH_PHY_LAN8720 = 4

/* Microchip KSZ8081 PHY. */
ETH_PHY_KSZ8081 = 5

/* Generic IEEE 802.3 compliant PHY. */
ETH_PHY_GENERIC = 6
enum eth_refclk_dir

RMII reference clock direction.

Values:

/* REF_CLK driven by PHY to MAC. */
ETH_REFCLK_PHY2MAC = 0x00

/* REF_CLK driven by MAC to PHY. */
ETH_REFCLK_MAC2PHY = 0x01
enum eth_refclk_phase

RMII reference clock sampling edge.

Values:

/* Data sampled on REF_CLK rising edge. */
ETH_SAMPLED_ON_RISING_EDGE = 0x00

/* Data sampled on REF_CLK falling edge. */
ETH_SAMPLED_ON_FALLING_EDGE = 0x01
enum eth_rx_jumbo_cfg

RX jumbo frame reception enable.

Values:

/* Jumbo frame reception disabled. */
ETH_RX_JUMBO_DISABLE = 0x0

/* Jumbo frame reception enabled (max 16384 bytes). */
ETH_RX_JUMBO_ENABLE = 0x1
enum eth_rx_threshold

RX FIFO almost-full threshold.

Values:

/* RX FIFO threshold: 1024 bytes. */
ETH_RX_THRESHOLD_1024B = 0

/* RX FIFO threshold: 128 bytes. */
ETH_RX_THRESHOLD_128B = 1

/* RX FIFO threshold: 256 bytes. */
ETH_RX_THRESHOLD_256B = 2

/* RX FIFO threshold: 512 bytes. */
ETH_RX_THRESHOLD_512B = 3
enum eth_speed

Ethernet link speed.

Values:

/* 100 Mbps link speed. */
ETH_SPEED_100M = 0

/* 10 Mbps link speed. */
ETH_SPEED_10M = 1
enum eth_sys_hw_ctrl_e

Ethernet system-level hardware power and clock control targets.

Values:

/* FE PHY IP power control. */
ETH_SYS_HW_FEPHY_IP

/* FE MAC IP power control. */
ETH_SYS_HW_FEMAC_IP

/* UABG analog block enable. */
ETH_SYS_HW_UABG_EN

/* UAHV analog block enable. */
ETH_SYS_HW_UAHV_EN

/* FE PHY enable. */
ETH_SYS_HW_FEPHY_EN

/* Lexra bus clock enable. */
ETH_SYS_HW_LX_EN
typedef void (*eth_task_yield)(void)

Function pointer type for the ETH task yield handler.

enum eth_trigger_level

Number of packets to accumulate before raising an interrupt.

Values:

/* Interrupt after 1 packet. */
ETH_TRIGGER_LEVEL_1_PKT = 0

/* Interrupt after 4 packets. */
ETH_TRIGGER_LEVEL_4_PKTS = 1

/* Interrupt after 8 packets. */
ETH_TRIGGER_LEVEL_8_PKTS = 2

/* Interrupt after 12 packets. */
ETH_TRIGGER_LEVEL_12_PKTS = 3

/* Interrupt after 16 packets. */
ETH_TRIGGER_LEVEL_16_PKTS = 4

/* Interrupt after 20 packets. */
ETH_TRIGGER_LEVEL_20_PKTS = 5

/* Interrupt after 24 packets. */
ETH_TRIGGER_LEVEL_24_PKTS = 6

/* Interrupt after 28 packets. */
ETH_TRIGGER_LEVEL_28_PKTS = 7
enum eth_tx_threshold

TX FIFO start-of-transmission threshold.

Values:

/* TX FIFO threshold: 128 bytes. */
ETH_TX_THRESHOLD_128B = 0

/* TX FIFO threshold: 256 bytes. */
ETH_TX_THRESHOLD_256B = 1

/* TX FIFO threshold: 512 bytes. */
ETH_TX_THRESHOLD_512B = 2

/* TX FIFO threshold: 1024 bytes. */
ETH_TX_THRESHOLD_1024B = 3
enum eth_vlan_action

Defines Tx Descriptor VLAN action.

Values:

/* No VLAN header modification. */
ETH_VLAN_HDR_INTACT = 0

/* Insert VLAN tag into the frame. */
ETH_VLAN_HDR_INSERT = 1

/* Remove VLAN tag from the frame. */
ETH_VLAN_HDR_REMOVE = 2

/* Remark VLAN ID in the existing tag. */
ETH_VLAN_HDR_REMARK_VID = 3
enum eth_vlan_strip

Rx VLAN Stripping Control. Controls BIT_RXVLAN (Bit 2).

Values:

/* VLAN tag preserved in received payload. */
ETH_VLAN_STRIP_DISABLE = 0

/* VLAN tag stripped by hardware on reception. */
ETH_VLAN_STRIP_ENABLE = 1
enum eth_vlan_type

VLAN Tag Type Definition for Transmit (Tx). Controls BIT_TDSC_VLAN_TYPE (Bit 15).

Values:

/* C-TAG: customer tag with TPID 0x8100. */
ETH_VLAN_TYPE_CTAG = 0

/* S-TAG: service tag (QinQ) with configurable TPID. */
ETH_VLAN_TYPE_STAG = 1
enum phy_clock_source_t

PHY Clock Source (Platform Specific)

Values:

/* Uses external crystal oscillator. */
PHY_CLK_XTAL = 0

/* Uses 25 MHz oscillator. */
PHY_CLK_OSC_25M

/* Uses 50 MHz oscillator as RMII reference clock. */
PHY_CLK_OSC_50M
enum phy_duplex_t

PHY Duplex Mode.

Values:

/* PHY half-duplex mode. */
PHY_DUPLEX_HALF = 0

/* PHY full-duplex mode. */
PHY_DUPLEX_FULL = 1
enum phy_eee_mode_t

EEE (Energy Efficient Ethernet) Modes.

Values:

/* EEE disabled. */
PHY_EEE_DISABLE = 0

/* Enable EEE via auto-negotiation. */
PHY_EEE_ENABLE_AN

/* Enable LPI (low power idle) signaling only. */
PHY_EEE_ENABLE_LPI

Link State Change Callback.

enum phy_speed_t

PHY Link Speed.

Values:

/* PHY link speed 10 Mbps. */
PHY_SPEED_10M = 10

/* PHY link speed 100 Mbps. */
PHY_SPEED_100M = 100

/* PHY link speed 1000 Mbps. */
PHY_SPEED_1000M = 1000

ETHERNET Exported Constants

/* Ethernet MAC address length in bytes. */
#define ETH_MAC_ADDR_LEN (6)

/* Ethernet frame header length in bytes. Dest(6) + Src(6) + Type(2) */
#define ETH_HEADER_LEN (14)

/* IEEE 802.1Q VLAN tag length in bytes. */
#define ETH_VLAN_TAG_LEN (4)

/* CRC field length in bytes. */
#define ETH_CRC_LEN (4)

/* Minimum Ethernet payload length in bytes. */
#define ETH_PAYLOAD_MIN_LEN (46)

/* Maximum standard Ethernet payload length in bytes. */
#define ETH_PAYLOAD_MAX_LEN (1500)

/* Maximum jumbo frame payload length in bytes. */
#define ETH_JUMBO_FRAME_PAYLOAD_LEN (16 * 1024)

/* Maximum total Ethernet frame size including header, VLAN, payload, and CRC. */
#define ETH_PKT_MAX_SIZE (ETH_HEADER_LEN + ETH_VLAN_TAG_LEN + ETH_PAYLOAD_MAX_LEN + ETH_CRC_LEN)

/* Maximum aligned buffer size for one Ethernet frame. */
#define ETH_MAX_BUF_SIZE ((ETH_PKT_MAX_SIZE + CACHE_LINE_SIZE) & ~(CACHE_LINE_SIZE - 1))

/* Enable the MAC's TX insertion and RX validation of IPv4/TCP/UDP checksums. */
#define ETH_CSUM_OFFLOAD 1

/* Hand RX DMA buffers to lwIP without copying. */
#define ETH_RX_ZERO_COPY 1

/* C-VLAN (802.1Q) header template value with TPID 0x8100. */
#define ETH_C_VLAN_HDR 0x8100279F

/* S-VLAN (QinQ) header template value. */
#define ETH_S_VLAN_HDR 0x88A8279F

/* TX DMA descriptor size in bytes (5 words). */
#define ETH_TX_DESC_SIZE 20

/* RX DMA descriptor size in bytes (4 words). */
#define ETH_RX_DESC_SIZE 16

/* Polling interval in microseconds when checking descriptor own bit. */
#define ETH_OWN_BIT_UPDATE_PERIOD 10

/* Maximum loop count before a hardware operation times out. */
#define ETH_TIMEOUT_CNT_MAX 1000000

/* MDIO bus operation wait time in microseconds. */
#define MDIO_WAIT_TIME 64

/* Wait condition: SMI write operation completed. */
#define WAIT_SMI_WRITE_DONE 0

/* Wait condition: SMI read operation completed. */
#define WAIT_SMI_READ_DONE 1

/* Wait condition: RMII link up detected. */
#define WAIT_RMII_LINKUP 2

ETHERNET Exported Functions

void Ethernet_AutoPolling(u32 opt)

Enable or disable MDIO auto-polling of the PHY status registers.

Parameters:

  • opt –

    This parameter can be one of the following values:

    • ENABLE: Enable auto-polling.

    • DISABLE: Disable auto-polling (required before manual MDIO read/write).

void Ethernet_ClearINT(u16 status)

Clear interrupt status bits.

Parameters:

  • status – BIT_ISR_* bits to clear.

Note

ETH_ISR is write-1-to-clear, so this is a plain write: the bits not in status, and any that arrived after they were read, are left pending. An ISR must clear every bit it read from Ethernet_GetPendingINT(), not only the ones it acts on: TDU and RDU1 latch until cleared and stall the DMA meanwhile.

u32 Ethernet_GetLinkStatus(void)

Get the Ethernet link status.

Returns:

1 for link up, 0 for link down.

u16 Ethernet_GetPendingINT(void)

Read the pending interrupt status without clearing it.

Returns:

ETH_ISR contents, a combination of BIT_ISR_* bits.

u8 *Ethernet_GetRXPktInfo(ETH_InitTypeDef *ETH_InitStruct, ETH_PktMetaDef *meta)

Get the current RX packet buffer address and extract packet metadata.

Parameters:

  • ETH_InitStruct – Pointer to Ethernet initialization structure containing the RX descriptor ring and current index.

  • meta – Pointer to metadata structure to be populated by the driver.

Returns:

Start of the first RX buffer, or NULL if no complete frame is available. The MAC puts 2 bytes ahead of the frame, so the ethernet header starts at return + 2.

Note

Per-packet path: ETH_InitStruct and the ring are validated once by Ethernet_Init().

void Ethernet_GetSpeedDuplex(u32 *speed, u32 *duplex)

Get the speed and duplex the MAC is running at.

Parameters:

  • speed – Returns the link speed, see eth_speed.

  • duplex – Returns the duplex mode, see eth_duplex.

u8 *Ethernet_GetTXPktInfo(ETH_InitTypeDef *ETH_InitStruct)

Get the TX packet buffer address of the current TX descriptor.

Parameters:
Returns:

The word-aligned start of the TX packet buffer, or NULL if no descriptor is available. TX DMA reads from any byte address, so the caller may start the frame 1~3 bytes into the buffer by writing that address back to the descriptor.

Note

Per-packet path: ETH_InitStruct and the ring are validated once by Ethernet_Init().

int Ethernet_Init(ETH_InitTypeDef *ETH_InitStruct)

Initialize Ethernet MAC, PHY, and DMA descriptors.

Parameters:

  • ETH_InitStruct – Pointer to ETH_InitTypeDef containing the full Ethernet configuration.

Returns:

RTK_SUCCESS on success, or a negative error code:

  • -RTK_ERR_BADARG if ETH_InitStruct, phy_dev, or phy_dev->ops is NULL.

  • -RTK_ERR_TIMEOUT if MAC reset timed out.

Note

Does not wait for auto-negotiation: it can take seconds, or never finish with no cable, and the link change interrupt reports the result.

int Ethernet_MacClkConfig(enum eth_mac_clk_src src, u32 ext_pin)

Select the MAC clock source and enable the MAC clock.

Parameters:

  • src – ETH_MAC_CLK_INT50M: divide SYS_PLL or USB_PLL down to 50MHz. ETH_MAC_CLK_EXT50M: take 50MHz from ext_pin.

  • ext_pin – Pin that receives the external clock, only used for ETH_MAC_CLK_EXT50M.

Returns:

RTK_SUCCESS, or RTK_FAIL if the PLLs cannot give 50MHz.

void Ethernet_PhyClkConfig(u32 pin, enum eth_phy_clk clk)

Output a 50MHz or 25MHz clock on a pin, to feed the PHY.

Parameters:

  • pin – Pin that supports the EXT_CLK_OUT pinmux function.

  • clk – ETH_PHY_CLK_50M or ETH_PHY_CLK_25M.

int Ethernet_ReadPhyReg(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)

Read data from MDIO bus (Clause 22).

Parameters:

  • phy_addr – PHY address (0-31).

  • reg_addr – Register address (0-31).

  • data – Pointer to store the read value.

Returns:

RTK_SUCCESS on success, negative error code on failure.

void Ethernet_ReleaseRXDesc(ETH_InitTypeDef *ETH_InitStruct, u32 n)

Hand the next n RX descriptors back to DMA and advance the ring index past them.

Parameters:

  • ETH_InitStruct – Pointer to Ethernet initialization structure.

  • n – Number of descriptors, starting at ETH_RxDescCurrentNum. After a frame from Ethernet_GetRXPktInfo(), pass ETH_RxSegmentCount.

Note

Per-packet path: ETH_InitStruct and the ring are validated once by Ethernet_Init().

void Ethernet_SetDescAddr(ETH_InitTypeDef *ETH_InitStruct)

Set the start address of the TX/RX descriptor ring.

Parameters:
void Ethernet_SetMacAddr(u8 *ETH_MacAddr)

Set the Ethernet MAC address.

Parameters:

  • ETH_MacAddr – The MAC address pointer.

void Ethernet_SetRefclkDirec(u32 refclk_mode)

Set the Ethernet RMII reference clock direction.

Parameters:
void Ethernet_StructInit(ETH_InitTypeDef *ETH_InitStruct, struct eth_phy_dev *PHY_Dev)

Initialize ETH_InitTypeDef.

Parameters:
u32 Ethernet_SwapRXSegBuf(ETH_InitTypeDef *ETH_InitStruct, u32 seg, u32 new_buf, u32 *seg_len)

Replace the buffer of one segment of the current RX frame, for zero-copy RX.

Parameters:

  • ETH_InitStruct – Pointer to Ethernet initialization structure.

  • seg – Segment index within the frame: 0 is FS, must be below ETH_RxSegmentCount.

  • new_buf – Buffer handed to DMA in its place: cache-line aligned, ETH_RxBufSize bytes, invalidated.

  • seg_len – Returns the byte count DMA wrote into the old buffer.

Returns:

The old buffer address, now owned by the caller.

Note

Call after Ethernet_GetRXPktInfo() and before Ethernet_ReleaseRXDesc(), which hands the descriptors back to DMA. Calling it again with the old buffer undoes the swap.

void Ethernet_UpdateTXDESCAndSend(ETH_InitTypeDef *ETH_InitStruct, ETH_PktMetaDef *meta)

Update the TX descriptor with metadata and trigger packet transmission.

Parameters:

  • ETH_InitStruct – Pointer to Ethernet initialization structure.

  • meta – Pointer to packet metadata (Length, VLAN, etc.).

Note

Per-packet path: ETH_InitStruct and the ring are validated once by Ethernet_Init().

void Ethernet_UseExtClk(u32 pin)

Use external 50M clock as the RMII reference source clock.

Parameters:

  • pin – The pin used to input the external 50MHz clock signal. It must be a pin that supports the EXT_CLK50M_IN pinmux function.

int Ethernet_WritePhyReg(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)

Write data to MDIO bus (Clause 22).

Parameters:

  • phy_addr – PHY address (0-31).

  • reg_addr – Register address (0-31).

  • data – Data to write.

Returns:

RTK_SUCCESS on success, negative error code on failure.