Ethernet

Supported Chips: [ RTL8721F ]

Overview

Ethernet is a wired networking technology that complies with the IEEE 802.3 standard. The Ameba series chips integrate an IEEE 802.3 compliant MAC (Media Access Control) controller and connect to an external PHY (Physical Layer) chip via the RMII (Reduced Media Independent Interface), enabling access to the physical network.

Ethernet Architecture

Features

The current Ethernet module supports the following key features:

• Interface Standards & Speed

  • Supports RMII interface standard.

  • Supports 10/100 Mbps speeds with Full-Duplex/Half-Duplex modes.

  • Supports hardware Auto-negotiation for speed and duplex modes.

• Protocols & Flow Control

  • Full-Duplex: Supports IEEE 802.3x Flow Control.

  • Half-Duplex: Supports CSMA/CD (Carrier Sense Multiple Access with Collision Detection) protocol.

• Operating Modes & Clocking

  • Supports configuring the RMII interface in MAC Mode or PHY Mode.

  • Supports outputting a 25/50MHz reference clock source, saving the need for an external PHY crystal.

• Management & Advanced Features

  • Supports configuring and managing PHY devices via the SMI (MDC/MDIO) interface.

  • Supports SMI Master (STA) mode to control external PHYs.

  • Supports EEE (Energy Efficient Ethernet) standard.

Quick Start

Communication Interfaces

Communication between the Ameba MAC and the external world relies on two core interfaces: RMII for data transmission and SMI (MDC/MDIO) for configuration management.

RMII and SMI Interfaces

RMII Data Interface Signals

The Ameba chip connects to the external PHY chip via the RMII interface. The standard signal definitions and directions are described below.

RMII Data Interface Signal Definitions

Signal Name	Abbr.	Direction	Description
TX Data 0	TXD0	MAC ➔ PHY	Transmit Data Bit 0. Lower bit of data transmitted from MAC to PHY.
TX Data 1	TXD1	MAC ➔ PHY	Transmit Data Bit 1. Higher bit of data transmitted from MAC to PHY.
TX Enable	TX_EN	MAC ➔ PHY	Transmit Enable. When high, indicates that valid data is present on TXD.
RX Data 0	RXD0	PHY ➔ MAC	Receive Data Bit 0. Lower bit of data transmitted from PHY to MAC.
RX Data 1	RXD1	PHY ➔ MAC	Receive Data Bit 1. Higher bit of data transmitted from PHY to MAC.
RX Error*	RX_ERR	PHY ➔ MAC	Receive Error. High when the PHY detects an error (e.g., coding error) in the current frame.
CRS_DV	CRS_DV	PHY ➔ MAC	Carrier Sense/Data Valid. Indicates the PHY is receiving data and the medium is not idle.
Ref Clock	REF_CLK	Bi-dir	50MHz Reference Clock. This is the core synchronization clock for RMII operation.

Note

The IEEE 802.3u standard defines RX_ERR (Receive Error). When the PHY detects an error in a received packet, it asserts this signal to notify the MAC. However, in practice, to save pins (GPIO), the MAC controllers of many embedded SoCs do not use the hardware RX_ERR pin in RMII mode. Data integrity relies entirely on the Ethernet frame’s built-in CRC/FCS checksum mechanism.

Compared to the standard MII interface, RMII reduces the data bus width from 4 bits to 2 bits, requiring fewer pins, making it suitable for embedded applications. To maintain a 100Mbps transmission rate with reduced width, the clock frequency is increased from 25MHz to 50MHz. RMII signals use REF_CLK for synchronization, so both MAC and PHY must reference the same clock source. In practice, the following REF_CLK architectures exist:

• MAC supplies REF_CLK to PHY: MAC’s REF_CLK is Output; PHY’s REF_CLK is Input.

• PHY supplies REF_CLK to MAC: MAC’s REF_CLK is Input; PHY’s REF_CLK is Output.

• External Source supplies REF_CLK to both: Both MAC and PHY REF_CLK are set to Input.

See the figure below:

REF_CLK Direction

The specific direction setting depends on the clock source scheme. See PHY Clock Source Selection for details.

SMI Management Interface Signals

The SMI (Serial Management Interface), commonly known as the MDIO Interface, is a simple two-wire serial interface used for exchanging management data between the Ethernet MAC sublayer and the Physical Layer (PHY), with a maximum speed of 2.5MHz.

The MDIO interface uses a Master-Slave architecture containing two types of entities:

• STA (Station Management Entity)

  • Typically integrated into the MAC controller.

  • Acts as the bus Master, initiating all management frames (Read/Write) and driving the clock signal (MDC).

• MMD (MDIO Management Device) / PHY

  • Integrated into the Ethernet PHY chip.

  • Acts as the bus Slave, responding to read/write requests from the STA.

The MDIO interface consists of two signal lines:

SMI Management Interface Signal Definitions

Signal Name	Abbr.	Direction	Description
MDC	MDC	MAC ➔ PHY	Management Data Clock. Provides the clock reference for MDIO data transfer (typically < 2.5MHz).
MDIO	MDIO	Bi-dir	Management Data Input/Output. Used to transfer configuration commands and status data. Requires an external pull-up resistor (typically 1.5kΩ).

Tip

• Aperiodic Clock: MDC does not need to be a continuous periodic signal. The STA can stop the clock between frame transmissions (holding high or low), and the PHY must support this static operation.

• Frequency Independent: As long as the maximum frequency limit (2.5 MHz) is not exceeded, the interface can operate at any lower rate, allowing for software bit-banging of MDIO timing.

Operating Modes

The connection method between the Ethernet MAC controller and external devices depends on its operating mode.

MAC Mode

This is the default operating mode where the CPU’s integrated MAC connects to an external PHY chip, as shown in MAC connecting to external PHY chip. In this mode, Ameba’s RMII interface follows standard MAC definitions to drive TX signals and manage the external PHY via MDC/MDIO.

MAC connecting to external PHY chip

PHY Mode

In embedded system designs, there are often scenarios where two chips with MAC controllers (e.g., SoC to SoC, or SoC to Switch) are located on the same PCB and very close to each other. Using two PHY chips for interconnection would increase BOM cost, power consumption, and PCB area.

• Traditional Connection: Requires additional components, as shown below.

Traditional Connection

• PHY Mode (MAC-to-MAC Direct Connection): The Ameba MAC controller can be configured in PHY Mode (Reverse RMII). The connection diagram is shown in MAC to MAC Direct Connection. This mode saves PHY chips and transformers, significantly optimizing hardware architecture.

MAC to MAC Direct Connection

Warning

PHY Mode Precautions

• Disable Auto-negotiation: Without a PHY chip, auto-negotiation cannot be used. Speed and Duplex must be forced manually.

• Cross Connection: Ensure TX/RX lines are crossed (TX connects to peer RX).

• Common Clock Source: A common clock source strategy is strongly recommended. Either one SoC outputs 50MHz to the other, or both share a single external crystal source to avoid FIFO overflow or CRC errors due to clock frequency deviation (PPM).

Pin Configuration

The ameba_intfcfg.c file predefines 4 groups of Ethernet pin configurations (ETHERNET_PAD). Group 0 is used by default.

ETHERNET_PAD Pin Mapping

Pin Function	Group 0 (Default)	Group 1	Group 2	Group 3
RMII Signals	(Fixed Set)	(Fixed Set)	(Fixed Set)	(Fixed Set)
REF_CLK	PB_9	PB_18	PB_30	PB_18
TXD0	PB_8	PB_13	PB_29	PC_4
TXD1	PB_7	PB_16	PB_28	PC_3
TXEN	PB_6	PB_15	PB_27	PC_2
RXD0	PB_11	PB_21	PC_0	PC_7
RXD1	PB_10	PB_19	PB_31	PC_6
RXERR	PB_4	PB_17	PB_25	PB_17
CRS	PB_5	PB_14	PB_26	PC_5
Mgmt & Clock
MDC	PB_12	PB_22	PC_1	PA_25
MDIO	PB_3	PB_23	PB_24	PA_26
EXTCLK	PA_12	PB_24	PA_12	PB_19

EXTCLK is used to provide a clock to an external PHY chip. See PHY Clock Source Selection.

Note

• All pin assignments under the RMII interface are fixed. Users need to check the pinmux table and modify the ETHERNET_Pin_Grp variable (0x0 - 0x3) in ameba_intfcfg.c to select an available pin group based on the chip package.

• MDC, MDIO, and EXTCLK can be flexibly configured to other pins. Modify based on the pinmux table.

PHY Clock Source Selection

PHY uses Ameba Internal Clock

If the PHY chip supports external clock input, users can configure a pin as EXT_CLK_OUT (the EXTCLK pin in Pin Configuration) via pin multiplexing. The Ameba IC outputs a 25MHz/50MHz clock to the PHY. In this case, the PHY does not need a separate XTAL.

Note

Floating PHY REF_CLK Pin: If using the RTL8201F PHY, an additional circuit connection method is supported. REF_CLK can be connected to the PHY’s XTAL2, and the PHY’s XTAL1 connected to GND to save the PHY’s XTAL, as shown below:

PHY uses Independent XTAL

If the PHY system clock is provided by an independent XTAL, EXT_CLK_OUT does not need to be configured. See below:

Configuration Process

The Ameba SDK integrates the LwIP component, implementing the MAC layer driver (ameba_ethernet.c) and the PHY RTL8201F driver (ameba_phy8201f.c). When using a standard EVB, users can configure and use Ethernet as follows:

1. Menuconfig: Enable related components via menuconfig before compiling.

   1. Go to CONFIG ETHERNET and enable Ethernet.

   2. Key Step: In PHY SOURCE CLK, select the clock source based on the board hardware (see PHY Clock Source Selection).

   • If PHY uses an external crystal: Select CONFIG ETHERNET > Enable ETHERNET > internal xtal, save and exit.

   • If PHY uses Ameba clock output: Go to PHY SOURCE CLK, select CONFIG ETHERNET > Enable ETHERNET > external 50M or external 25M, save and exit.

2. Pin and PHY Adaptation

   • If using a standard EVB, the SDK adapts to PHY RTL8201F by default. Check the schematic and modify the ETHERNET_Pin_Grp index in ameba_intfcfg.c to select the ETHERNET_PAD[4][11] member used by the board.

   • If using a custom board or other PHY chips:

     • Modify the ETHERNET_Pin_Grp index in ameba_intfcfg.c based on the actual pin combination.

     • Add the PHY driver for the specific chip used. Refer to PHY Interface Adaptation.

PHY Interface Adaptation

Software Architecture

Before adapting a PHY driver, it is essential to understand the Ethernet architectural layering. The Ameba Ethernet module integrates the Lightweight TCP/IP stack (LwIP) and MAC driver. The correspondence to OSI and TCP/IP models is shown below:

Ethernet Software Architecture

Layer functions:

Ameba Ethernet Architecture Details

Layer	Component	Description	Core Files	Note
L5-7: App	User App	Implements user logic and high-level protocols (HTTP, MQTT).	(User Defined)	Socket/Netconn API
L4: Transport	TCP & UDP	End-to-end communication; TCP for reliability, UDP for low latency.	tcp.c, udp.c	LwIP Core
L3: Network	IP & ARP	Routing, logical addressing (IPv4/v6), address resolution.	ip4.c, etharp.c	LwIP Core
L2: Data Link	LLC / Adapter	Converts LwIP pbuf to hardware descriptors; “Glue Layer”.	ethernetif.c	Porting Layer
	MAC Driver	Manipulates MAC registers, manages DMA descriptors and interrupts.	ameba_ethernet.c	Platform Specific
L1: Physical	PHY Driver	Configures external PHY transceiver, manages Auto-negotation.	ameba_phy8201f.c	Platform Specific
	HW Interface	Physical bus between MAC and PHY.	N/A	RMII / MII

Note

The L2 MAC driver and RMII operations are implemented in the SDK. RTL8201F driver (L1) is provided.

Adaptation Steps

The Ameba SDK provides a flexible PHY abstraction layer, allowing users to adapt different Ethernet PHY chips by implementing the eth_phy_ops interface table and defining device instances.

Implement PHY Operations

Implement the key functions in struct eth_phy_ops based on the PHY datasheet.

Note

• Standard PHY registers are defined in ameba_phy.h.

• Custom registers can be defined in a user file (e.g., ameba_phy_custom.c).

Taking RTL8201F as an example:

Essential PHY Driver Interfaces

OPS Member	Function	Description	Reason
.init	phy_rtl8201_init	Init & ID Check Read PHY ID and match with RTL8201_PHY_ID_MATCH.	Prevents matching wrong hardware; ensures PHY is powered and MDIO is working.
.reset	phy_rtl8201_reset	Soft Reset Write BMCR reset bit and wait for stabilization.	Ensures PHY is in a known state.
.cfg_refclock	phy_rtl8201_cfg_refclock	Ref Clock Config Switch to Page 7 to set RMII clock direction (Input/Output).	Critical: RMII requires a synchronized 50MHz clock. Wrong direction prevents link establishment.
.cfg_link	phy_rtl8201_cfg_link	Link Config Configure Auto-Neg advertisement or force Speed/Duplex.	Required to set 10M/100M or duplex modes.

Define Bus Interface and PHY Instance

Define the MDIO bus read/write interface and create the eth_phy_dev instance, specifying the PHY address.

// 1. Define MDIO bus operations
// Use low-level read/write functions provided by SDK
const struct eth_mdio_ops eth_mdio_bus_default = {
    .mdio_read  = Ethernet_ReadPhyReg,
    .mdio_write = Ethernet_WritePhyReg,
};

// 2. Define PHY device instance
struct eth_phy_dev eth_phy_dev_custom = {
    .bus  = &eth_mdio_bus_default, // Bind bus interface
    .addr = 0x01,                  // [Important] PHY Address must match schematic
    .ops  = &custom_phy_ops,       // Bind operations implemented above
};

Register and Initialize

In the Ethernet initialization phase, call Ethernet_StructInit() passing the PHY instance.

void User_Ethernet_Init(void)
{
    ETH_InitTypeDef eth_initstruct;

    // Initialize using custom PHY device instance
    // This mounts eth_phy_dev_custom to the MAC driver
    Ethernet_StructInit(&eth_initstruct, &eth_phy_dev_custom);

    // Call other Ethernet functions...
}

Functional Details

Auto-negotiation

Auto-negotiation allows devices on both ends of a link to automatically select common operating parameters:

• Duplex Mode

• Speed

• Flow Control

Note

• IEEE 802.3u makes auto-negotiation optional for 100Mbps Ethernet.

Detection Mechanism

Auto-negotiation uses pulses on the physical link:

• NLP (Normal Link Pulse): Used for 10BASE-T link beat. Single 100ns pulse every 16ms ± 8ms.

• FLP (Fast Link Pulse): Used for 100BASE-TX/1000BASE-T. Extends NLP into a “Burst”.

  • Structure: Burst every 16ms.

  • Encoding: 33 pulse positions (17 clock + 16 data).

  • Link Codeword: 16-bit word advertising speed/duplex capabilities.

Link Pulses and Codewords

Parallel Detection

Used when one side enables Auto-Neg and the other forces a fixed mode.

Principle: The Auto-Neg side detects FLP, NLP, and Idle streams.

1. NLP Detected: Determine peer is 10M.

2. 4B/5B Idle Stream Detected: Determine peer is 100M.

Warning

Duplex Mismatch: Parallel detection cannot detect duplex mode. By standard, the Auto-Neg side must fallback to Half-Duplex.

Negotiation Scenarios

Link establishment depends on configuration:

Negotiation Scenarios

Local Config	Peer Config	Result	Explanation
Auto-Neg	Auto-Neg	✅ Success	Exchange capabilities, lock to highest common mode (e.g., 100M Full).
Auto-Neg	Fixed 10M/100M (Half)	✅ Success	Parallel detection sets local to Half-Duplex. Matches peer.
Auto-Neg	Fixed 10M/100M (Full)	⚠️ Duplex Mismatch	Link Up, but Packet Loss. Local falls back to Half via parallel detection; Peer is Full. Causes collisions and CRC errors.
Auto-Neg (Full Only)	Auto-Neg (Half Only)	❌ Fail	No common capabilities.
Fixed Mode A	Fixed Mode B	❌ Fail	Mismatched speed or duplex prevents sync.

If Auto-Neg is disabled, ensure parameters match exactly on both sides.

Note

Auto-Neg should be disabled for:

• PHY Mode: Connecting to an external MAC requires fixed speed/duplex.

VLAN

VLANs (Virtual LANs) break the limitations of a flat broadcast domain:

• Broadcast Storms: Limits broadcast packets to the VLAN.

• Security: Provides logical isolation.

VLAN Application

VLAN Tagging: Adds a 4-byte tag to the frame to identify membership.

Frame Format

IEEE 802.1Q inserts a tag between the Source MAC and EtherType.

VLAN Frame Format

Fields:

Field	Length	Description
TPID	2 Bytes	Tag Protocol Identifier. Fixed 0x8100 for 802.1Q.
PRI	3 Bits	Priority. 0-7. Used for QoS.
CFI/DEI	1 Bit	Canonical Format Indicator / Drop Eligible Indicator.
VID	12 Bits	VLAN ID. 0-4095. Identifies the VLAN.

QinQ (Double Tagging) uses an outer STAG (Service Tag) and inner CTAG (Customer Tag).

VLAN Frame Processing

Switch logic:

1. Ingress (Receive):

   • Untagged frame from Access Link -> Add PVID Tag -> Internal Switching.

2. Egress (Send):

   • Send to Access Link -> Strip Tag -> Send Untagged Frame.

   • Send to Trunk Link -> Keep Tag -> Send Tagged Frame.

VLAN Configuration

Ameba MAC supports hardware VLAN offload for inserting/removing tags.

Note

HW Limits:

• Supports Double Tagging (STAG + CTAG). No Triple Tag.

• Egress: Single insertion/removal/remark per packet.

• Ingress: Strips inner CTAG only; tag info stored in descriptor.

Egress (TX) Configuration

1. Select Target: CTAG or STAG.

2. Select Action: Insert, Remove, Remark.

Parameter	Description
TxTagType	Target Selection 0: CTAG (Inner, TPID 0x8100) 1: STAG (Outer, TPID defined by STagPID)
STagPID	STAG Protocol ID. Custom TPID (e.g., 0x9100) used if TxTagType is STAG.
DefTxVID	Target VLAN ID. Used for INSERT or REMARK operations.
DefTxAction	Egress Action.

Mode	Function	Scenario
Intact	No change.	Soft-Tagging: OS stack handles tags. Trunk Passthrough.
Insert	Insert new tag.	QinQ: Add Provider Tag. PVID: Force default VLAN on egress.
Remove	Remove tag.	Access Port: Strip tag for end devices. QinQ Termination.
Remark	Replace VID only.	VLAN Translation.

Ingress (RX) Configuration

• RxStrip: Controls hardware stripping (COM_REG.rxvlan).

  • 1: Strip tag. VID available in RX descriptor.

  • 0: Do not strip. Payload contains full tag.

Energy Efficient Ethernet (EEE)

EEE (IEEE 802.3az) reduces power during low data activity using Low Power Idle (LPI).

System Architecture

Requires coordination between MAC (LPI Client) and PHY.

EEE Architecture

Entering/Exiting LPI

In RMII, LPI is signaled via control (TX_EN/CRS_DV) and data (TXD/RXD) combinations.

LPI Signaling

1. TX Path (MAC to PHY):

   • Enter: MAC drives TX_EN=0, TXD=01.

   • Exit: MAC drives TXD=00. Wait for wake time \(T_{wq}\), then assert TX_EN.

2. RX Path (PHY to MAC):

   • Enter: PHY drives CRS_DV=0, RXD=01.

   • Exit: PHY drives RXD=00 upon detecting IDLE on the line.

LPI Decision Makers

1. TX Path:

   • HW Auto: Enters LPI when TX queue is empty, rate is low, or Pause frame received.

   • SW Force: Manual entry.

2. RX Path:

   • MAC passively enters low power state when PHY signals LPI via RMII.

Configuration Process

1. Prerequisites: Enable Auto-Neg, Full Duplex, PHY supports EEE.

2. Sleep/Wake Policy:

Sleep Policy

Option	Description	Scenario
ETH_EEE_SLEEP_IMMEDIATE	Immediate (Default)	IoT. Lowest power, but frequent switching.
ETH_EEE_SLEEP_LOW_TRAFFIC	Threshold	Latency Sensitive. Only sleep when traffic is low.
ETH_EEE_SLEEP_ON_PAUSE	Pause Frame	High Throughput.

3. Traffic Threshold:

   • TrafficThresholdLevel (0-100). Valid only with ETH_EEE_SLEEP_LOW_TRAFFIC.

   • Lower = Aggressive sleep. Higher = Conservative.

Test Modes

Loopback modes for debugging:

Binary	Macro	Mode	Description
2'b00	ETH_LPB_NONE	Normal	Normal operation.
2'b01	ETH_LPB_R2T_EXT	External (R2T)	RX to TX. Forwards received RX packets directly to TX. Tests external physical connection.
2'b11	ETH_LPB_T2R_INT	Internal (T2R)	TX to RX. CPU sent data loops back to RX inside MAC. Does not pass to PHY. Tests driver/MAC logic.

Ethernet Descriptors

Descriptors are shared memory structures between Software (Driver) and Hardware (DMA), enabling Zero-Copy and CPU Offload.

Descriptor Ring

Note

Consistency Requirements

• Memory Attribute: Descriptors should be in Non-cacheable SRAM (or DDR with MPU config) to avoid Cache Coherency issues.

• Alignment: RX buffers must be 4-Byte Aligned.

Descriptor Format

Descriptor Format

1. OWN (Ownership Bit)

• OWN = 1 (DMA): CPU has prepared data (TX) or buffer (RX). CPU must not touch.

• OWN = 0 (CPU): DMA has completed operation. CPU can reclaim.

2. EOR (End of Ring)

• EOR = 1: End of ring. DMA wraps around to base address.

Descriptor Configuration

• Buffer Size: Calculated for Max Ethernet Frame + VLAN + CRC = 1522 Bytes. Aligned to cache line (32B) -> 1536 Bytes.

• Descriptor Count: ETH_RxDescNum / ETH_TxDescNum. More descriptors handle burst traffic better but use more RAM.

Performance Data

Test environment: Code in PSRAM, Descriptors in Non-Cache SRAM. TCP Window 23360 Bytes. Buffer 1536 Bytes.

Ethernet Throughput (Unit: Mbps)

Link Mode	UDP TX	UDP RX	TCP TX	TCP RX
100Mbps Full-Duplex	95.4	93.5	94.8	78.0
100Mbps Half-Duplex	95.4	92.0	90.0	78.0
10Mbps Full-Duplex	9.60	9.57	9.50	9.49
10Mbps Half-Duplex	9.54	9.57	8.80	8.90

Note: Reference data based on standard testing.