Timer
Overview
Ameba series products provide multiple timers for user applications:
RTL8721Dx:
10 Basic Timers:
TIM0-TIM7: Low-frequency Basic Timers (SDM32K clock source)
TIM10-TIM11: High-frequency Basic Timers (XTAL40M clock source)
1x 8-channel PWM Timer: TIM8
1x 1-channel Capture Timer: TIM9
1x 32-bit Debug Timer
2 sets of PMC Timers
RTL8720E:
13 Basic Timers:
TIM0-TIM7: Low-frequency Basic Timers (SDM32K clock source)
TIM10-TIM14: High-frequency Basic Timers (XTAL40M clock source)
1x 8-channel PWM Timer: TIM8
1x 1-channel Capture Timer: TIM9
1x 32-bit Debug Timer
RTL8710E:
13 Basic Timers:
TIM0-TIM7: Low-frequency Basic Timers (SDM32K clock source)
TIM10-TIM14: High-frequency Basic Timers (XTAL40M clock source)
1x 8-channel PWM Timer: TIM8
1x 1-channel Capture Timer: TIM9
1x 32-bit Debug Timer
RTL8726E:
13 Basic Timers:
TIM0-TIM7: Low-frequency Basic Timers (SDM32K clock source)
TIM10-TIM14: High-frequency Basic Timers (XTAL40M clock source)
1x 8-channel PWM Timer: TIM8
1x 1-channel Capture Timer: TIM9
1x 32-bit Debug Timer
RTL8713E:
13 Basic Timers:
TIM0-TIM7: Low-frequency Basic Timers (SDM32K clock source)
TIM10-TIM14: High-frequency Basic Timers (XTAL40M clock source)
1x 8-channel PWM Timer: TIM8
1x 1-channel Capture Timer: TIM9
1x 32-bit Debug Timer
RTL8730E:
12 Basic Timers:
TIM0-TIM7: Low-frequency Basic Timers (SDM32K clock source)
TIM10-TIM13: High-frequency Basic Timers (XTAL40M clock source)
1x 6-channel PWM Timer: TIM8
1x 1-channel Capture Timer: TIM9
1x 32-bit Debug Timer
RTL8721F:
4 Basic Timers: TIM0-TIM3 with software-configurable clock source (SDM32K/XTAL40M)
4x 4-channel PWM Timers: TIM4-TIM7
1x 1-channel Capture Timer: TIM8
1x 64-bit Debug Timer
2 sets of PMC Timers
RTL8720F:
4 Basic Timers: TIM0-TIM3 with software-configurable clock source (SDM32K/XTAL40M)
1x 4-channel PWM Timer: TIM4
1x 6-channel PWM Timer: TIM5
1x 1-channel Capture Timer: TIM6
1x 64-bit Debug Timer
2 sets of PMC Timers
RTL8735C:
4 Gtimer groups:
Group 0 and Group 2 each have 8 timers
Group 1 and Group 3 each have 1 timer
Total: 18 timers
Each timer features:
Count up and count down
Periodic and one-shot mode
4 match events
Prescaler
Basic Timer
Features
32-bit up-counter
Overflow interrupt generation
Preloadable auto-reload register
Sleep mode operation with interrupt wakeup capability
Application Examples
SDK provides two implementation types for Basic Timer:
mbed Examples
Path:
{SDK}\example\peripheral\mbed\Timer\mbed_gtimer\{demo}Demonstrates Basic Timer control in mbed environment
raw Examples
Path:
{SDK}\example\peripheral\raw\Timer\raw_gtimer\{demo}Demonstrates direct register-level Basic Timer control
Note
Check example’s README.md for supported chip information.
Raw API
BASICTIMER Exported Types
-
struct RTIM_TimeBaseInitTypeDef
TIM Basic Init Structure Definition.
Public Members
-
u32 TIM_Prescaler
Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between 0x0 and 0xFFFF, basic timer dont care.
-
u32 TIM_Period
Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter is 16bits for PWM/Capture timers, and 32bits for basic timers. You can get it from SourceClock & TIM_Prescaler.
-
u32 TIM_UpdateEvent
Specifies whether or not to enable update event(UEV). This parameter can be ENABLE or DISABLE. ENABLE means UEV Enable, DISABLE means UEV Disable.
-
u32 TIM_UpdateSource
Specifies the update request source. This parameter can be TIM_UpdateSource_Overflow or TIM_UpdateSource_Global. TIM_UpdateSource_Overflow means counter overflow generates an update event(UEV). TIM_UpdateSource_Global means both counter overflow and setting the UG bit can generate UEV.
-
u32 TIM_ARRProtection
DISABLE or ENABLE, when ENABLE: period will update when cnt = 0(counter overflow, an UEV happens), or period will update immediatly.
-
u8 TIM_Idx
Specifies the timer index.
-
u32 TIM_SecureTimer
Specifies the secure attribute of this timer. This parameter is used in secure world of trustzone.
-
u32 TIM_Prescaler
BASICTIMER Exported Constants
SEC Control Enable Definition
/* R/W 0x0 Secure timer enable * 0: non-security timer * 1: security timer */
#define TIM_BIT_SEC ((u32)0x00000001 << 0)
TIM Event Source
/* Event source: counter update event. */
#define TIM_EventSource_Update ((u32)0x00000001)
/* Check if LP timer event source value is valid. */
#define IS_LP_TIM_EVENT_SOURCE ((((SOURCE) & 0xFFFFFFFE) == 0x0000) && \
(((SOURCE) & 0x1) != 0x0000))
/* Check if HP timer event source value is valid. */
#define IS_HP_TIM_EVENT_SOURCE ((((SOURCE) & 0xFFFFFE00) == 0x0000) && \
(((SOURCE) & 0x1FF) != 0x0000))
/* Check if HP timer event source value is valid. */
#define IS_HP_TIM_EVENT_SOURCE ((((SOURCE) & 0xFFFFFE00) == 0x0000) && \
(((SOURCE) & 0x1FF) != 0x0000))
/* Check if HP timer event source value is valid. */
#define IS_HP_TIM_EVENT_SOURCE ((((SOURCE) & 0xFFFFFE00) == 0x0000) && \
(((SOURCE) & 0x1FF) != 0x0000))
/* Check if HP timer event source value is valid. */
#define IS_HP_TIM_EVENT_SOURCE ((((SOURCE) & 0xFFFFFE00) == 0x0000) && \
(((SOURCE) & 0x1FF) != 0x0000))
/* Check if HP timer event source value is valid. */
#define IS_HP_TIM_EVENT_SOURCE ((((SOURCE) & 0xFFFFFE00) == 0x0000) && \
(((SOURCE) & 0x1FF) != 0x0000))
/* Check if HP timer event source value is valid. */
#define IS_HP_TIM_EVENT_SOURCE ((((SOURCE) & 0xFFFFFF80) == 0x0000) && \
(((SOURCE) & 0x7F) != 0x0000))
/* Check if HP timer event source value is valid. */
#define IS_HP_TIM_EVENT_SOURCE ((((SOURCE) & 0xFFFFFE00) == 0x0000) && \
(((SOURCE) & 0x1FF) != 0x0000))
/* Check if HP timer event source value is valid. */
#define IS_HP_TIM_EVENT_SOURCE ((((SOURCE) & 0xFFFFFE00) == 0x0000) && \
(((SOURCE) & 0x1FF) != 0x0000))
TIM PSC Reload Mode
/* Prescaler reloaded at next update event. */
#define TIM_PSCReloadMode_Update ((u32)0x00000000)
/* Prescaler reloaded immediately. */
#define TIM_PSCReloadMode_Immediate ((u32)0x00000001)
/* Check if prescaler reload mode value is valid. */
#define IS_TIM_PRESCALER_RELOAD (((RELOAD) == TIM_PSCReloadMode_Update) || \
((RELOAD) == TIM_PSCReloadMode_Immediate))
TIM Prescaler
/* Check if prescaler value fits in 16 bits. */
#define IS_TIM_PSC (VAL <= 0xFFFF)
TIM Update Source
/* Source of update is the counter overflow or the setting of UG bit. */
#define TIM_UpdateSource_Global ((u32)0x00000000)
/* Source of update is counter overflow. */
#define TIM_UpdateSource_Overflow ((u32)0x00000004)
/* Check if update request source value is valid. */
#define IS_TIM_UPDATE_SOURCE (((SOURCE) == TIM_UpdateSource_Global) || \
((SOURCE) == TIM_UpdateSource_Overflow))
TIM Type
/* Check if peripheral is a valid timer. */
#define IS_TIM_ALL_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S))
/* Check if peripheral is a secure-world timer. */
#define IS_TIM_SEC_TIM (((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S))
/* Check if peripheral is a basic timer. */
#define IS_TIM_BASIC_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S))
/* Check if peripheral is a 40 MHz timer. */
#define IS_TIM_40M_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S))
/* Check if peripheral is a valid timer. */
#define IS_TIM_ALL_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a secure-world timer. */
#define IS_TIM_SEC_TIM (((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a basic timer. */
#define IS_TIM_BASIC_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a 40 MHz timer. */
#define IS_TIM_40M_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a valid timer. */
#define IS_TIM_ALL_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a secure-world timer. */
#define IS_TIM_SEC_TIM (((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a basic timer. */
#define IS_TIM_BASIC_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a 40 MHz timer. */
#define IS_TIM_40M_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a valid timer. */
#define IS_TIM_ALL_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a secure-world timer. */
#define IS_TIM_SEC_TIM (((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a basic timer. */
#define IS_TIM_BASIC_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a 40 MHz timer. */
#define IS_TIM_40M_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a valid timer. */
#define IS_TIM_ALL_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a secure-world timer. */
#define IS_TIM_SEC_TIM (((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a basic timer. */
#define IS_TIM_BASIC_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a 40 MHz timer. */
#define IS_TIM_40M_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM14) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S) || \
((PERIPH) == TIM14_S))
/* Check if peripheral is a valid timer. */
#define IS_TIM_ALL_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S))
/* Check if peripheral is a secure-world timer. */
#define IS_TIM_SEC_TIM (((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S))
/* Check if peripheral is a basic timer. */
#define IS_TIM_BASIC_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S))
/* Check if peripheral is a 40 MHz timer. */
#define IS_TIM_40M_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM10) || \
((PERIPH) == TIM11) || \
((PERIPH) == TIM12) || \
((PERIPH) == TIM13) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S) || \
((PERIPH) == TIM10_S) || \
((PERIPH) == TIM11_S) || \
((PERIPH) == TIM12_S) || \
((PERIPH) == TIM13_S))
/* Check if peripheral is a valid timer. */
#define IS_TIM_ALL_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a secure-world timer. */
#define IS_TIM_SEC_TIM (((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a basic timer. */
#define IS_TIM_BASIC_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S))
/* Check if peripheral is a 40 MHz timer. */
#define IS_TIM_40M_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a valid timer. */
#define IS_TIM_ALL_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S))
/* Check if peripheral is a secure-world timer. */
#define IS_TIM_SEC_TIM (((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S))
/* Check if peripheral is a basic timer. */
#define IS_TIM_BASIC_TIM (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM0_S) || \
((PERIPH) == TIM1_S) || \
((PERIPH) == TIM2_S) || \
((PERIPH) == TIM3_S))
/* Check if peripheral is a 40 MHz timer. */
#define IS_TIM_40M_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S))
TIM Peripheral Count
/* Total number of TIM peripherals. */
#define TimerNum 12
/* Total number of TIM peripherals. */
#define TimerNum 15
/* Total number of TIM peripherals. */
#define TimerNum 15
/* Total number of TIM peripherals. */
#define TimerNum 15
/* Total number of TIM peripherals. */
#define TimerNum 15
/* Total number of TIM peripherals. */
#define TimerNum 14
/* Total number of TIM peripherals. */
#define TimerNum 9
/* Total number of TIM peripherals. */
#define TimerNum 7
BASICTIMER Exported Functions
TimeBase Management Functions
-
void RTIM_ARRPreloadConfig(RTIM_TypeDef *TIMx, u32 NewState)
Enable or disable TIMx peripheral Preload register on ARR.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
NewState – New state of the TIMx peripheral Preload register This parameter can be: ENABLE or DISABLE.
Note
DISABLE: TIMx_ARR register is not buffered, and shadow register will update immediately
ENABLE: TIMx_ARR register is buffered, and shadow register will update after overflow
-
void RTIM_ChangePeriod(RTIM_TypeDef *TIMx, u32 Autoreload)
Set the TIMx Autoreload Register(TIMx_ARR) value to change period with protection.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
Autoreload –
Specifies the Autoreload register new value. The valid range depends on the TIM type:
Basic timers (non-CCM): 0 ~ 0xFFFFFFFF
CCM timers (PWM/Capture): 0 ~ 0xFFFF
-
void RTIM_ChangePeriodImmediate(RTIM_TypeDef *TIMx, u32 Autoreload)
Set the TIMx Autoreload Register(TIMx_ARR) value to change period.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
Autoreload –
Specifies the Autoreload register new value. The valid range depends on the TIM type:
Basic timers (non-CCM): 0 ~ 0xFFFFFFFF
CCM timers (PWM/Capture): 0 ~ 0xFFFF
-
void RTIM_Cmd(RTIM_TypeDef *TIMx, u32 NewState)
Enable or disable the specified TIM peripheral.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
NewState – New state of the TIMx peripheral. This parameter can be: ENABLE or DISABLE.
-
void RTIM_DeInit(RTIM_TypeDef *TIMx)
DeInit the specified TIM peripheral, including disable TIM, close and clear interrupt.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
-
void RTIM_GenerateEvent(RTIM_TypeDef *TIMx, u32 TIM_EventSource)
Configure the TIMx event to be generated by software.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
TIM_EventSource – Specifies the event source. This parameter can be one or more of the following values TIM Event Source
-
u32 RTIM_GetCount(RTIM_TypeDef *TIMx)
Get the TIMx Counter value.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
- Returns:
Counter Register value.
-
void RTIM_PrescalerConfig(RTIM_TypeDef *TIMx, u32 Prescaler, u32 TIM_PSCReloadMode)
Configure the TIMx Prescaler.
- Parameters:
TIMx – The TIM peripheral with CCM capability. See IS_TIM_CCM_TIM macro.
Prescaler – Specifies the Prescaler Register value, which can be a number in 0~0xFFFF range.
TIM_PSCReloadMode –
Specifies the TIM Prescaler Reload mode This parameter can be one of the following values:
TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
-
void RTIM_Reset(RTIM_TypeDef *TIMx)
Reset timer, counter will start from 0.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
-
void RTIM_TimeBaseInit(RTIM_TypeDef *TIMx, RTIM_TimeBaseInitTypeDef *TIM_InitStruct, IRQn_Type IrqNum, IRQ_FUN UserCB, u32 UserCBData)
Initialize the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_InitStruct.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
TIM_InitStruct – Pointer to a RTIM_TimeBaseInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
IrqNum – The IRQ number for TIMx, which can be TIMERx_IRQ where x is 0 to (TimerNum - 1). See TIM Peripheral Count.
UserCB – ISR callback function. This parameter uses the IRQ_FUN type, which takes a void pointer and returns u32.
UserCBData – Parameters of ISR function.
-
void RTIM_TimeBaseStructInit(RTIM_TimeBaseInitTypeDef *TIM_InitStruct)
Initialize the parameters in the TIM_InitStruct with its default value.
- Parameters:
TIM_InitStruct – Pointer to a RTIM_TimeBaseInitTypeDef structure which will be initialized.
-
void RTIM_UpdateDisableConfig(RTIM_TypeDef *TIMx, u32 NewState)
Enable or Disable the TIMx Update event(UEV).
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
NewState – New state of the TIMx UDIS bit This parameter can be:ENABLE or DISABLE
Note
If NewState is ENABLE, Update Disable Bit is set, UEV disable and shadow registers keep their value.
If NewState is DISABLE, Update Disable Bit is clear, UEV enable and buffered registers are loaded with their preload values when UEV happen.
-
void RTIM_UpdateRequestConfig(RTIM_TypeDef *TIMx, u32 TIM_UpdateSource)
Configure the TIMx Update Request Interrupt source.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
TIM_UpdateSource –
Specifies the Update source. This parameter can be one of the following values:
TIM_UpdateSource_Global: Source of update is the counter overflow or the setting of UG bit.
TIM_UpdateSource_Overflow: Source of update is counter overflow.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
-
void RTIM_ChangePeriodImmediate_us(RTIM_TypeDef *TIMx, u8 tim_idx, u32 period_us)
Set the TIMx Autoreload Register(TIMx_ARR) value to change period(us).
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
tim_idx – Where x can be 0-8.
period_us – Period to be set in microseconds.
-
void RTIM_ChangePeriod_us(RTIM_TypeDef *TIMx, u8 tim_idx, u32 period_us)
Set the TIMx Autoreload Register(TIMx_ARR) value to change period(us) with protection.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
tim_idx – Where x can be 0-8.
period_us – Period to be set in microseconds.
FUNCTION_REF=RTIM_ChangePeriodImmediate_us
FUNCTION_REF=RTIM_ChangePeriod_us
Interrupt Management Functions
-
u32 RTIM_GetINTStatus(RTIM_TypeDef *TIMx, u32 TIM_IT)
Check whether the TIM interrupt has occurred or not.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
TIM_IT – Specifies the TIM interrupt source to check. This parameter is one of the TIM interrupt sources. See TIM Interrupt Control for available values.
- Returns:
The new state of the TIM_IT:
TRUE: The specified TIM interrupt has occurred.
FALSE: The specified TIM interrupt has not occurred.
-
void RTIM_INTClear(RTIM_TypeDef *TIMx)
Clear the TIMx’s all interrupt pending bits.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
-
void RTIM_INTClearPendingBit(RTIM_TypeDef *TIMx, u32 TIM_IT)
Clear the TIMx’s interrupt pending bits.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
TIM_IT – Specifies the pending bit(s) to clear. This parameter is a combination of TIM interrupt bits. See TIM Interrupt Control for available values.
-
void RTIM_INTConfig(RTIM_TypeDef *TIMx, u32 TIM_IT, u32 NewState)
ENABLE/DISABLE the TIMx’s interrupt bits.
- Parameters:
TIMx – The TIM peripheral, where x can be 0 to (TimerNum - 1). See TIM Peripheral Count.
TIM_IT – Specifies the interrupt bit(s) to configure. This parameter is a combination of TIM interrupt bits. See TIM Interrupt Control for available values.
NewState – ENABLE or DISABLE.
Mbed API
MBED_TIMER Exported Types
Structure Type
-
typedef void (*gtimer_irq_handler)(uint32_t id)
Typedef of interrupt handler function pointer.
-
typedef struct gtimer_s gtimer_t
Typedef of struct gtimer_s as gtimer_t.
Enumeration Type
-
enum TIMER_ID
Enumeration of general timer IDs.
Values:
/* General timer 0. */ TIMER0 = 0 /* General timer 1. */ TIMER1 = 1 /* General timer 2. */ TIMER2 = 2 /* General timer 3. */ TIMER3 = 3 /* General timer 4. */ TIMER4 = 4 /* General timer 5. */ TIMER5 = 5 /* General timer 6. */ TIMER6 = 6 /* General timer 7. */ TIMER7 = 7 /* General timer 8. */ TIMER8 = 8 /* General timer 9. */ TIMER9 = 9 /* General timer 10. */ TIMER10 = 10 /* General timer 11. */ TIMER11 = 11 /* Total number of general timers. */ GTIMER_MAX = 12
-
enum TIMER_ID
Enumeration of general timer IDs.
Values:
/* General timer 0. */ TIMER0 = 0 /* General timer 1. */ TIMER1 = 1 /* General timer 2. */ TIMER2 = 2 /* General timer 3. */ TIMER3 = 3 /* General timer 4. */ TIMER4 = 4 /* General timer 5. */ TIMER5 = 5 /* General timer 6. */ TIMER6 = 6 /* General timer 7. */ TIMER7 = 7 /* General timer 8. */ TIMER8 = 8 /* General timer 9. */ TIMER9 = 9 /* General timer 10. */ TIMER10 = 10 /* General timer 11. */ TIMER11 = 11 /* General timer 12. */ TIMER12 = 12 /* General timer 13. */ TIMER13 = 13 /* General timer 14. */ TIMER14 = 14 /* Total number of general timers. */ GTIMER_MAX = 15
STRUCTURE_REF=TIMER_ID_RTL8720E
STRUCTURE_REF=TIMER_ID_RTL8720E
STRUCTURE_REF=TIMER_ID_RTL8720E
-
enum TIMER_ID
Enumeration of general timer IDs.
Values:
/* General timer 0. */ TIMER0 = 0 /* General timer 1. */ TIMER1 = 1 /* General timer 2. */ TIMER2 = 2 /* General timer 3. */ TIMER3 = 3 /* General timer 4. */ TIMER4 = 4 /* General timer 5. */ TIMER5 = 5 /* General timer 6. */ TIMER6 = 6 /* General timer 7. */ TIMER7 = 7 /* General timer 8. */ TIMER8 = 8 /* General timer 9. */ TIMER9 = 9 /* General timer 10. */ TIMER10 = 10 /* General timer 11. */ TIMER11 = 11 /* General timer 12. */ TIMER12 = 12 /* General timer 13. */ TIMER13 = 13 /* Total number of general timers. */ GTIMER_MAX = 14
-
enum TIMER_ID
Enumeration of general timer IDs.
Values:
/* General timer 0. */ TIMER0 = 0 /* General timer 1. */ TIMER1 = 1 /* General timer 2. */ TIMER2 = 2 /* General timer 3. */ TIMER3 = 3 /* General timer 4. */ TIMER4 = 4 /* General timer 5. */ TIMER5 = 5 /* General timer 6. */ TIMER6 = 6 /* General timer 7. */ TIMER7 = 7 /* General timer 8. */ TIMER8 = 8 /* Total number of general timers. */ GTIMER_MAX = 9
-
enum TIMER_ID
Enumeration of general timer IDs.
Values:
/* General timer 0. */ TIMER0 = 0 /* General timer 1. */ TIMER1 = 1 /* General timer 2. */ TIMER2 = 2 /* General timer 3. */ TIMER3 = 3 /* General timer 4. */ TIMER4 = 4 /* General timer 5. */ TIMER5 = 5 /* General timer 6. */ TIMER6 = 6 /* Total number of general timers. */ GTIMER_MAX = 7
MBED_TIMER Exported Functions
-
void gtimer_deinit(gtimer_t *obj)
Deinitialize the timer device, including interrupt and timer registers.
- Parameters:
obj – Timer object defined in application software.
-
void gtimer_init(gtimer_t *obj, uint32_t tid)
Initialize the timer device, including timer registers and interrupt.
- Parameters:
obj – Timer object defined in application software.
tid – General timer ID, which can be a value of TIMER_ID enumeration.
-
uint32_t gtimer_read_tick(gtimer_t *obj)
Get counter value of the specified timer.
- Parameters:
obj – Timer object defined in application software.
- Returns:
Counter value.
-
uint64_t gtimer_read_us(gtimer_t *obj)
Read current timer tick in microsecond.
- Parameters:
obj – Timer object defined in application software.
- Returns:
64b tick time in microsecond(us).
-
void gtimer_reload(gtimer_t *obj, uint32_t duration_us)
Change period of the specified timer.
- Parameters:
obj – Timer object defined in application software.
duration_us – Period to be set in microseconds.
-
void gtimer_start(gtimer_t *obj)
Start the specified timer and enable update interrupt.
- Parameters:
obj – Timer object defined in application software.
-
void gtimer_start_one_shout(gtimer_t *obj, uint32_t duration_us, void *handler, uint32_t hid)
Start the specified timer in one-shot mode with specified period and interrupt handler.
- Parameters:
obj – Timer object defined in application software.
duration_us – Period to be set in microseconds.
handler – User-defined IRQ callback function.
hid – User-defined IRQ callback parameter.
Note
In one-shot mode, timer will stop counting the first time counter overflows.
-
void gtimer_start_periodical(gtimer_t *obj, uint32_t duration_us, void *handler, uint32_t hid)
Start the specified timer in periodical mode with specified period and interrupt handler.
- Parameters:
obj – Timer object defined in application software.
duration_us – Period to be set in microseconds.
handler – User-defined IRQ callback function.
hid – User-defined IRQ callback parameter.
Note
In periodical mode, timer will restart from 0 each time the counter overflows.
PWM Timer
Features
16-bit up-counter
Preloadable auto-reload register
16-bit programmable prescaler
Independent PWM generation per channel
Supported interrupts:
Counter overflow
Software update event
Channel counter overflow
Channel capture/compare
Operation modes:
PWM mode: Configurable duty cycle and period
Input capture: Edge-triggered counter capture
One-pulse mode: Programmable delayed pulse generation
Application Examples
SDK provides two implementation types for PWM Timer:
mbed Examples
Path:
{SDK}\example\peripheral\mbed\Timer\mbed_pwmDemonstrates PWM control in mbed environment
raw Examples
Path:
{SDK}\example\peripheral\raw\Timer\{demo}Demonstrates direct register-level PWM control
Key implementations:
raw_pwm: PWM mode demo
raw_tim_capture_pwm_32k: Input capture demo
raw_tim_pwm_one_pulse: One-pulse mode demo
Note
Check example’s README.md for supported chip information.
Raw API
PWMTIMER Exported Types
-
struct TIM_CCInitTypeDef
TIM Output Compare Init Structure Definition.
Public Members
-
u32 TIM_CCMode
Specifies the CC timer mode. This parameter can be a value of TIM_CCMode_PWM or TIM_CCMode_Inputcapture.
-
u32 TIM_CCPolarity
Specifies the polarity. This parameter can be TIM_CCPolarity_High/TIM_CCPolarity_Low. If CCx channel is configured as output: TIM_CCPolarity_High means OCx active high. TIM_CCPolarity_Low means OCx active low. If CCx channel is configured as input: TIM_CCPolarity_High means positive edge of TRGI is active for capture. TIM_CCPolarity_Low means negative edge of TRGI is active for capture.
-
u32 TIM_OCProtection
Output Compare value update protection. TIM_OCPreload_Enable/TIM_OCPreload_Disable. TIM_OCPreload_Enable means duty cycle will update when UEV happens if write to CCRx field in TIMx_CCRX. TIM_OCPreload_Disable means duty cycle will update immediately if write to CCRx field in TIMx_CCRX.
-
u32 TIM_OCPulse
Specifies the output pulse value to be loaded into the CCRx Register, which decides the duty cycle. This parameter can be a number between 0x0000 and 0xFFFF.
-
u32 TIM_ICPulseMode
Specifies the pulse mode of TIM with pulse capability. This parameter can be TIM_CCMode_PulseWidth or TIM_CCMode_PulseNumber.
-
u32 TIM_CCMode
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
-
struct PWM1_DevTable
PWM dev Table Definition.
Public Members
-
RTIM_TypeDef *TIMx
Pointer to TIM peripheral register base address.
-
u32 Tx_HandshakeInterface
DMA TX handshake interface number.
-
RTIM_TypeDef *TIMx
-
struct TIM_AudInitTypeDef
TIM5 audio and motor Output mode Init Structure Definition.
Public Members
-
u32 TIM_IdleLevel
Specifies the PWM init output level. This parameter can be PWM_OUTPUT_LOW/PWM_OUTPUT_HIGH.
-
u32 TIM_AudBrkLevel
Specifies the PWM brake output level. This parameter can be PWM_OUTPUT_LOW/PWM_OUTPUT_HIGH.
-
u32 TIM_AudFIFOEmptyLevel
Specifies when fifo is empty PWM Output Level. This parameter can be PWM_OUTPUT_LOW/PWM_OUTPUT_HIGH.
-
u32 TIM_AudEmgBrk
Specifies ENABLE/DISABLE emergency brake fuction. This parameter can be ENABLE/DISABLE.
-
u32 TIM_AudEmgBrkLevel
Specifies after emergency brake PWM output level. This parameter can be PWM_EMGBRK_OUTPUT_LOW/PWM_EMGBRK_OUTPUT_HIGH.
-
u32 TIM_AudEmgBrkPol
Specifies after emergency brake trig polarity. This parameter can be PWM_EMGBRK_TRI_POL_HIHG/PWM_EMGBRK_TRI_POL_LOW.
-
u32 TIM_AudCCRSourceSel
Specifies the CCR data source select. This parameter can be PWM_CCR_SOURCE_CPU/PWM_CCR_SOURCE_FIFO.
-
u32 TIM_AudPolSel
Specifies channel1/3/5 polarity, for channel0/2/4 this parameter is invalid. This parameter can be PWM_POLARITY_OPPOSITE/PWM_POLARITY_SAME.
-
u32 TIM_AudChnNum
Specifies PWM channel 0/2/4 control 1 or 2 output pad, for channel1/3/5 this parameter is invalid. This parameter can be PWM_CHANNEL_OUTPUT_ONEPAD/PWM_CHANNEL_OUTPUT_TWOPAD.
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u32 TIM_AudDeadZoneEn
Specifies deadzone statue. This parameter can be DISABLE/ENABLE
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u32 TIM_AudDeadZoneTim
Specifies deadzone time. This parameter can be a number between 0x000 to 0x7FF.
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u32 TIM_AudFIFOemptyMode
Specifies when fifo is empty PWM Output mode. This parameter can be PWM_FIFO_EMPTY_MAINTAIN/PWM_FIFO_EMPTY_BRAKE.
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u32 TIM_IdleLevel
PWMTIMER Exported Constants
TIM Capture Compare Control
/* Enable the Capture/Compare channel output. */
#define TIM_CCx_Enable ((u32)0x01000000)
/* Disable the Capture/Compare channel output. */
#define TIM_CCx_Disable ((u32)0x00000000)
/* Check if CCx enable/disable value is valid. */
#define IS_TIM_CCX (((CCX) == TIM_CCx_Enable) || ((CCX) == TIM_CCx_Disable))
/* Enable output compare preload register on CCRx. */
#define TIM_OCPreload_Enable ((u32)0x02000000)
/* Disable output compare preload register on CCRx. */
#define TIM_OCPreload_Disable ((u32)0x00000000)
/* Check if output compare preload state value is valid. */
#define IS_TIM_OCPRELOAD_STATE (((STATE) == TIM_OCPreload_Enable) || \
((STATE) == TIM_OCPreload_Disable))
/* if input is set : Positive edge of TRGI is active for capture */
#define TIM_CCPolarity_High ((u32)0x00000000)
/* if input is set : negative edge of TRGI is active for capture */
#define TIM_CCPolarity_Low ((u32)0x04000000)
/* Check if CC polarity value is valid. */
#define IS_TIM_CC_POLARITY (((POLARITY) == TIM_CCPolarity_High) || \
((POLARITY) == TIM_CCPolarity_Low))
/* CC channel configured as PWM output mode. */
#define TIM_CCMode_PWM ((u32)0x00000000)
/* CC channel configured as input capture mode. */
#define TIM_CCMode_Inputcapture ((u32)0x08000000)
/* Check if CC mode value is valid. */
#define IS_TIM_CC_MODE (((MODE) == TIM_CCMode_PWM) || \
((MODE) == TIM_CCMode_Inputcapture))
TIM CC Event Source
/* Event source: Capture/Compare channel 0 event. */
#define TIM_EventSource_CC0 ((u32)0x00000002)
/* Event source: Capture/Compare channel 1 event. */
#define TIM_EventSource_CC1 ((u32)0x00000004)
/* Event source: Capture/Compare channel 2 event. */
#define TIM_EventSource_CC2 ((u32)0x00000008)
/* Event source: Capture/Compare channel 3 event. */
#define TIM_EventSource_CC3 ((u32)0x00000010)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
/* Event source: Capture/Compare channel 6 event. */
#define TIM_EventSource_CC6 ((u32)0x00000080)
/* Event source: Capture/Compare channel 7 event. */
#define TIM_EventSource_CC7 ((u32)0x00000100)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
/* Event source: Capture/Compare channel 6 event. */
#define TIM_EventSource_CC6 ((u32)0x00000080)
/* Event source: Capture/Compare channel 7 event. */
#define TIM_EventSource_CC7 ((u32)0x00000100)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
/* Event source: Capture/Compare channel 6 event. */
#define TIM_EventSource_CC6 ((u32)0x00000080)
/* Event source: Capture/Compare channel 7 event. */
#define TIM_EventSource_CC7 ((u32)0x00000100)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
/* Event source: Capture/Compare channel 6 event. */
#define TIM_EventSource_CC6 ((u32)0x00000080)
/* Event source: Capture/Compare channel 7 event. */
#define TIM_EventSource_CC7 ((u32)0x00000100)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
/* Event source: Capture/Compare channel 6 event. */
#define TIM_EventSource_CC6 ((u32)0x00000080)
/* Event source: Capture/Compare channel 7 event. */
#define TIM_EventSource_CC7 ((u32)0x00000100)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
Not supported.
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
TIM Channel
/* Timer channel 0 index. */
#define TIM_Channel_0 ((u16)0x0000)
/* Timer channel 1 index. */
#define TIM_Channel_1 ((u16)0x0001)
/* Timer channel 2 index. */
#define TIM_Channel_2 ((u16)0x0002)
/* Timer channel 3 index. */
#define TIM_Channel_3 ((u16)0x0003)
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Timer channel 6 index. */
#define TIM_Channel_6 ((u16)0x0006)
/* Timer channel 7 index. */
#define TIM_Channel_7 ((u16)0x0007)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Timer channel 6 index. */
#define TIM_Channel_6 ((u16)0x0006)
/* Timer channel 7 index. */
#define TIM_Channel_7 ((u16)0x0007)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Timer channel 6 index. */
#define TIM_Channel_6 ((u16)0x0006)
/* Timer channel 7 index. */
#define TIM_Channel_7 ((u16)0x0007)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Timer channel 6 index. */
#define TIM_Channel_6 ((u16)0x0006)
/* Timer channel 7 index. */
#define TIM_Channel_7 ((u16)0x0007)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Timer channel 6 index. */
#define TIM_Channel_6 ((u16)0x0006)
/* Timer channel 7 index. */
#define TIM_Channel_7 ((u16)0x0007)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5))
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5))
TIM Default Level
/* PWM one-pulse default output level: high. */
#define TIMPWM_DefaultLevel_High ((u32)0x00000000)
/* PWM one-pulse default output level: low. */
#define TIMPWM_DefaultLevel_Low ((u32)0x00000001)
/* Check if default level value is valid. */
#define IS_TIMPWM_DefaultLevel (((LEVEL) == TIMPWM_DefaultLevel_High) || ((LEVEL) == TIMPWM_DefaultLevel_Low))
TIM Interrupt Control
/* Timer counter update interrupt flag. */
#define TIM_IT_Update ((u32)0x00000001)
/* Capture/Compare channel 0 interrupt flag. */
#define TIM_IT_CC0 ((u32)0x00000002)
/* Capture/Compare channel 1 interrupt flag. */
#define TIM_IT_CC1 ((u32)0x00000004)
/* Capture/Compare channel 2 interrupt flag. */
#define TIM_IT_CC2 ((u32)0x00000008)
/* Capture/Compare channel 3 interrupt flag. */
#define TIM_IT_CC3 ((u32)0x00000010)
/* Channel 0 update interrupt enable flag. */
#define TIM_IT_UIE0 ((u32)0x00010000)
/* Channel 1 update interrupt enable flag. */
#define TIM_IT_UIE1 ((u32)0x00020000)
/* Channel 2 update interrupt enable flag. */
#define TIM_IT_UIE2 ((u32)0x00040000)
/* Channel 3 update interrupt enable flag. */
#define TIM_IT_UIE3 ((u32)0x00080000)
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Capture/Compare channel 6 interrupt flag. */
#define TIM_IT_CC6 ((u32)0x00000080)
/* Capture/Compare channel 7 interrupt flag. */
#define TIM_IT_CC7 ((u32)0x00000100)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Channel 6 update interrupt enable flag. */
#define TIM_IT_UIE6 ((u32)0x00400000)
/* Channel 7 update interrupt enable flag. */
#define TIM_IT_UIE7 ((u32)0x00800000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFF00FE00) == 0x0000) && (((IT) & (u32)0xFF01FF) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5) || \
((IT) == TIM_IT_UIE6) || \
((IT) == TIM_IT_UIE7))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Capture/Compare channel 6 interrupt flag. */
#define TIM_IT_CC6 ((u32)0x00000080)
/* Capture/Compare channel 7 interrupt flag. */
#define TIM_IT_CC7 ((u32)0x00000100)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Channel 6 update interrupt enable flag. */
#define TIM_IT_UIE6 ((u32)0x00400000)
/* Channel 7 update interrupt enable flag. */
#define TIM_IT_UIE7 ((u32)0x00800000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFF00FE00) == 0x0000) && (((IT) & (u32)0xFF01FF) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5) || \
((IT) == TIM_IT_UIE6) || \
((IT) == TIM_IT_UIE7))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Capture/Compare channel 6 interrupt flag. */
#define TIM_IT_CC6 ((u32)0x00000080)
/* Capture/Compare channel 7 interrupt flag. */
#define TIM_IT_CC7 ((u32)0x00000100)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Channel 6 update interrupt enable flag. */
#define TIM_IT_UIE6 ((u32)0x00400000)
/* Channel 7 update interrupt enable flag. */
#define TIM_IT_UIE7 ((u32)0x00800000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFF00FE00) == 0x0000) && (((IT) & (u32)0xFF01FF) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5) || \
((IT) == TIM_IT_UIE6) || \
((IT) == TIM_IT_UIE7))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Capture/Compare channel 6 interrupt flag. */
#define TIM_IT_CC6 ((u32)0x00000080)
/* Capture/Compare channel 7 interrupt flag. */
#define TIM_IT_CC7 ((u32)0x00000100)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Channel 6 update interrupt enable flag. */
#define TIM_IT_UIE6 ((u32)0x00400000)
/* Channel 7 update interrupt enable flag. */
#define TIM_IT_UIE7 ((u32)0x00800000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFF00FE00) == 0x0000) && (((IT) & (u32)0xFF01FF) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5) || \
((IT) == TIM_IT_UIE6) || \
((IT) == TIM_IT_UIE7))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Capture/Compare channel 6 interrupt flag. */
#define TIM_IT_CC6 ((u32)0x00000080)
/* Capture/Compare channel 7 interrupt flag. */
#define TIM_IT_CC7 ((u32)0x00000100)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Channel 6 update interrupt enable flag. */
#define TIM_IT_UIE6 ((u32)0x00400000)
/* Channel 7 update interrupt enable flag. */
#define TIM_IT_UIE7 ((u32)0x00800000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFF00FE00) == 0x0000) && (((IT) & (u32)0xFF01FF) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5) || \
((IT) == TIM_IT_UIE6) || \
((IT) == TIM_IT_UIE7))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFFC0FF80) == 0x0000) && (((IT) & (u32)0x3F007F) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5))
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFFF0FFE0) == 0x0000) && (((IT) & (u32)0xF001F) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFFC0FF80) == 0x0000) && (((IT) & (u32)0x3F007F) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5))
TIM OPM Control
/* External trigger polarity: positive edge active. */
#define TIM_OPMode_ETP_positive ((u32)0x00000000)
/* External trigger polarity: negative edge active. */
#define TIM_OPMode_ETP_negative ((u32)0x00000100)
/* External trigger polarity: both edges active. */
#define TIM_OPMode_ETP_bothedge ((u32)0x00000200)
/* Check if external trigger polarity mode is valid. */
#define IS_TIM_OPM_ETP_MODE (((MODE) == TIM_OPMode_ETP_positive) || \
((MODE) == TIM_OPMode_ETP_negative) || \
((MODE) == TIM_OPMode_ETP_bothedge))
/* One-pulse mode: counter stops at next update event. */
#define TIM_OPMode_Single ((u32)0x00000008)
/* Repetitive (PWM) mode: counter does not stop at next update event. */
#define TIM_OPMode_Repetitive ((u32)0x00000000)
/* Check if one-pulse operation mode value is valid. */
#define IS_TIM_OPM_MODE (((MODE) == TIM_OPMode_Single) || \
((MODE) == TIM_OPMode_Repetitive))
TIM Phase Sync Control
/* Phase sync direction: channel delays behind reference counter. */
#define TIMPWM_PSync_Delay ((u32)0x00000000)
/* Phase sync direction: channel leads ahead of reference counter. */
#define TIMPWM_PSync_Ahead ((u32)0x00000001)
/* Check if phase sync direction value is valid. */
#define IS_TIMPWM_PSync_Dir (((DIR) == TIMPWM_PSync_Delay) || ((DIR) == TIMPWM_PSync_Ahead))
/* Enable phase sync parameter preload register. */
#define TIMPWM_PSyncPreload_Enable ((u32)0x00000000)
/* Disable phase sync parameter preload register. */
#define TIMPWM_PSyncPreload_Disable ((u32)0x00000001)
/* Check if phase sync preload state value is valid. */
#define IS_TIMPWM_PPRELOAD_STATE (((STATE) == TIMPWM_PSyncPreload_Enable) || \
((STATE) == TIMPWM_PSyncPreload_Disable))
TIM PWM Type
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S))
/* Check if peripheral is the audio/motor PWM timer. */
#define IS_PWM_TIM5 (((PERIPH) == TIM5) || \
((PERIPH) == TIM5_S))
PWM AUD Channel
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
/* PWM audio/motor channel 0 index. */
#define PWM_AUD_Channel_0 ((u16)0x0000)
/* PWM audio/motor channel 1 index. */
#define PWM_AUD_Channel_1 ((u16)0x0001)
/* PWM audio/motor channel 2 index. */
#define PWM_AUD_Channel_2 ((u16)0x0002)
/* PWM audio/motor channel 3 index. */
#define PWM_AUD_Channel_3 ((u16)0x0003)
/* PWM audio/motor channel 4 index. */
#define PWM_AUD_Channel_4 ((u16)0x0004)
/* PWM audio/motor channel 5 index. */
#define PWM_AUD_Channel_5 ((u16)0x0005)
/* Check if value is a valid PWM AUD channel index (0-5). */
#define IS_PWM_AUD_CHANNEL (((CHANNEL) == PWM_AUD_Channel_0) || \
((CHANNEL) == PWM_AUD_Channel_1) || \
((CHANNEL) == PWM_AUD_Channel_2) || \
((CHANNEL) == PWM_AUD_Channel_3) || \
((CHANNEL) == PWM_AUD_Channel_4) || \
((CHANNEL) == PWM_AUD_Channel_5))
PWM Audio and Motor Control
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
/* PWM idle/brake output level: low. */
#define PWM_OUTPUT_LOW ((u32)0x00000000)
/* PWM idle/brake output level: high. */
#define PWM_OUTPUT_HIGH ((u32)0x00000001)
/* Emergency brake PWM output level: low. */
#define PWM_EMGBRK_OUTPUT_LOW ((u32)0x00000000)
/* Emergency brake PWM output level: high. */
#define PWM_EMGBRK_OUTPUT_HIGH ((u32)0x00000004)
/* Emergency brake trigger polarity: high level active. */
#define PWM_EMGBRK_TRI_POL_HIHG ((u32)0x00000000)
/* Emergency brake trigger polarity: low level active. */
#define PWM_EMGBRK_TRI_POL_LOW ((u32)0x04000000)
/* CCR data source: CPU register write. */
#define PWM_CCR_SOURCE_CPU ((u32)0x00000000)
/* CCR data source: FIFO. */
#define PWM_CCR_SOURCE_FIFO ((u32)0x00000010)
/* Disable emergency brake function. */
#define PWM_EMGBRK_DISABLE ((u32)0x00000000)
/* Enable emergency brake function. */
#define PWM_EMGBRK_ENABLE ((u32)0x00000008)
/* Channel output phase: opposite to paired channel. */
#define PWM_POLARITY_OPPOSITE ((u32)0x00000000)
/* Channel output phase: same as paired channel. */
#define PWM_POLARITY_SAME ((u32)0x00000020)
/* Channel controls one output pad. */
#define PWM_CHANNEL_OUTPUT_ONEPAD ((u32)0x00000000)
/* Channel controls two output pads. */
#define PWM_CHANNEL_OUTPUT_TWOPAD ((u32)0x00000040)
/* Enable dead zone control. */
#define PWM_DeadzoneEn ((u32)0x00000080)
/* Disable dead zone control. */
#define PWM_DeadzoneDis ((u32)0x00000000)
/* FIFO empty mode: maintain last output data. */
#define PWM_FIFO_EMPTY_MAINTAIN ((u32)0x00000000)
/* FIFO empty mode: enter brake state. */
#define PWM_FIFO_EMPTY_BRAKE ((u32)0x00000100)
PWM Audio and Motor Interrupt Control
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
/* Interrupt status flag: FIFO empty event. */
#define TIM_IT_FIFO_EMPTY_FLAG ((u32)0x00000001)
/* Interrupt status flag: emergency brake release event. */
#define TIM_IT_EMG_BRK_RELEASE_FLAG ((u32)0x00000002)
/* Interrupt enable bit: FIFO empty interrupt. */
#define TIM_IT_FIFO_EMPTY ((u32)0x00000004)
/* Interrupt enable bit: emergency brake release interrupt. */
#define TIM_IT_EMG_BRK_RELEASE ((u32)0x00000008)
/* All audio/motor interrupt status flags combined. */
#define TIM_IT_AUD_ALL_FLAG (TIM_IT_FIFO_EMPTY_FLAG | TIM_IT_EMG_BRK_RELEASE_FLAG)
/* Check if value is a valid audio/motor interrupt status flag. */
#define IS_TIM_AUD_IT_FLAG (((IT) == TIM_IT_FIFO_EMPTY_FLAG) || ((IT) == TIM_IT_EMG_BRK_RELEASE_FLAG))
/* All audio/motor interrupt enable bits combined. */
#define TIM_IT_AUD_ALL (TIM_IT_FIFO_EMPTY | TIM_IT_EMG_BRK_RELEASE)
/* Check if value is a valid audio/motor interrupt enable bit. */
#define IS_TIM_AUD_IT (((IT) == TIM_IT_FIFO_EMPTY) || ((IT) == TIM_IT_EMG_BRK_RELEASE))
PWMTIMER Exported Functions
Capture Compare Management Functions
-
void RTIM_CCRxMode(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 TIM_CCMode)
Initialize the TIMx Channel CCmode.
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel – The channel need to be set mode, which can be one of the following parameters TIM Channel.
TIM_CCMode –
CCx working mode which can be one of the following parameters:
TIM_CCMode_PWM
TIM_CCMode_Inputcapture
-
void RTIM_CCRxSet(RTIM_TypeDef *TIMx, u32 Compare, u16 TIM_Channel)
Set the TIMx Capture Compare X register value.
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
Compare – The value specifies pulsewidth, which is in the 0x00~0xFFFF range. Duty cycle = Compare / (ARR+1).
TIM_Channel – The channel to be set, which can be one of the following parameters TIM Channel.
Note
CCRx=0 will give 0% cycle pwm pulse.
CCRx>=TIM_Period there will be 100% pwm pulse.
-
void RTIM_CCStructInit(TIM_CCInitTypeDef *TIM_CCInitStruct)
Fill each TIM_CCInitStruct member with its default value.
- Parameters:
TIM_CCInitStruct – Pointer to a TIM_CCInitTypeDef structure which will be initialized.
-
void RTIM_CCxCmd(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 TIM_CCx)
Enable or disable the TIM Capture Compare Channel x.
- Parameters:
TIMx – The TIM peripheral with CCM capability. See IS_TIM_CCM_TIM macro.
TIM_Channel – Specifies the TIM Channel This parameter can be one of the following values TIM Channel
TIM_CCx –
Specifies the TIM Channel CCxE bit new state. This parameter can be one of the following values:
TIM_CCx_Enable
TIM_CCx_Disable
-
void RTIM_CCxInit(RTIM_TypeDef *TIMx, TIM_CCInitTypeDef *TIM_CCInitStruct, u16 TIM_Channel)
Initialize the TIMx Channel according to the specified parameters in the TIM_CCInitStruct.
- Parameters:
TIMx – The TIM peripheral with CCM capability. See IS_TIM_CCM_TIM macro.
TIM_CCInitStruct – Pointer to a TIM_CCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
TIM_Channel – The channel need to be initialized, which can be one of the following parameters TIM Channel
-
void RTIM_CCxPolarityConfig(RTIM_TypeDef *TIMx, u32 TIM_OCPolarity, u16 TIM_Channel)
Configure the TIMx channel x polarity.
- Parameters:
TIMx – The TIM peripheral with CCM capability. See IS_TIM_CCM_TIM macro.
TIM_OCPolarity –
Specifies the OCx Polarity This parameter can be one of the following values:
TIM_CCPolarity_High: Output Compare active high
TIM_CCPolarity_Low: Output Compare active low
TIM_Channel – Specifies the TIM Channel This parameter can be one of the following values TIM Channel
-
void RTIM_OCxPreloadConfig(RTIM_TypeDef *TIMx, u32 TIM_OCProtection, u16 TIM_Channel)
Enable or disable the TIMx peripheral Preload register on CCRx.
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_OCProtection –
New state of the TIMx peripheral Preload register This parameter can be one of the following values:
TIM_OCPreload_Enable: value is loaded in the active register at each update event.
TIM_OCPreload_Disable: new value is taken in account immediately
TIM_Channel – The channel need to be set, which can be one of the following parameters TIM Channel
-
void RTIM_SetOnePulseDefaultLevel(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 DefaultLevel)
Set the TIMx’s default level in one pulse mode.
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel – The channel to be set, which can be one of the following parameters TIM Channel.
DefaultLevel –
Specifies the OPM Mode Default Level. This parameter can be one of the following values:
TIMPWM_DefaultLevel_High
TIMPWM_DefaultLevel_Low
Note
Takes effect only in PWM output mode’s One-Pulse-Mode.
You must select TIM_OPMode_Single if you want to set One Pulse Mode, which makes the counter stop automatically at the next UEV.
-
void RTIM_SetOnePulseOutputMode(RTIM_TypeDef *TIMx, u32 TIM_OPMode, u32 TriggerPolarity)
Set the TIMx’s One Pulse Mode (output one pulse PWM mode).
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_OPMode –
Specifies the OPM Mode to be used. This parameter can be one of the following values:
TIM_OPMode_Single
TIM_OPMode_Repetitive
TriggerPolarity –
Specifies the OPM Mode Trigger Polarity. This parameter can be one of the following values:
TIM_OPMode_ETP_positive
TIM_OPMode_ETP_negative
TIM_OPMode_ETP_bothedge
Note
You must select TIM_OPMode_Single if you want to set One Pulse Mode, which makes the counter stop automatically at the next UEV.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
-
u32 RTIM_IsChannelCaptureEnabled(RTIM_TypeDef *TIMx, u16 TIM_Channel)
Get the TIMx Channel inputcapture mode enabled or not.
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel – Specifies the TIM Channel This parameter can be one of the following values TIM Channel
- Returns:
The capture enable status:
RTK_SUCCESS: Capture is enabled.
RTK_FAIL: Capture is not enabled.
Not supported.
Phase Sync Functions
-
u32 RTIM_GetChannelCountx(RTIM_TypeDef *TIMx, u16 TIM_Channel)
Get the TIMx Channel Counter value.
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel – Specifies the TIM Channel This parameter can be one of the following values TIM Channel
- Returns:
Counter Register value.
-
void RTIM_PSyncxCmd(RTIM_TypeDef *TIMx, u16 TIM_Channel, u8 NewState)
Enable or disable the TIMx Phase Sync function.
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel – Specifies the TIM Channel This parameter can be one of the following values TIM Channel
NewState – ENABLE/DISABLE.
-
void RTIM_PSyncxDir(RTIM_TypeDef *TIMx, u16 TIM_Channel, u8 TIM_SyncDir)
Set the TIMx Phase Sync X direction.
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel – The channel to be set, which can be one of the following parameters TIM Channel.
TIM_SyncDir – TIMPWM_PSync_Delay/TIMPWM_PSync_Ahead
-
u32 RTIM_PSyncxGet(RTIM_TypeDef *TIMx, u16 TIM_Channel)
Get the TIMx Phase Sync X value.
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel – The channel to be read, which can be one of the following parameters TIM Channel.
- Returns:
TIMx Phase Sync X value.
-
void RTIM_PSyncxPreloadConfig(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 TIM_PSyncProtection)
Enable or disable the preload function of TIMx phase sync register.
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel – The channel need to be set, which can be one of the following parameters TIM Channel
TIM_PSyncProtection –
TIMPWM_PSyncPreload_Enable/TIMPWM_PSyncPreload_Disable
TIMPWM_PSyncPreload_Enable: value is loaded in the active register at each update event.
TIMPWM_PSyncPreload_Disable: new value is taken in account immediately
-
void RTIM_PSyncxSet(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 TIM_SyncPhase)
Set the TIMx Phase Sync X value.
- Parameters:
TIMx – The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel – The channel to be set, which can be one of the following parameters TIM Channel.
TIM_SyncPhase – The phase sync value compared to CNT in TIM_CNT
Note
TIM_SyncPhase should always smaller than ARR value
Audio and Motor Functions
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
-
void PWM_DmaBurstSize(RTIM_TypeDef *TIMx, u32 msize)
Set DMA burstsize = 2^(n+1).
- Parameters:
TIMx – TIMx: where x only can be 5.
msize – Burstsize = 2^(n+1) it can be one of the GDMA Msize values.
Note
PWM burstsize must be same as GDMA burstsize.
-
void PWM_DmaCmd(RTIM_TypeDef *TIMx, u32 NewState)
PWM and GDMA handshake on or off.
- Parameters:
TIMx – TIMx: where x only can be 5.
NewState – New state of the handshake of GDMA-PWM. This parameter can be: ENABLE or DISABLE.
-
bool PWM_TXGDMA_Init(u32 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTXData, u32 Length)
Initialize GDMA peripheral.
- Parameters:
Index –
GDMA_InitStruct – Pointer to a GDMA_InitTypeDef structure that contains the configuration information for the GDMA peripheral.
CallbackData – GDMA callback data.
CallbackFunc – GDMA callback function.
pTXData – TX Buffer.
Length – TX Count.
- Returns:
The initialization result:
TRUE: Initialize successfully.
FALSE: Initialize failed.
-
void RTIM_AudStructInit(TIM_AudInitTypeDef *TIM_AudInitStruct)
Fill each TIM_AudInitStruct member with its default value.
- Parameters:
TIM_AudInitStruct – Pointer to a TIM_AudInitTypeDef structure which will be initialized.
-
void RTIM_AudioandMotorINTClear(RTIM_TypeDef *TIMx)
Clear the TIM5’s audio and motor interrupt bits.
- Parameters:
TIMx – Where x only can be 5.
-
void RTIM_AudioandMotorINTConfig(RTIM_TypeDef *TIMx, u32 TIM_IT, u32 NewState)
ENABLE/DISABLE the TIM5’s audio and motor interrupt bits.
- Parameters:
TIMx – Where x only can be 5.
TIM_IT –
Specifies the interrupt bit to configure. This parameter can be any combination of the following values:
TIM_IT_EMG_BRK_RELEASE: emergency brake release.
TIM_IT_FIFO_EMPTY: FIFO empty intr.
NewState – ENABLE or DISABLE
-
void RTIM_AudioandMotorSetBrakeLevel(RTIM_TypeDef *TIMx, u32 BRAKE_LEVEL, u16 TIM_Channel)
Set the TIM5’s brake status.
- Parameters:
TIMx – Where x only can be 5.
BRAKE_LEVEL –
Specifies the channel brake level. This parameter can be any of the following values:
PWM_OUTPUT_LOW
PWM_OUTPUT_HIGH
TIM_Channel – The channel need to be initialized, which can be one of the following parameters TIM Channel
-
void RTIM_AudioandMotorSetBrakeLevelUp(RTIM_TypeDef *TIMx)
For fifo empty, after configuring the brake state of all channels, set brake state up and the brake state will take effect.
- Parameters:
TIMx – Where x only can be 5.
-
void RTIM_AudioandMotorSetFIFOEmptyMode(RTIM_TypeDef *TIMx, u32 FIFO_EMPTY_MODE, u16 TIM_Channel)
Set the TIM5’s FIFO empty mode.
- Parameters:
TIMx – Where x only can be 5.
FIFO_EMPTY_MODE –
Specifies the FIFO empty mode. This parameter can be any of the following values:
PWM_FIFO_EMPTY_MAINTAIN
PWM_FIFO_EMPTY_BRAKE
TIM_Channel – The channel need to be initialized, which can be one of the following parameters TIM Channel
-
void RTIM_AudxInit(RTIM_TypeDef *TIMx, TIM_AudInitTypeDef *TIM_AudInitStruct, u16 TIM_Channel)
Initialize the TIMx Channel 0-5 according to the specified parameters in the TIM_AudInitStruct.
- Parameters:
TIMx – Where x only can be 5.
TIM_AudInitStruct – Pointer to a TIM_AudInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
TIM_Channel – The channel need to be initialized, which can be one of the following parameters TIM Channel
Note
TIM5 has 6 channels: TIM_Channel_0-5.
-
void RTIM_DeadzoneCmd(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 NewState)
Enable or disable deadzone control function.
- Parameters:
TIMx – Where x only can be 5.
TIM_Channel – The channel need to be configured, which can be one of the following parameters TIM Channel
NewState – New state of the deadzone control function. This parameter can be: ENABLE or DISABLE.
-
void RTIM_EmgBrkDbcCmd(RTIM_TypeDef *TIMx, u32 NewState)
Enable/Disable debounce function of TIM emergency brake.
- Parameters:
TIMx – TIMx: where x only can be 5.
NewState – New state of the TIMx peripheral. This parameter can be: ENABLE or DISABLE.
-
u32 RTIM_GetAudioandMotorINTStatus(RTIM_TypeDef *TIMx, u32 TIM_IT_AUD_FLAG)
Clear the TIM5’s audio and motor interrupt bits.
- Parameters:
TIMx – Where x only can be 5.
TIM_IT_AUD_FLAG –
Specifies the TIM audio and motor interrupt flag to check. This parameter can be one of the following values:
TIM_IT_EMG_BRK_RELEASE_FLAG: emergency brake release intr flag.
TIM_IT_FIFO_EMPTY_FLAG: FIFO empty intr flag.
- Returns:
The new state of the TIM_IT:
TRUE: The specified TIM interrupt has occurred.
FALSE: The specified TIM interrupt has not occurred.
-
void RTIM_ResetFIFO(RTIM_TypeDef *TIMx)
Reset FIFO.
- Parameters:
TIMx – TIMx: where x only can be 5.
-
void RTIM_SetDeadzoneMAXChnID(RTIM_TypeDef *TIMx)
Set the max deadzone_tim’channel id.
- Parameters:
TIMx – Where x only can be 5.
-
void RTIM_SetDeadzoneTim(RTIM_TypeDef *TIMx, u32 deadzone_tim, u16 TIM_Channel)
Set deadzone_tim.
- Parameters:
TIMx – Where x only can be 5.
deadzone_tim – It means delay cycles on positive edge, it’s count by 40M.
TIM_Channel – The channel need to be initialized, which can be one of the following parameters TIM Channel
-
void RTIM_SetEmgBrkDbcCnt(RTIM_TypeDef *TIMx, u16 Dbc_Cnt)
Set debounce counter under XTAL40M to realize signal deglitch.
- Parameters:
TIMx – TIMx: where x only can be 5.
Dbc_Cnt – Debounce counter to be set.
Note
Dbc_Cnt = 0 means debounce function is disabled.
-
void RTIM_SetEmgBrkLevel(RTIM_TypeDef *TIMx, u32 EMG_BRK_LEVEL, u16 TIM_Channel)
Set emergency brake level.
- Parameters:
TIMx – TIMx: where x only can be 5.
EMG_BRK_LEVEL – It means when emergency brake is triggered, the PWM output level. This parameter can be: PWM_EMGBRK_OUTPUT_LOW or PWM_EMGBRK_OUTPUT_HIGH.
TIM_Channel – The channel need to be initialized, which can be one of the following parameters TIM Channel
-
void RTIM_SetEmgBrkPolarity(RTIM_TypeDef *TIMx, u32 EMG_BRK_POLARITY)
Set emergency brake trigger polarity.
- Parameters:
TIMx – Where x only can be 5.
EMG_BRK_POLARITY –
Emergency brake trigger polarity. This parameter can be one of the following values:
PWM_EMGBRK_TRI_POL_HIHG: High level to trigger emergency braking
PWM_EMGBRK_TRI_POL_LOW: Low level to trigger emergency braking
-
void RTIM_SetFIFOFirstLevel(RTIM_TypeDef *TIMx, u16 FIFO_Level)
When writing a FIFO for the first time, you should configure the level of FIFO before FIFO to be read. Generally greater than the number of chn working in FIFO.
- Parameters:
TIMx – TIMx: where x only can be 5.
FIFO_Level – The level of FIFO before FIFO to be read.
-
void RTIM_SetPadOutMode(RTIM_TypeDef *TIMx, u32 Channel, u32 Mode)
Set the PAD output mode for the specified channel. Used to select the correspondence between ch and output pad.
- Parameters:
TIMx – Where x only can be 5.
Channel – The index of the channel, range [0, PWM_CHAN_MAX-1].
Mode –
The PAD output mode selection. This parameter can be one of the following values:
PWM_CHANNEL_OUTPUT_TWOPAD: Two chns control two output pad.
PWM_CHANNEL_OUTPUT_ONEPAD: One chn controls two output pad.
-
void RTIM_SetPhaseSel(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 Phase)
Select output phase in audio/motor scenario.
- Parameters:
TIMx – Where x only can be 5.
TIM_Channel – The channel need to be configured, which can be one of the following parameters TIM Channel
Phase –
Output phase selection. This parameter can be one of the following values:
0: opposite phase
1: same phase
Mbed API
MBED_PWM Exported Types
Structure Type
-
typedef struct pwmout_s pwmout_t
Typedef struct pwmout_s to pwmout_t.
MBED_PWM Exported Functions
-
void pwmout_free(pwmout_t *obj)
Deinitialize the PWM device of the specified channel.
- Parameters:
obj – PWM object defined in application software.
Note
If all channels are released, PWMTIMER will also be disabled.
-
void pwmout_init(pwmout_t *obj, PinName pin)
Initialize PWM channel output according to the specified pin.
- Parameters:
obj – PWM object defined in application software.
pin – Pin name of corresponding PWM channel to be set.
Note
Default period: 1638us.
Default pulse width: 102us.
Default duty cycle: 6.227%.
-
void pwmout_period(pwmout_t *obj, float seconds)
Set the period of the specified channel in seconds.
- Parameters:
obj – PWM object defined in application software.
seconds – The period value to be set in seconds(s).
-
void pwmout_period_ms(pwmout_t *obj, int ms)
Set the period of the specified channel in milliseconds.
- Parameters:
obj – PWM object defined in application software.
ms – The period value to be set in milliseconds(ms).
-
void pwmout_period_us(pwmout_t *obj, int us)
Set the period of the specified channel in microseconds.
- Parameters:
obj – PWM object defined in application software.
us – The period value to be set in microseconds(us).
-
void pwmout_pulsewidth(pwmout_t *obj, float seconds)
Set the pulse width of the specified channel in seconds.
- Parameters:
obj – PWM object defined in application software.
seconds – The pulse width value to be set in seconds(s).
-
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
Set the pulse width of the specified channel in milliseconds.
- Parameters:
obj – PWM object defined in application software.
ms – The pulse width value to be set in milliseconds(ms).
-
void pwmout_pulsewidth_us(pwmout_t *obj, int us)
Set the pulse width of the specified channel in microseconds.
- Parameters:
obj – PWM object defined in application software.
us – The pulse width value to be set in microseconds(us).
-
float pwmout_read(pwmout_t *obj)
Get the duty cycle of the specified channel.
- Parameters:
obj – PWM object defined in application software.
- Returns:
Duty cycle of the specified channel, in the range [0.0, 1.0].
-
void pwmout_set_polarity(pwmout_t *obj, int polarity)
Set the polarity of the specified PWM channel.
- Parameters:
obj – PWM object defined in application software.
polarity –
This parameter can be one of the following values:
0: Output is LOW when timer count < set value.
1: Output is HIGH when timer count < set value (default).
Attention
Configure polarity after setting duty cycle or pulse width.
-
void pwmout_start(pwmout_t *obj)
Enable the specified channel to output PWM.
- Parameters:
obj – PWM object defined in application software.
Capture Timer
Features
16-bit up-counter
16-bit programmable prescaler
Preloadable auto-reload register
Operation modes:
Pulse width measurement
Pulse counting within configurable window
Application Examples
SDK provides raw implementation examples for Capture Timer:
Path:
{SDK}\example\peripheral\raw\Timer\{demo}Demonstrates direct register-level capture control
Key implementations:
raw_tim_pulse_width_32k: Pulse width measurement
raw_tim_pulse_num_32k: Pulse counting implementation
Note
Check example’s README.md for supported chip information.
Raw API
CAPTIMER Exported Constants
TIM CC Pulse Mode
/* Input pulse mode: measure pulse width. */
#define TIM_CCMode_PulseWidth ((u32)0x00000000)
/* Input pulse mode: count pulse number. */
#define TIM_CCMode_PulseNumber ((u32)0x10000000)
/* Check if TIM pulse mode value is valid. */
#define IS_TIM_CC_PULSEMODE (((MODE) == TIM_CCMode_PulseWidth) || \
((MODE) == TIM_CCMode_PulseNumber))
/* Maximum CCR value mask (16-bit). */
#define TIM_CCMode_CCR ((u32)0x0000FFFF)
/* Check if pulse width compare value fits in CCR. */
#define IS_TIM_CC_PULSEWIDTH ((Compare) <= TIM_CCMode_CCR)
TIM Capture Type
/* Check if peripheral is an input pulse capture timer. */
#define IS_TIM_INPULSE_TIM (((PERIPH) == TIM9) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is an input pulse capture timer. */
#define IS_TIM_INPULSE_TIM (((PERIPH) == TIM9) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is an input pulse capture timer. */
#define IS_TIM_INPULSE_TIM (((PERIPH) == TIM9) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is an input pulse capture timer. */
#define IS_TIM_INPULSE_TIM (((PERIPH) == TIM9) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is an input pulse capture timer. */
#define IS_TIM_INPULSE_TIM (((PERIPH) == TIM9) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is an input pulse capture timer. */
#define IS_TIM_INPULSE_TIM (((PERIPH) == TIM9) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is an input pulse capture timer. */
#define IS_TIM_INPULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is an input pulse capture timer. */
#define IS_TIM_INPULSE_TIM (((PERIPH) == TIM6) || \
((PERIPH) == TIM6_S))
CAPTIMER Exported Functions
-
u32 RTIM_CCRxGet(RTIM_TypeDef *TIMx, u16 TIM_Channel)
Get the TIMx Capture Compare X register value.
- Parameters:
TIMx – The TIM peripheral with CCM capability. See IS_TIM_CCM_TIM macro.
TIM_Channel – The channel to be read, which can be one of the following parameters TIM Channel.
- Returns:
Capture Compare x Register value.
Note
If you want to get pulse width of PWM, remember to plus 1 to the return value of this function.
Debug Timer
Features
Dual clock sources:
XTAL40M: 1μs resolution (1MHz from 40MHz crystal)
SDM32K: ~30.5μs per period (32768 Hz); since the counter has no fractional part, each tick increments the count by 31μs (an inherent hardware rounding error)
Sleep mode persistence
A lock-free counter: atomic counter access for multi-core systems
Raw API
DEBUGTIMER Exported Constants
Debug Timer Clock Source
/* Select XTAL as clock source */
#define DTIM_CLK_XTAL 0
/* Select 32K as clock source */
#define DTIM_CLK_32K 1
DEBUGTIMER Exported Functions
-
u32 DTimer_AtomGet(void)
Get the Debug Timer atom counter value. Reading this register does not increment the atom counter.
- Returns:
Current atom counter value.
-
u32 DTimer_AtomIncGet(void)
Get the Debug Timer atom counter value and trigger auto-increment. Reading this register auto-increments the atom counter by 1.
- Returns:
Atom counter value after auto-increment.
-
void DTimer_AtomSet(u32 NewValue)
Set the Debug Timer atom counter value.
- Parameters:
NewValue – New atom counter value.
-
void DTimer_Cmd(bool Newstatus)
Enable or disable the Debug Timer peripheral The debug timer is a free-running timer that works at 1 MHz.
- Parameters:
Newstatus – New state of the Debug Timer peripheral. This parameter can be: ENABLE or DISABLE.
-
u32 DTimer_ScratchGet(void)
Get the Debug Timer scratch register value.
- Returns:
Current scratch register value.
-
void DTimer_ScratchSet(u32 NewValue)
Set the Debug Timer scratch register value.
- Parameters:
NewValue – New scratch register value.
-
u32 DTimestamp_Get(void)
Get the Debug Timer u32 current counter.
- Returns:
Current u32 counter value.
-
void DTimestamp_Set(u32 NewValue)
Set the Debug Timer current counter.
- Parameters:
NewValue – New counter value.
-
void DTimer_CLK(u8 DTim_speed)
Select clock for timestamp, which works at 1MHz by default.
- Parameters:
DTim_speed –
Speed of debugtimer counter.
0: OSC32KHz.
1: 1MHz, which is divided from XTAL40MHz.
FUNCTION_REF=DTimestamp_Set
FUNCTION_REF=DTimer_CLK
FUNCTION_REF=DTimestamp_Set
FUNCTION_REF=DTimer_CLK
FUNCTION_REF=DTimestamp_Set
FUNCTION_REF=DTimer_CLK
FUNCTION_REF=DTimestamp_Set
FUNCTION_REF=DTimer_CLK
FUNCTION_REF=DTimestamp_Set
FUNCTION_REF=DTimer_CLK
-
void DTimestamp_Set(u64 NewValue)
Set the Debug Timer u64 current counter.
- Parameters:
NewValue – New u64 counter value.
-
u32 DTimesPassedtime32_Get(u32 OldTime)
Get the u32 elapsed time.
- Parameters:
OldTime – Old timestamp value for comparison.
- Returns:
Elapsed timer ticks since OldTime.
-
u64 DTimesPassedtime64_Get(u64 OldTime)
Get the u64 elapsed time.
- Parameters:
OldTime – Old timestamp value for comparison.
- Returns:
Elapsed timer ticks since OldTime.
-
u64 DTimestamp64_Get(void)
Get the Debug Timer u64 current counter.
- Returns:
Current u64 counter value.
FUNCTION_REF=DTimestamp_Set_RTL8721F
FUNCTION_REF=DTimesPassedtime32_Get
FUNCTION_REF=DTimesPassedtime64_Get
FUNCTION_REF=DTimestamp64_Get
PMC Timer
Features
RTL8721Dx:
2 sets of PMC Timers (each set contains 4 counters):
Sleep countdown counter
Deepsleep countdown counter
Wakeup counter
Reserved counter
32-bit width down counter (stops automatically when reaching 0)
Configurable interrupt generation upon reaching 0
SDM32K clock source
Timer countdown value can be reset during operation
RTL8720E:There is no PMC timer
RTL8710E:There is no PMC timer
RTL8726E:There is no PMC timer
RTL8713E:There is no PMC timer
RTL8730E:There is no PMC timer
RTL8721F:
2 sets of PMC Timers (each set contains 4 counters):
Sleep countdown counter
Deepsleep countdown counter
Wakeup counter
Reserved counter
32-bit width down counter (stops automatically when reaching 0)
Configurable interrupt generation upon reaching 0
SDM32K clock source
Timer countdown value can be reset during operation
RTL8720F:
2 sets of PMC Timers (each set contains 4 counters):
Sleep countdown counter
Deepsleep countdown counter
Wakeup counter
Reserved counter
32-bit width down counter (stops automatically when reaching 0)
Configurable interrupt generation upon reaching 0
SDM32K clock source
Timer countdown value can be reset during operation
RTL8735C:
4 sets of PMC Timers:
TIMER0 ~ TIMER3
32-bit width down counter (stops automatically when reaching 0)
Configurable interrupt generation upon reaching 0
SDM32K clock source
Compare mode: Timer set value takes effect only when greater than current counter value
Raw API
PMCTIMER Exported Constants
PMCTIMER Device Config
/* PMC timer device instance for CM4/KM4 core. */
#define PMC_TIMER_DEV PMCTIMER_DEV0
/* PMC timer device instance for CM0/KM0 core. */
#define PMC_TIMER_DEV PMCTIMER_DEV1
/* PMC timer IRQ number for CM4/KM4 core. */
#define PMC_TIMER_IRQ PMC_TIMER0_IRQ
/* PMC timer IRQ number for CM0/KM0 core. */
#define PMC_TIMER_IRQ PMC_TIMER1_IRQ
/* PMC timer interrupt priority. */
#define PMC_TIMER_INT_PRIO INT_PRI_LOWEST
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
/* PMC timer device instance for CM4/KM4TZ core. */
#define PMC_TIMER_DEV PMCTIMER_DEV0
/* PMC timer device instance for CM4/KM4NS core. */
#define PMC_TIMER_DEV PMCTIMER_DEV1
/* PMC timer IRQ number for CM4/KM4TZ core. */
#define PMC_TIMER_IRQ PMC_TIMER0_IRQ
/* PMC timer IRQ number for CM4/KM4NS core. */
#define PMC_TIMER_IRQ PMC_TIMER1_IRQ
/* PMC timer interrupt priority. */
#define PMC_TIMER_INT_PRIO INT_PRI_LOWEST
/* PMC timer device instance for CM4/KM4NS core. */
#define PMC_TIMER_DEV PMCTIMER_DEV0
/* PMC timer device instance for CM4/KM4TZ core. */
#define PMC_TIMER_DEV PMCTIMER_DEV1
/* PMC timer IRQ number for CM4/KM4NS core. */
#define PMC_TIMER_IRQ PMC_TIMER0_IRQ
/* PMC timer IRQ number for CM4/KM4TZ core. */
#define PMC_TIMER_IRQ PMC_TIMER1_IRQ
/* PMC timer interrupt priority. */
#define PMC_TIMER_INT_PRIO INT_PRI_LOWEST
PMCTIMER Index
/* PMC timer index for system active time during sleep. */
#define PMC_SLEEP_TIMER 0
/* PMC timer index for system active time during deep sleep. */
#define PMC_DSLP_TIMER 1
/* PMC timer index for setting wakeup time during sleep. */
#define PMC_WAKEUP_TIMER 2
/* Reserved PMC timer index. */
#define PMC_RSVD_TIMER 3
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
/* PMC timer index for system active time during sleep. */
#define PMC_SLEEP_TIMER 0
/* PMC timer index for system active time during deep sleep. */
#define PMC_DSLP_TIMER 1
/* PMC timer index for setting wakeup time during sleep. */
#define PMC_WAKEUP_TIMER 2
/* Reserved PMC timer index. */
#define PMC_RSVD_TIMER 3
/* PMC timer index for system active time during sleep. */
#define PMC_SLEEP_TIMER 0
/* PMC timer index for system active time during deep sleep. */
#define PMC_DSLP_TIMER 1
/* PMC timer index for setting wakeup time during sleep. */
#define PMC_WAKEUP_TIMER 2
/* Reserved PMC timer index. */
#define PMC_RSVD_TIMER 3
PMCTIMER Valid Check
/* Bit mask for timer x configuration valid status. */
#define PMCT_BIT_TIM_VALIDx ((u32)(0x00000001 << (8 + x)))
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
/* Bit mask for timer x configuration valid status. */
#define PMCT_BIT_TIM_VALIDx ((u32)(0x00000001 << (8 + x)))
/* Bit mask for timer x configuration valid status. */
#define PMCT_BIT_TIM_VALIDx ((u32)(0x00000001 << (8 + x)))
PMCTIMER Reset
/* Bit mask to pulse reset timer x. */
#define PMCTRESET_BIT_TIMERx ((u32)(0x00000001 << (28 + x)))
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
/* Bit mask to pulse reset timer x. */
#define PMCTRESET_BIT_TIMERx ((u32)(0x00000001 << (28 + x)))
/* Bit mask to pulse reset timer x. */
#define PMCTRESET_BIT_TIMERx ((u32)(0x00000001 << (28 + x)))
PMCTIMER Exported Functions
-
u32 PMCTimerCnt_Get(PMCTIMER_TpyeDef *PMC_TIMER, u32 Timer_Idx)
Get the pmc timer current Counter value.
- Parameters:
PMC_TIMER – The pointer of PMC TIMER DEV.
Timer_Idx – Timer index in PMC TIMER DEV. This parameter can be: 0 ~ 3.
- Returns:
Current counter value.
-
void PMCTimerCnt_Reset(PMCTIMER_TpyeDef *PMC_TIMER, u32 Timer_Idx)
Reset the pmc timer count down value.
- Parameters:
PMC_TIMER – The pointer of PMC TIMER DEV.
Timer_Idx – Timer index in PMC TIMER DEV. This parameter can be: 0 ~ 3.
-
void PMCTimerCnt_Set(PMCTIMER_TpyeDef *PMC_TIMER, u32 Timer_Idx, u32 NewValue)
Set the pmc timer count down value.
- Parameters:
PMC_TIMER – The pointer of PMC TIMER DEV.
Timer_Idx – Timer index in PMC TIMER DEV. This parameter can be: 0 ~ 3.
NewValue – New counter.
-
void PMCTimer_Cmd(PMCTIMER_TpyeDef *PMC_TIMER, u32 Timer_Idx, bool NewState)
Enable or disable the pmc timer counter The pmc timer group contains 4 timers for each group, all runs at 32k.
- Parameters:
PMC_TIMER – The pointer of PMC TIMER DEV.
Timer_Idx – Timer index in PMC TIMER DEV. This parameter can be: 0 ~ 3.
NewState – New state of the PMC timer counter. This parameter can be: ENABLE or DISABLE.
-
void PMCTimer_INTClear(PMCTIMER_TpyeDef *PMC_TIMER, u32 Timer_Idx)
Clear the pmc timer’s interrupt bits.
- Parameters:
PMC_TIMER – The pointer of PMC TIMER DEV.
Timer_Idx – Timer index in PMC TIMER DEV. This parameter can be: 0 ~ 3.
-
void PMCTimer_INTConfig(PMCTIMER_TpyeDef *PMC_TIMER, u32 Timer_Idx, u32 NewState)
ENABLE/DISABLE the pmc timer’s interrupt bits.
- Parameters:
PMC_TIMER – The pointer of PMC TIMER DEV.
Timer_Idx – Timer index in PMC TIMER DEV. This parameter can be: 0 ~ 3.
NewState – ENABLE or DISABLE.
-
u32 PMCTimer_Valid_Check(PMCTIMER_TpyeDef *PMC_TIMER, u32 Timer_Idx)
Check pmctimer current state.
- Parameters:
PMC_TIMER – The pointer of PMC TIMER DEV.
Timer_Idx – Timer index in PMC TIMER DEV. This parameter can be: 0 ~ 3.
- Returns:
The validation result:
TRUE: valid
FALSE: not valid
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
FUNCTION_REF=PMCTimerCnt_Get
FUNCTION_REF=PMCTimerCnt_Reset
FUNCTION_REF=PMCTimerCnt_Set
FUNCTION_REF=PMCTimer_Cmd
-
void PMCTimer_CompCmd(PMCTIMER_TpyeDef *PMC_TIMER, u32 Timer_Idx, u32 NewState)
Enable or disable the comparison function of pmctimer.
- Parameters:
PMC_TIMER – The pointer of PMC TIMER DEV.
Timer_Idx – Timer index in PMC TIMER DEV.
NewState – This parameter can be: ENABLE or DISABLE.
FUNCTION_REF=PMCTimer_INTClear
FUNCTION_REF=PMCTimer_INTConfig
-
u32 PMCTimer_INT_Hdl(void *Data)
PMC timer interrupt handler for wakeup timer.
- Parameters:
Data – Unused.
- Returns:
Always returns TRUE.
-
void PMCTimer_Init(void)
Initialize PMC timer: register interrupt and enable wakeup timer.
-
void PMCTimer_Reset(void)
Reset the PMC wakeup timer counter.
FUNCTION_REF=PMCTimer_Valid_Check
FUNCTION_REF=PMCTimerCnt_Get
FUNCTION_REF=PMCTimerCnt_Reset
FUNCTION_REF=PMCTimerCnt_Set
FUNCTION_REF=PMCTimer_Cmd
FUNCTION_REF=PMCTimer_CompCmd
FUNCTION_REF=PMCTimer_INTClear
FUNCTION_REF=PMCTimer_INTConfig
FUNCTION_REF=PMCTimer_INT_Hdl
FUNCTION_REF=PMCTimer_Init
FUNCTION_REF=PMCTimer_Reset
FUNCTION_REF=PMCTimer_Valid_Check