A2C

Supported Chip[ RTL8721F ]

Overview

A2C (Automotive 2-wire Connection) is a real-time serial communication controller designed for high-reliability automotive and industrial application scenarios. This module implements the data link layer protocol of the ISO 11898-1 standard (excluding ISO 11898-1 FD), supporting multi-master communication, non-destructive arbitration, and robust error detection mechanisms. A2C features hardware-level automation capabilities (such as automatic retransmission, automatic reply, FIFO, and DMA), designed to minimize CPU load to the greatest extent.

Features

A2C supports the following features:

• Core Protocol

  • Compatible with ISO 11898-1 standard, supporting 11-bit standard frames and 29-bit extended frames

  • Supports 3-point sampling (used at low bit rates)

• Transmission and Reception

  • Supports automatic retransmission after transmission failure

  • Supports hardware automatic reply to remote frames

  • Supports recording reception timestamps

  • Supports time-triggered message transmission

• Buffer and Memory Management

  • Hardware supports 16 message buffers for temporary message storage

  • Message buffers can be flexibly configured for transmission or reception

  • Supports using message buffers No. 12 to No. 15 as a FIFO

  • Supports DMA transfer during reception

• Low Power

  • Supports low-power wake-up

• Debug and Error Management

  • Supports internal and external loopback modes; external loopback mode allows capturing protocol frames for analysis

  • Supports silence mode for bus monitoring

  • Supports various error interrupts, such as bit error, stuff error, form error, etc.

A2C Physical Layer

Topology

As a protocol controller, the A2C module requires an external transceiver to convert logical levels to differential signals. The physical layer design directly determines the communication distance and anti-interference capability. Depending on the application scenario, A2C supports two typical network topologies:

1. High-Speed Closed-Loop Network (ISO 11898-2)

Suitable for high-speed (standard A2C up to 1Mbps), short-distance (<40m) communication. Both ends of the bus must be connected with 120Ω termination resistors to suppress signal reflection.

2. Low-Speed Open-Loop Network (ISO 11898-3)

Suitable for low-speed (up to 125Kbps), long-distance (<1km) communication.

Physical Signals

The TX/RX signals between the A2C controller and the transceiver are normal logic levels, where 0 represents a low level and 1 represents a high level. The signals on the bus lines H/L from the transceiver use differential signal transmission.

• When an A2C node needs to transmit data, the controller sends the binary code via TX to the transceiver. The transceiver converts this normal logic level into a differential signal and transmits it to the bus network via the differential lines H and L.

• When an A2C node needs to receive data, the transceiver converts the differential signal received on H and L into a normal logic level and outputs it to the A2C controller via RX.

Differential signal transmission requires two signal lines. The voltage amplitudes on the two lines are the same but opposite in phase. Their difference is used to represent logic levels 0 and 1. The figure below shows a set of standard differential signals and their difference.

Compared to single-ended signal transmission, differential signal transmission has the following characteristics:

• Strong Anti-Interference Ability: When noise interference occurs, the noise couples to both signal lines simultaneously. The final signal difference cancels out, suppressing external common-mode noise.

• Low Electromagnetic Radiation: Since the signal lines are twisted pair, the magnetic field polarities are opposite, canceling out external radiation. This results in less interference with surrounding circuits and easier passing of EMC (Electromagnetic Compatibility) tests.

• Precise Timing Positioning: Single-ended signal logic switching depends on a fixed reference voltage (e.g., Vcc/2), which is highly susceptible to power supply fluctuations. The logic switching point of differential signals is the crossing point of the two signal lines. The detection of the crossing point is unaffected by reference voltage drift, greatly reducing timing jitter.

• No Common Ground Required: Single-ended signals must reference GND. Inconsistent reference voltages at both ends can easily lead to signal misjudgment. Differential signals only concern the voltage difference and do not require a common ground.

Note

The actual differential signal transmitted on the line is affected by the real electromagnetic environment, transmission distance, etc., causing deformation in signal shape, amplitude, and phase.

Differential Signal Specifications

The ISO 11898 standard specifies the differential signals as follows:

ISO 11898-2 (High-Speed) Physical Layer Voltage Specifications

Signal	Recessive (Logic 1)			Dominant (Logic 0)
	Min	Typ	Max	Min	Typ	Max
A2C_High (V)	2.0	2.5	3.0	2.75	3.5	4.5
A2C_Low (V)	2.0	2.5	3.0	0.5	1.5	2.25
High-Low Diff (V)	-0.5	0	0.05	1.5	2.0	3.0

ISO 11898-3 (Low-Speed) Physical Layer Voltage Specifications

Signal	Recessive (Logic 1)			Dominant (Logic 0)
	Min	Typ	Max	Min	Typ	Max
A2C_High (V)	1.6	1.75	1.9	3.85	4.0	5.0
A2C_Low (V)	3.10	3.25	3.4	0	1.0	1.15
High-Low Diff (V)	-0.3	-1.5	/	0.3	3.0	/

Taking the ISO 11898-2 high-speed physical layer voltage specification as an example:

• When representing Logic 1 (Recessive Level), the voltages on both H and L lines are 2.5V, with a voltage difference of 0V.

• When representing Logic 0 (Dominant Level), the voltage on the H line is 3.5V, and the voltage on the L line is 1.5V, with a voltage difference of 2V.

For example, when the transceiver wants to transmit a logic level 0 from the controller, it drives the H signal line to 3.5V and the L signal line to 1.5V, thereby outputting a dominant level (logic 0).

Tip

The dominant and recessive levels defined in ISO 11898 have a “Wired-AND” characteristic similar to the I2C bus (any node outputting a low level pulls the bus level low). If two A2C communication nodes transmit simultaneously, with one outputting a recessive level and the other a dominant level, the bus will present a dominant level (Logic 0). This is the fundamental mechanism for arbitration during node communication.

Since the physical layer has only one pair of differential lines and can only represent one signal at a time, communication is half-duplex for the node; transmitting and receiving data cannot occur simultaneously. In the entire communication network, because the bus is shared, only one communication node can transmit signals at any given time (except during the arbitration phase where multiple nodes can transmit simultaneously), while other nodes can only receive.

A2C Protocol Layer

Protocol Frame Format Overview

The protocol layer defines the encapsulation format of data on the bus. The A2C protocol mainly includes the following frame formats:

ISO 11898-1 Frame Formats

Frame Type	Main Purpose	Transmission Timing/Constraint	Key Features
Data Frame	Transmits actual data	Actively sent when the bus is idle Subject to arbitration mechanism (lower ID has higher priority) Automatic retransmission on arbitration failure (configurable)	Structure: SOF + ID + Control + Data + CRC + ACK + EOF Capacity: 0~8 Bytes ACK: Sender sends recessive bit; receiver sends dominant bit to acknowledge
Remote Frame	Requests data for a specific ID	Sent when the bus is idle (subject to arbitration) Target node must support and be configured to respond	Structure: Similar to Data Frame, but RTR=1 and no Data Field Note: Introduces latency and consumes bandwidth
Error Frame	Notifies global bus error	Sent Immediately: Triggered immediately upon error detection, not waiting for bus idle Destroys the frame currently being transmitted	Structure: Error Flag (6 bits) + Error Delimiter (8 bits) Active Error: Sends 6 dominant bits (violates bit stuffing rule) Passive Error: Sends 6 recessive bits Trigger: Bit, Stuff, CRC, Form, ACK errors
Overload Frame	Delays the next frame reception (gives receiver breathing time)	When a dominant level is detected at the last bit of EOF, the last bit of Error Delimiter, the last bit of Overload Delimiter, or the 1st/2nd bit of Intermission Automatically handled by controller hardware; application layer cannot send actively	Structure: Similar to Active Error Frame (6 dominant bits) Status: Modern CAN controllers are very fast and rarely need this frame
Interframe Space (Intermission)	Physically separates consecutive frames	Mandatory time gap No node can send Data/Remote Frames during this period	Composition: Intermission (3 recessive bits) + Bus Idle Special Case: After Error/Overload Frame, sends Delimiter (8 bits) first, then enters Intermission

Data Frame

The Data Frame is the most common type used for data transmission between nodes on the A2C bus.

Standard Data Frames use an 11-bit identifier, formatted as follows:

Standard Data Frame

Extended Data Frames use a 29-bit identifier (11-bit Base ID + 18-bit Extension ID) for larger networks, formatted as follows:

Extended Data Frame

Key Field Analysis

The frame structure starts with a dominant bit (Logic 0) and ends with consecutive recessive bits (Logic 1). A complete Data Frame consists of seven fields: Start of Frame, Arbitration Field, Control Field, Data Field, CRC Field, ACK Field, and End of Frame.

Data Frame Structure Definition

Field	Composition/Bit Definition	Technical Description
Start of Frame (SOF)	1 bit (Dominant)	Identifies the start of the frame, used for hard synchronization.
Arbitration Field	ID, RTR, IDE, SRR	ID: 11-bit (Standard) or 29-bit (Extended), determines priority. Smaller ID number means higher priority. RTR: Remote Transmission Request. Distinguishes Data Frame (0) from Remote Frame (1). Data Frame has higher priority than Remote Frame. IDE: Identifier Extension. Distinguishes Standard Frame (0) from Extended Frame (1). Standard Frame has higher priority than Extended Frame. Arbitration Mechanism: Wired-AND logic, dominant level takes precedence.
Control Field	DLC (4 bits), r0/r1	DLC: Data Length Code, indicates number of data bytes (0-8). r0/r1 are reserved bits.
Data Field	0-8 Bytes	Payload, MSB first.
CRC Field	CRC Sequence (15 bits) + Delimiter	Hardware calculates checksum. Delimiter is a recessive bit.
ACK Field	ACK Slot + Delimiter	Sender sends recessive; receiver pulls low to dominant to acknowledge.
End of Frame (EOF)	7 bits (Recessive)	Identifies the end of the frame, no bit stuffing.

Remote Frame

Used by a receiving node to request data from a transmitting node. The main difference from a Data Frame is: RTR bit is Recessive (1) and there is no Data Field. Formats are shown in Standard Remote Frame and Extended Remote Frame.

Standard Remote Frame

Extended Remote Frame

Error Frame

Sent when a node detects a bus error. It consists of an Error Flag (6 bits) and an Error Delimiter (8 bits). Figures Active Error Frame and Passive Error Frame show the two frame formats. Since different nodes may detect errors and send error frames at different time points, the error flags on the bus may superimpose, resulting in an error flag duration between 6 and 12 bits. Refer to Error Detection and Management for details.

Active Error Frame

Passive Error Frame

Overload Frame

Sent when a receiving node is not ready to receive the next frame data, used to insert extra delay between frames. The format is as follows:

Refer to Sending Overload Frame for timing details.

Interframe Space

Used to separate Data Frames and Remote Frames. The format is as follows:

• Data Frames and Remote Frames can be separated from any preceding frame (Data, Remote, Error, Overload) by inserting an Interframe Space.

• Interframe Space cannot be inserted before Overload Frames and Error Frames.

Where:

• Intermission: After the previous frame (EOF or Error Delimiter) ends, the bus must maintain a recessive level (1) for 3 bits.

• Suspension: When an error occurs:

  • If a node is in Error Active state, after sending a frame and the 3-bit Intermission, it can immediately contend for the bus to send the next frame.

  • If a node frequently errors and enters Error Passive state, the protocol requires it to wait an additional 8 recessive bits (Suspension) after sending a frame.

• Bus Idle: If the above phases are completed and there is still no data on the bus, it enters “Bus Idle” state. The bus remains recessive (1). Any node wishing to send data can pull the level low (0) at any time to start transmission (i.e., send SOF bit).

Bit Timing and Synchronization

A2C uses asynchronous serial communication, requiring both sender and receiver to agree on a baud rate. To solve clock drift and transmission delay issues, ISO 11898 defines a bit timing decomposition and synchronization mechanism based on Time Quantum (Tq).

Bit Decomposition

According to the ISO 11898-1 standard, the timing of one bit on the bus is divided into four segments:

The minimum unit of a decomposed bit is the Time Quantum (Tq), with size prescaler/core clk, where core_clk is the A2C source clock input. A complete bit generally consists of 8-25 Tqs.

• Synchronization Segment (Sync_Seg): Used to determine if the signal edge on the bus falls exactly within the Sync_Seg. If so, the communication node is synchronized with the bus.

• Propagation Segment (Prop_Seg): Used to compensate for physical transmission delay on the lines and internal transceiver delay. Electrical signals take time to propagate. For example, during arbitration, if this time is not reserved, Node A might sample before its signal reaches Node B, causing a sampling error.

• Phase Buffer Segment 1 (Phase_Seg1): Elastic buffer before sampling, located immediately before the sample point. If Sync_Seg of the current bit detects a late signal edge (after Sync_Seg), meaning the current bit arrived late, this segment is extended to prevent premature sampling.

• Phase Buffer Segment 2 (Phase_Seg2): Elastic buffer after sampling. If Sync_Seg of the current bit detects an early signal edge, meaning the current bit ends too early, this segment is shortened so the next bit can be sampled correctly.

Sample Point is located at the end of Phase_Seg1. By controlling segment lengths, the sample point position can be shifted for accurate sampling.

The table below gives reference ranges for each segment.

Minimum Configuration Range of Time Segments

Parameter	Range	Description
Bit Rate Prescaler (Prescaler)	1 ~ 32	Tq = prescaler / core_clk
Sync_Seg	1 Tq (Fixed)	Synchronizes A2C nodes on the bus.
Prop_Seg	1 ~ 8 Tqs	Compensates for physical delay in the network.
Phase_Seg1	1 ~ 8 Tqs	Compensates for edge phase errors; may be temporarily lengthened during synchronization.
Phase_Seg2	2 ~ 8 Tqs	Compensates for edge phase errors; may be temporarily shortened during synchronization.
SJW	1 ~ 4 Tqs	Cannot be longer than either Phase Buffer Segment (Phase_Seg1/2).

Communication Baud Rate

The communication rate of an A2C node is the inverse of the total Tq count for a single bit. For example, if the clock source is 40MHz and the prescaler is 2, a single Tq time is 0.05us. Assuming a single bit occupies 20 Tqs, the baud rate is:

\[Baud\ Rate = \frac{core\_clk}{(BRP) \times (Total\ Tq)} = 1000000 baud/s\]

Synchronization Process

The previously defined segment division for each data bit did not involve phase details. According to the ISO 11898 standard, synchronization is divided into:

• Hard Synchronization: Only effective when a “Start of Frame (SOF)” signal exists.

• Resynchronization: Effective for subsequent signals after SOF.

Both use the Sync_Seg segment for detection. The goal is to align the node’s internal Sync_Seg to encompass the signal edge.

1. Hard Synchronization

   When Bus Idle ends, the first SOF signal arrives. If the receiving node detects the bus SOF edge outside its internal timing SS (Sync_Seg) range, it determines it is unsynchronized. The receiving node then forcibly resets its Bit Time counter, aligning its Sync_Seg to the falling edge of the SOF signal. Sampling can proceed correctly after synchronization.

   

   Hard Synchronization

   Using Figure Hard Synchronization as an example:

   1. Transmitting Node_A sends the SOF bit; the falling edge is in its SS segment.

   2. Receiving Node_B finds its current SS segment is not synchronized with Node_A’s SOF SS segment. (Node_B’s SS segment occurred 5 Tqs earlier).

   3. Node_B forcibly aligns its current SS segment to sync with the SOF SS segment.

2. Resynchronization

   During frame transmission (except for SOF), resynchronization occurs upon detecting a recessive-to-dominant (high-to-low) edge. Based on the relative position of the bus edge and Sync_Seg, resynchronization is divided into:

   1. Resynchronization for Phase Lead (as shown in Figure Resynchronization (Phase Lead)).

      1. Transmitting Node_A is slower than Receiving Node_B. Node_A’s SS segment occurs when Node_B’s SS segment for the current bit occurred 2 Tqs ago.

      2. Node_B extends PBS1 by 2 Tqs.

      3. Node_A’s sample point for the current bit now syncs with Node_B’s.

   2. Resynchronization for Phase Lag (as shown in Figure Resynchronization (Phase Lag)).

      1. Transmitting Node_A’s SS segment occurs 2 Tqs before Receiving Node_B’s.

      2. Node_B shortens its PBS2 segment.

      3. This allows Node_B’s next bit to start 2 Tqs earlier, syncing the next bit’s sample point with Node_A.

   

   Resynchronization (Phase Lead)

   

   Resynchronization (Phase Lag)

   The time duration by which Phase_Seg1 is increased or Phase_Seg2 is decreased during resynchronization is defined as SJW (Resynchronization Jump Width). A single synchronization cannot add or subtract more than the SJW duration. If needed, the controller adjusts via multiple small steps. A larger SJW allows the controller to absorb larger errors but may reduce communication speed/stability tolerance.

Error Detection and Management

When transmitting or receiving data on the bus, if a communication node detects an error, it actively initiates an Error Frame. As mentioned earlier, besides the 6-bit error flag, error flags may overlap by 0 to 6 bits. Before detailing Error Frames, one must understand Bit Stuffing, Error Types, and Error Handling mechanisms in ISO 11898.

Bit Stuffing

The ISO 11898 protocol relies on signal edge transitions for synchronization. If a data stream has a large number of consecutive identical logic levels (e.g., consecutive ‘1’s or ‘0’s), the signal will not toggle for a long time. The receiver will lose synchronization, causing sample point drift and communication errors. To solve this, bit stuffing rules are applied:

• Sender Logic: When sending Data or Remote Frames, if 5 consecutive bits of the same polarity are detected within the SOF ~ CRC fields, a stuffing bit of the opposite polarity is automatically inserted.

• Receiver Logic: When receiving Data or Remote Frames, if 5 consecutive bits of the same polarity are detected within the SOF ~ CRC fields during decoding, the subsequent bit (which must be of opposite polarity) is automatically removed (De-stuffed) to restore original data. If the 6th bit has the same level as the previous 5, it is treated as a Stuff Error.

The diagram below marks stuffing bits in orange:

Bit Stuffing Diagram

Error Types

Common error types are listed below:

Summary of Error Types and Error Frame Transmission Timing

Error Type	Description	Detection Frame (Field)	Error Frame Timing	Detector
Bit Error	Detected when the monitored bus value differs from the bit value sent (excluding stuffing bits).	Data Frame (SOF ~ CRC) Remote Frame (SOF ~ CRC) Error Frame Flag Overload Frame Flag	Next Bit (Immediately starts sending Error Flag after the bit where error was detected)	Sender
Stuff Error	Detected when 6 consecutive bits of the same level are observed in a field requiring bit stuffing.	Data Frame (SOF ~ CRC Sequence) Remote Frame (SOF ~ CRC Sequence)	Next Bit (Immediately starts sending Error Flag upon detecting the 6th consecutive identical bit)	Receiver
CRC Error	Detected when the calculated CRC result differs from the received CRC sequence.	Data Frame (CRC Sequence) Remote Frame (CRC Sequence)	After ACK Delimiter (Starts sending at the first bit of EOF, i.e., after ACK Delimiter)	Receiver
Form Error	Detected when a fixed-format bit field contains an illegal value.	Data/Remote Frame (CRC Delimiter, ACK Delimiter, EOF first 6 bits) Error Delimiter Overload Delimiter	Next Bit (Exception: Form Error in CRC Delimiter is treated as CRC Error, sent after ACK Delimiter)	Sender Receiver
ACK Error	Detected when the sender observes a recessive level in the ACK Slot (did not receive dominant ACK from receiver).	Data Frame (ACK Slot) Remote Frame (ACK Slot)	After ACK Delimiter (Starts sending at the first bit of EOF, i.e., after ACK Delimiter)	Sender

Error Frame Timing:

1. Immediate Transmission (Next Bit):

   Bit Error, Stuff Error, and Form Error (most cases) trigger an Error Frame immediately at the next bit. This ensures data consistency and prevents error propagation.

2. Delayed Transmission (After ACK Delimiter):

   CRC Error and ACK Error trigger Error Frames after the ACK Delimiter.

   • CRC Error: Although the receiver calculates the error during CRC, it does not report it immediately. It sends an ACK (if format is correct) or not, and waits until after the ACK Delimiter to pull the bus low at the EOF stage. This avoids corrupting the ACK process for other nodes that might have received data correctly.

   • ACK Error: If the sender sees no acknowledgment (Recessive ACK Slot), it sends an Error Frame after the ACK Delimiter.

Note

• Bit Errors do not occur during ID Arbitration, ACK Slot, or while sending a Passive Error Flag:

  • In Arbitration: Sending 1 but reading 0 is considered arbitration loss.

  • In ACK Slot: Sender sends Recessive 1 and reads 1 implies no ACK received (ACK Error).

  • Passive Error: Sending Passive Error Flag (6 recessive bits) but reading Dominant is not a Bit Error.

• A dominant bit in the last bit of EOF triggers an Overload Frame, not an Error Frame.

• Sender errors: Bit Error, Form Error, ACK Error.

• Receiver errors: Stuff Error, Form Error, CRC Error.

Error Handling Mechanism

When an A2C node detects an error, it transitions between three states based on its internal error counters (TEC and REC).

Error State Transition

Note

• TEC: Transmit Error Counter

• REC: Receive Error Counter

The table below summarizes entry conditions and behavior for each state.

A2C Bus Error States

Error State	Entry Condition (Threshold)	Error Flag Type	Communication & Behavior
Error Active	TEC ≤ 127 AND REC ≤ 127	Active Error Flag (6 consecutive Dominant bits)	Normal Communication: Node fully participates in transmission and reception. Strong Intervention: Upon detecting an error, immediately sends dominant levels to destroy bus data, notifying the entire network.
Error Passive	TEC > 127 OR REC > 127	Passive Error Flag (6 consecutive Recessive bits)	Weak Intervention: Sends recessive bits upon error. If the bus is dominant, this flag is overwritten (cannot destroy bus traffic) and does not affect other Error Active nodes. Transmission Delay: Must wait an extra 8 recessive bits (“Suspension Transmission”) between consecutive frames.
Bus Off	TEC > 255	None (Transmission Disabled)	Communication Disabled: Node is logically disconnected from the bus; physical driver is off. Recovery: Requires reset sequence or detecting 128 occurrences of 11 consecutive recessive bits to revert to Error Active.

Error counters are updated at the first bit of the error flag. A single transmission/reception may meet multiple conditions, potentially adjusting the counter multiple times.

Error Counter Update Rules

No.	Trigger Condition	TEC (Tx)	REC (Rx)
1	Receiver detects error (Exception: Bit Error during Error/Overload Flag does not change REC)	—	+1
2	Receiver detects dominant bit as first bit after sending Error Flag	—	+8
3	Sender detects error while outputting Error Flag	+8	—
4	Sender detects Bit Error while sending Active/Overload Flag	+8	—
5	Receiver detects Bit Error while sending Active/Overload Flag	—	+8
6	Any node detects 14 consecutive dominant bits (starting from Active/Overload Flag), and for every subsequent 8 dominant bits	+8	+8
7	Detecting 8 consecutive dominant bits after Passive Error Flag	+8	+8
8	Successful Transmission (ACK received, no error, EOF complete)	-1	—
9	Successful Reception (CRC correct, ACK sent successfully)	—	If REC > 127, set to 127; if REC = 0, keep 0; otherwise -1.
10	Bus Off Recovery (Detected 128 × 11 recessive bits)	Set to 0	Set to 0

Sending Error Frame

1. Non-overlapping Error Flags: Figure Non-overlapping Error Flags shows Node A detecting a “Bit Error” while transmitting, followed by Node B detecting a “Stuff Error” (due to 6 consecutive dominant levels). The error flags from Node A and Node B do not overlap.

Non-overlapping Error Flags

2. Overlapping Error Flags: Figure Overlapping Error Flags shows Node A generating a “Bit Error” and Node B detecting a Stuff Error (6 consecutive dominant levels). The active error flags overlap by 2 bits, with 4 bits remaining.

Overlapping Error Flags

Sending Overload Frame

The Overload Flag consists of 6 consecutive dominant bits (0). It destroys the transmission of other nodes on the bus, preventing them from sending messages normally, effectively delaying their transmission. An Overload Frame is transmitted in the following three cases:

• Receiver Internal Not Ready: Due to processing speed or buffer limitations, the receiving node is not ready for the next frame. It sends an Overload Frame at the first bit of Intermission to forcibly extend the idle time.

• Dominant Bit Detected at 1st or 2nd Bit of Intermission: A normal Intermission contains at least 3 consecutive recessive bits. Detecting a dominant bit in the first two implies a node transmitted early (timing error) or bus interference. The node sends an Overload Frame to handle this synchronization anomaly.

• Dominant Bit Detected at 8th Bit (Last Bit) of Error/Overload Delimiter: The delimiter format is 8 consecutive recessive bits. If the last bit is dominant, it is treated as the next frame starting too early (or previous frame not ending correctly). This specific Overload Frame does not increment the error counter.

• Dominant Bit Detected at Last Bit of EOF: Since the first 6 bits of EOF passed checks, the protocol deems current frame reception Valid, and handles this as an overload condition rather than a form error.

Note

• Error Counters: Sending an Overload Frame is “harmless”; it does not increment the node’s TEC or REC.

• Limit: To prevent permanent bus blocking, controllers typically limit the number of consecutive Overload Frames (usually max 2 frames delay).

A2C Configuration

Clock Source Configuration

A2C relies on XTAL (40MHz) as the clock source. Users can call A2C_CoreClockSet() to select XTAL.

Baud Rate and Bit Timing Configuration

As mentioned, an A2C bus bit consists of four time segments. To simplify configuration, the A2C controller combines Prop_Seg and Phase_Seg1 into TSEG1, and refers to Phase_Seg2 as TSEG2.

Note

TSEG1 setting is the sum of Propagation Segment (Prop_Seg) and Phase Buffer Segment 1 (Phase_Seg1).

Taking Clock Source 40MHz, 1Mbaud/s rate, Sample Point at 80% as an example, the parameters are calculated as follows:

1. Sample Point Formula

\[\text{Sample Point %} = \frac{\text{Sync_Seg} + \text{TSEG1}}{\text{Sync_Seg} + \text{TSEG1} + \text{TSEG2}} \times 100\%\]

Values satisfying the 80% ratio (4/5) include 8/10, 12/15, 16/20, 20/25.

The total Tq count for a single bit is:

\[Total\ Tq = \text{Sync_Seg} + \text{TSEG1} + \text{TSEG2}\]

Typically, Total Tq is between 8 ~ 25. We can choose 10 or 20 for convenience.

Selecting Total Tq = 10:

\[\text{Sync_Seg} + \text{TSEG1} = 8\]

\[\text{Sync_Seg} + \text{TSEG1} + \text{TSEG2} = 10\]

Thus, TSEG1 = 8 - 1 = 7 and TSEG2 = 10 - 7 - 1 = 2.

SJW is usually 1 ~ 4 Tqs and must not exceed the smaller of TSEG1 and TSEG2. In this example, setting it to 1 Tq is recommended.

2. Bit Timing Parameter Setting

Baud rate formula:

\[Baud\ Rate = \frac{core\_clk}{(BRP) \times (Total\ Tq)}\]

Given 1Mbps rate, 40MHz clock, and 10 Total Tqs, the prescaler (BRP) is 4.

Parameters can be configured as follows:

Bit Timing Parameter Settings

Parameter	Phy Value	Register	Note
Clock	40 MHz		XTAL as clock source
BRP	4	3	tq = 100ns
NBT	10 tq		Nominal Bit Time
TSEG1	7 tq	6	PropSeg + PhaseSeg1
TSEG2	2 tq	1	PhaseSeg2
SJW	1 tq	1
Result	80%		Sample Point (1+7)/10 = 80%

In practice, users can directly call A2C_CalcBitTiming() to calculate the required parameters for the target baud rate.

3-Point Sampling

When 3-Point Sampling is enabled, the A2C controller samples the input signal at three different points separated by Tq, as shown below. The final logic level is determined by the majority. This effectively filters glitches and improves robustness.

Note

Generally recommended for low baud rates (below 125Kbps), where each Tq is longer, making the system more susceptible to glitches causing level shifts.

Message Tx/Rx Settings

The A2C module manages message transmission and reception (including filtering) via Message Buffers (MB). A2C provides a set of registers as a common interface (referred to as RAM Interface) to manage message buffers.

Message Buffer Management

A2C features independent RAM space (352 × 32 bits), divided into 16 Message Buffers (MB0~MB15). By default, each buffer occupies 6 × 32 bits.

• Capacity Config: Each buffer stores one message; size is independently configurable.

• Address Allocation: Set the Base Address for each buffer. If MB0 Base Address is 0x0 and MB1 is 0x6, MB0 size is 6 × 32 bits.

• Boundary: The effective range of the entire RAM can be specified.

Message Transmission and Reception

1. Transmission Flow

   1. Select Buffer: Choose and enable a Message Buffer.

   2. Fill Data: Write data, ID, DLC, and frame attributes (IDE, RTR) to the RAM Interface.

   3. Configure Mode: Set to Transmit Mode.

   4. Write Buffer: Write settings and data into the Message Buffer.

   5. Status Update: Buffer status bits update automatically; interrupt triggers if enabled.

2. Reception Flow

   1. Select Buffer: Choose and enable a Message Buffer.

   2. Configure Filter: Set ID, Mask (MASK), IDE, and RTR bits in the RAM Interface to define expected message characteristics.

   3. Configure Mode: Set to Receive Mode.

   4. Write Buffer: Write settings into the Message Buffer.

   5. Receive & Store: Upon receiving a frame and passing CRC, the processor scans all RX buffers for a filter match. If matched and error-free, the message is stored.

   6. Status Update: Buffer status bits update automatically; interrupt triggers if enabled (user reads buffer in interrupt).

For A2C usage examples, refer to A2C example.

Buffer Priority

When multiple buffers meet Tx or Rx conditions simultaneously, hardware arbitrates based on buffer number (0-15):

• Tx Priority: Lower number has higher priority (e.g., MB0 > MB1).

• Rx Priority: Higher number has higher priority during matching (e.g., MB15 > MB0).

Message Filtering

ISO 11898 uses broadcast communication; there are no physical addresses. Nodes use Message Filtering to decide whether to accept data frames.

A2C allows configuring Receive Identifier (ID) and Acceptance Mask (MASK) for hardware-level filtering, reducing CPU load.

A2C Message Filter Settings

1. Receive All Messages

   Set only ARB register (Receive ID) without configuring MASK. This implies ignoring ID bits, receiving all messages.

2. Receive Partial Messages

   Set ARB and MASK registers. For example (Figure A2C Message Filter Settings), to filter standard frames: if ARB bits [28:18] are 0x1 and MASK bits [28:18] are 0x7FC, the lower 2 bits of the Standard ID are ignored. Base IDs 0x00, 0x01, 0x02, and 0x03 will be accepted.

3. Receive Specific Message

   Set ARB register and configure all MASK bits to 1. This strictly matches the Receive ID; only messages with the exact ID are accepted.

Tip

Users can also set attributes in MASK to further match frame types:

• RTR Attribute: Strictly match RTR setting in ARB (Data vs Remote Frame).

• IDE Attribute: Strictly match IDE setting in ARB (Standard vs Extended Frame).

FIFO Mode

A2C supports merging the top 4 buffers (MB12~MB15) into a First-In-First-Out (FIFO) queue to enhance continuous reception capabilities.

• Enable Mechanism: When FIFO is enabled, MB12~MB15 are reserved as FIFO storage space.

• Filter Rule: The FIFO uniformly uses MB12’s configuration (ID, IDE, RTR, and Mask) as the filtering standard.

• Highest Priority: The FIFO possesses the highest reception priority, strictly higher than normal reception buffers.

• Overflow Handling: When the FIFO is full (MB12~MB15 all contain data) and a new message is received, the FIFO executes a rolling overwrite policy. The oldest received data (originally in MB12) is lost, data from MB13 moves to MB12, and so on, with the new message being stored in MB15. This action simultaneously triggers the overflow status flag.

• Status Monitoring (A2C_FIFO_STS):

  • fifo_msg_empty: FIFO is empty.

  • fifo_msg_full: FIFO is full (contains 4 unread frames).

  • fifo_msg_overflow: Overflow (new frame received while full caused data loss).

  • fifo_msg_lvl: Current number of messages in the FIFO.

Note

FIFO mode is enabled by default; users can disable it if not needed.

Receiving via DMA

A2C supports data reception via General Direct Memory Access (GDMA), supporting two flow control modes: GDMA as flow controller or A2C as flow controller.

When DMA is enabled, data in the Message Buffer (including ARB, CS, DATA) is transferred sequentially via GDMA to the target memory.

Configuration Process:

1. A2C Side:

   1. In Rx DMA config register, set Rx DMA ownership and rxdma_src_msize (usually 1).

      1. rxdma_owner = 0: Ownership belongs to GDMA.

      2. rxdma_owner = 1: Ownership belongs to A2C.

   2. In the Message Buffer Control Register, enable DMA for that buffer.

   3. In A2C Global Control Register, enable Rx DMA.

2. GDMA Side:

   Configure source address, destination address, direction, block size, etc.

Note

• Rx DMA transfer targets one Message Buffer per operation.

• GDMA Source Burst Size must match rxdma_src_msize configured in A2C.

Automatic Retransmission

The ISO 11898-1 standard stipulates that if the controller fails to transmit a message successfully (i.e., no ACK received, error occurred, or arbitration lost), the controller can be configured to automatically retransmit the message. Once automatic retransmission is enabled, software only needs to write the transmission request once, and the hardware will automatically handle the subsequent retransmission logic. This process is typically transparent to the upper layer software (Application Layer).

Note

• Setting a specific number of retransmission attempts is not supported.

Enable Automatic Retransmission

In the A2C module, the A2C_AutoReTxEn control bit determines whether to follow the standard ISO automatic retransmission process:

• Enable (A2C_AutoReTxEn = 1): Standard Mode. When transmission fails (e.g., arbitration lost or transmission error occurred), the hardware automatically re-participates in bus contention and attempts to send the same frame again until it is successfully sent or the node enters the “Bus Off” state due to excessive errors.

• Disable (A2C_AutoReTxEn = 0): Single Shot Mode. The A2C controller attempts to send the message only once. Regardless of whether the transmission is successful (even if an error occurs or arbitration is lost), the hardware will not attempt to retransmit.

Scenarios Triggering Automatic Retransmission

When the automatic retransmission function is enabled, the following three scenarios will trigger a retransmission:

1. Arbitration Lost:

   During the ID transmission phase, if the current node detects that the bus level is inconsistent with the level it is transmitting (it transmits recessive 1, but the bus is dominant 0), it indicates that a higher priority node is transmitting. The current node immediately stops transmitting and switches to the receiving state. Once the bus becomes idle, the hardware immediately attempts to transmit the message again.

2. Transmission Error:

   If a Bit Error, Stuff Error, Form Error, or CRC Error is detected during transmission, the transmitting node sends an Error Frame to destroy the current transmission and retransmits the message when the bus becomes idle.

3. ACK Error:

   The transmitting node sends a recessive level (1) in the ACK Slot, but does not detect a dominant level (0) on the bus. This means that no node on the bus has correctly responded to the message (i.e., replied with an ACK). The transmitting node determines this as an ACK Error, subsequently sends an Error Frame, and retransmits the message when the bus becomes idle.

Low Power Wake-up

The A2C module supports low-power sleep modes, with the sleep type only supporting CG (Clock Gating) mode. In this mode, the module’s main clock is stopped, but the internally integrated wake-up detection circuit remains active.

A2C uses a low-frequency clock (OSC4M) to drive the wake-up circuit. When the CPU and A2C module enter sleep mode, the system must keep OSC4M enabled to support the monitoring function. For sleep mode configuration, please refer to Power Saving Configuration .

Wake-up Diagram

The workflow of the wake-up circuit is as follows:

1. Enable Conditions:

   Wake-up detection is valid only when the A2C enters sleep mode (a2c_sleep_en is set) and the wake-up filter function is enabled (a2c_wakepin_flt_en is set).

2. Detection Principle:

   The circuit continuously monitors the duration of the dominant level on the Rx pin and compares it with the preset threshold a2c_wakepin_flt_length to determine if it is a valid wake-up signal. As shown in Wake-up Diagram, if the duration t of the dominant level (i.e., logic level 0 on the Rx pin) is greater than the set threshold (a2c_wakepin_flt_length/OSC4M), it wakes up the A2C module and the entire system.

3. Trigger Action:

   • Wake-up: If the detected dominant level duration exceeds the preset threshold, the wake-up circuit generates a wake-up signal to reactivate the A2C module and the entire system.

   • Hold: If the dominant level duration does not reach the threshold, the module and system remain in sleep mode.

Note

• Protocol frame content is irrelevant for wake-up: The dominant level that wakes up the A2C module comes from a valid protocol frame, but this frame cannot be received.

• Transceiver must work normally during wake-up: Some transceivers may have standby/sleep modes. Ensure the transceiver is operating normally before attempting to wake up the A2C module.

• Wake-up & Frame Loss:

  Since it takes time for the system to recover from sleep and for the main clock to stabilize, the A2C module will inevitably miss the frame that triggered the wake-up. Whether subsequent data can be received depends on the sender’s retransmission mechanism:

  • If no other node on the bus sends an ACK:

    The sending node determines transmission failure due to missing ACK. If its automatic retransmission mechanism is enabled, it will immediately retransmit the frame. By this time, the A2C module has completed wake-up initialization and can correctly receive this retransmitted message.

  • If other nodes on the bus send an ACK:

    The sending node receives an ACK and considers the message sent successfully, so it will not retransmit. In this case, although the current node (A2C) is successfully woken up, it cannot receive the data of that frame (resulting in single frame loss).

Test Modes

Two test modes are available:

• Silence Mode: Bus Monitoring Mode in ISO 11898-1. Used to analyze traffic without interfering. It receives all frames but sends nothing (no frames, no ACK).

• Loopback Mode: Verifies A2C controller functionality.

  • External Loopback: Data frames are sent to the TX pin; protocol frames can be captured by an external analyzer.

  • Internal Loopback: Data frames transfer entirely within the A2C controller; nothing is sent externally.

Silence Mode

External Loopback Mode

Internal Loopback Mode