LCD Controller (LCDC)

Supported ICs[ RTL8721F ]

Introduction

The Liquid Crystal Display Controller (LCDC) is used to fetch display data from main memory and output with MIPI-DSI interface. MIPI-DSI supports several formats, or packet sequences. The following figure illustrates the video mode data transmission.

DSI packets

Normally, RGB pixel data is sent with one full scanline of pixels in a single packet. And during the BLLP the DSI Link transmit one or more null packets from the host processor to the peripheral using HS Mode.

When the display function is prepared to be turned on, in order to avoid underflow, the MIPI-DSI must be initialized after the LCDC is ready, so that the LCDC will have enough time to prepare the pixel data of the first line. In contrast, to safely close the display function, stop the MIPI-DSI first and then stop the LCDC.

MIPI-DSI Interface

Display Module Reset Pin

The display module reset pin is _PA_4. The function Pinmux_Swdoff() needs to be called firstly because _PA_4 is used for SWD by default. Triggering this pin low enables DSI-CLK+/- lanes and DSI-Dn+/- Data lanes to be driven into Low Power Mode. Be sure to perform this operation after supplying power if the TFT panels need to be reset.

Command Mode Power Modes

DSI-CLK+/- Lanes

DSI-CLK+/- lanes can be driven into three different power modes:

• Low Power Mode (LPM LP-11)

• Ultra-Low Power Mode (ULPM)

• High Speed Clock Mode (HSCM)

1. DSI-CLK+/- lanes can be driven to Low Power Mode, when DSI-CLK lanes are entering LP-11 State Code, in three different ways:

   1. After SW Reset, HW Reset or Power On Sequence => LP-11

   2. After DSI-CLK+/- lanes are leaving Ultra-Low Power Mode (ULPM, LP-00 State Code) => LP10 => LP-11 (LPM).

   3. After DSI-CLK+/- lanes are leaving High Speed Clock Mode (HSCM, HS-0 or HS-1 State Code) => HS-0 => LP-11 (LPM).

2. DSI-CLK+/- lanes can be driven to Ultra-Low Power Mode (ULPM), when DSI-CLK lanes are entering LP-00 State Code. The only entering possibility is from the Low Power Mode (LPM, LP-11 State Code) => LP-10 => LP-00 (ULPM).

3. DSI-CLK+/- lanes can be driven to High Speed Clock Mode (HSCM), when DSI-CLK lanes are starting to work between HS-0 and HS-1 State Codes. The only entering possibility is from the Low Power Mode (LPM, LP-11 State Code) => LP-01 => LP-00 => HS-0 => HS-0/1 (HSCM).

DSI-Dn+/- Data Lanes

DSI-Dn+/- Data lanes can be driven in different modes which are:

• Escape Mode (Only DSI-D0+/- data lanes are used)

• High-Speed Data Transmission (DSI-D1+/- and DSI-D0+/- data lanes are used)

• Bus Turnaround Request (Only DSI-D0+/- data lanes are used)

These modes and their entering codes are defined in the following table:

Mode	Entering mode sequence	Leaving mode sequence
Escape Mode	LP-11 => LP-10 => LP-00 => LP-01 => LP-00	LP-00 => LP-10 => LP11
High-Speed Data Transmission	LP-11 => LP-01 => LP-00 => HS-0	(HS-0 or HS-1) => LP-11
Bus Turnaround Request	LP-11 => LP-10 => LP-00 => LP-10 => LP-00	High-Z

Escape commands are illustrated below:

Escape command	Command type (Mode/Trigger)	Entry command pattern (First-bit/Last-bit transmitted)	D1	D0
Low-Power Data Transmission	Mode	1110 0001 bin	–	Supported
Ultra-Low Power Mode	Mode	0001 1110 bin	Supported	Supported
Underfined-1	Mode	1001 1111 bin	–	–
Underfined-2	Mode	1101 1110 bin	–	–
Remote Application Reset	Trigger	0110 0010 bin	–	Supported
Tearing Effect	Trigger	0101 1101 bin	–	–
Acknowledge	Trigger	0010 0001 bin	–	Supported
Unknow-5	Trigger	1010 0000 bin	–	–

Video Mode Bandwidth Requirements

Depending on the resolution of the display panel and on the refresh rate, the D-PHY required bandwidth can be calculated below:

BRbps = (VACT+VSA+VBP+VFP) x (HACT+HSA+HBP+HFP) x Pixel Format x Frame Rate/Lanenum

Here, Pixel Format is decided by the packet selected to transmit image data in the MIPI-DSI protocol. The LSBs are typically dropped once Pixel Format is less than 24bit.

For example:

• Frame rate=60Hz

• VACT=800Line

• VSA=5Line

• VBP=20Line

• VSA=5Line

• VFP=15Line

• HACT=480Pixel

• HAS=4Pixel

• HBP=30Pixel

• HFP=30Pixel

• Lanenum=2(lane)

• Pixel Format=24(bit)

So, BRbps=330Mbps/lane

When image data is transferred to a video mode display module, the MIPI-DSI requests the pixel data from the VO interface. The pixel data is fixed with RGB888 format, so the result of the frequency of the VO interface multiply by 24-bit shall be great than BRbps x Lanenum to avoid any display problems. The frequency of the VO interface can be modified to meet the bandwidth requirements of the MIPI-DSI by the CKD_MIPI field of the LSYS_CKD_GRP0 register.

The LCDC required bandwidth depends mainly on three factors:

• The number of used LCDC layers

• The LCDC layer color depth

• The VO Interface clock (depends on the resolution of the display panel and on the refresh rate)

The VO returns 1 pixel data for each VO clock cycle, so the maximum required bandwidth can be calculated as VO_CLK x 3 if three LCDC layers are used and the image layer data format is ARGB8888.

Modifying the CKD_HPERI field of the LSYS_CKD_GRP0 register can change the frequency of LCDC if the bandwidth of LCDC does not meet the requirements of VO Interface. Users should check if the memory bandwidth can sustain the hardware configuration because the master’s concurrent access on the same external memory leads to more latency and impacts its throughput. Setting the LCDC request to HPR can reduce the latency if masters concurrent access DDR Once that the framebuffer location is in the DDR.

How to Use LCDC

To build and run LCDC demo in SDK, follow these steps:

1. Enable LCDC demo: KM4 make menuconfig > MENUCONFIG FOR CHIP CONFIG > CONFIG FUNCTION TEST > Enable Peripheral Test, and select LCDC_Verify_Mode.

2. Open the LCDCMIPI clock which is used by VO interface and the HPERI clock used by LCDC.

   /*
   
   * @brif   RCC Configuration.
   *  by Users.
   
   */
   BOOT_RAM_DATA_SECTION
   RCC_ConfDef RCC_Config[] = {
      /*Function,          Clock,                        State*/
      /* AON */
      {APBPeriph_SDM32K,   APBPeriph_SDM32K_CLOCK,       ENABLE},
      {APBPeriph_RTC,      APBPeriph_RTC_CLOCK,          DISABLE},
      {APBPeriph_ATIM,     APBPeriph_ATIM_CLOCK,         DISABLE},
      {APBPeriph_BOR,      APBPeriph_CLOCK_NULL,         DISABLE},
   
      {APBPeriph_PSRAM,    APBPeriph_PSRAM_CLOCK,        DISABLE},
      {APBPeriph_AUDIO,    APBPeriph_CLOCK_NULL,         DISABLE},
      {APBPeriph_AC,       APBPeriph_AC_CLOCK,           DISABLE},
      {APBPeriph_DDRP,     APBPeriph_DDRP_CLOCK,         ENABLE},
      {APBPeriph_DDRC,     APBPeriph_DDRC_CLOCK,         ENABLE},
      {APBPeriph_IRDA,     APBPeriph_IRDA_CLOCK,         DISABLE},
      {APBPeriph_ECDSA,    APBPeriph_ECDSA_CLOCK,        DISABLE},
      {APBPeriph_ED25519,  APBPeriph_ED25519_CLOCK,      DISABLE},
      {APBPeriph_RSA,      APBPeriph_CLOCK_NULL,         DISABLE},
      {APBPeriph_IPC_HP,   APBPeriph_IPC_HP_CLOCK,       ENABLE},
      {APBPeriph_LEDC,     APBPeriph_LEDC_CLOCK,         DISABLE},
      {APBPeriph_TRNG,     APBPeriph_TRNG_CLOCK,         DISABLE},
      {APBPeriph_USB,      APBPeriph_USB_CLOCK,          DISABLE},
      {APBPeriph_SDH,      APBPeriph_SDH_CLOCK,          DISABLE},
      {APBPeriph_SPI1,     APBPeriph_SPI1_CLOCK,         DISABLE},
      {APBPeriph_SPI0,     APBPeriph_SPI0_CLOCK,         DISABLE},
      {APBPeriph_GDMA,     APBPeriph_GDMA_CLOCK,         ENABLE},
      {APBPeriph_LCDC,     APBPeriph_LCDCMIPI_CLOCK,     ENABLE},
      {APBPeriph_IPSEC,    APBPeriph_IPSEC_CLOCK,        ENABLE},
      {APBPeriph_LX1,      APBPeriph_LX1_CLOCK,          ENABLE},
      {APBPeriph_NULL,     APBPeriph_HPERI_CLOCK,        ENABLE},
   

3. Modify MipiDsi_ST7701S() by your LCM parameter, and in this function LCM is initialized by the following steps:

   1. Call MIPI_StructInit() to define the configuration parameters of MIPI-DSI.

   2. Set configuration parameters according to your requirements.

   3. Trigger the display module reset pin low.

   4. Call MIPI_DPHY_init() to configure the D-PHY.

   5. Call MIPI_DSI_init() to configure the MIPI-DSI.

   6. Send init CMD to LCM according to the ST7701S_init_cmd_g[] in command mode.

4. Call LcdcRgbDisplayTest() to switch to video mode to start display.

   1. Call LCDC_StructInit() to define the configuration parameters of LCDC.

   2. Set configuration parameters according to your requirements.

   3. Call LCDC_Init() to configure the LCDC.

   4. Call LCDC_CheckLCDCReady() to wait LCDC is ready.

   5. Call MIPI_DSI_Mode_Switch() to switch to video mode for image display.

Raw API

LCDC Exported Types

RTL8730ERTL8721F

RTL8730E:

struct LCDC_InitTypeDef

LCDC Init Structure Definition.

Public Members

u16 LCDC_ImageWidth

Specifies the width of the display image in pixels.

u16 LCDC_ImageHeight

Specifies the height of the display image in pixels.

u8 LCDC_BgColorRed

Specifies the red component of the background color. Value range: 0x00 to 0xFF.

u8 LCDC_BgColorGreen

Specifies the green component of the background color. Value range: 0x00 to 0xFF.

u8 LCDC_BgColorBlue

Specifies the blue component of the background color. Value range: 0x00 to 0xFF.

LCDC_LayerConfigTypeDef layerx[LCDC_LAYER_MAX_NUM]

Specifies the configuration for each display layer.

struct LCDC_LayerConfigTypeDef

LCDC Layer Init Structure Definition.

Public Members

u8 LCDC_LayerEn

Specifies layer enable or not. This parameter can be a value of ENABLE or DISABLE

u8 LCDC_LayerImgFormat

Specifies the layer image data format. This parameter can be a value of LCDC Layer IMG Format

u8 LCDC_LayerColorKeyingEn

Specifies the layer’s color keying enable or not. This parameter can be a value of ENABLE or DISABLE

u32 LCDC_LayerImgBaseAddr

Specifies the image base address. This parameter can be a number between 0x0 and 0xffffffff.

u16 LCDC_LayerHorizontalStart

Specifies the first pixel of a line of the layer window. This parameter can be a number between 0x0 and 0xfff.

u16 LCDC_LayerHorizontalStop

Specifies the last pixel of a line of the layer window. This parameter can be a number between 0x0 and 0xfff.

u16 LCDC_LayerVerticalStart

Specifies the first line of the layer window. This parameter can be a number between 0x0 and 0xfff.

u16 LCDC_LayerVerticalStop

Specifies the last line of the layer window. This parameter can be a number between 0x0 and 0xfff.

u32 LCDC_LayerColorKeyingVal

Specifies the color key value (RGB), which is used by the Color Keying. This parameter can be a number between 0x0 and 0xffffff.

u8 LCDC_LayerBlendConfig

Specifies the blending factor. This parameter can be a value of 0 (const alpha) or 1 (pixel alpha x constant alpha)

u8 LCDC_LayerConstAlpha

Specifies the Constant Alpha used for blending. This parameter can be a number between 0x00 and 0xff. Hardware divides the Constant Alpha value by 256. When Constant Alpha is 0xFF, it is identified as 1.

LCDC Exported Constants

LCDC IT Clear

RTL8730ERTL8721F

RTL8730E:

/* Validates that IT is a legal LCDC interrupt clear bitmask. */
#define IS_LCDC_CLEAR_IT ((((IT) & (u32)0xFFFFFFD2) == 0x00) && ((IT) != 0x00))

LCDC DMA Underflow Mode

RTL8730ERTL8721F

RTL8730E:

/* DMA underflow outputs last valid data. */
#define LCDC_DMAUNFW_OUTPUT_LASTDATA (0)

/* DMA underflow outputs configured error data. */
#define LCDC_DMAUNFW_OUTPUT_ERRORDATA (LCDC_BIT_DMA_UN_MODE)

/* Validates that MODE is a legal DMA underflow output mode. */
#define IS_LCDC_DMA_DMA_UNDERFLOW_MODE (((MODE) == LCDC_DMAUNFW_OUTPUT_LASTDATA) || ((MODE) == LCDC_DMAUNFW_OUTPUT_ERRORDATA))

LCDC DMA Debug Out

RTL8730ERTL8721F

RTL8730E:

/* Enable secondary DMA write-back debug output. */
#define LCDC_DMA_OUT_ENABLE LCDC_BIT_LCD_DMA_OUT

/* Disable secondary DMA write-back debug output. */
#define LCDC_DMA_OUT_DISABLE (0)

/* Validates that MODE is a legal DMA debug output mode. */
#define IS_LCDC_DMA_DEBUG_OUT_MODE (((MODE) == LCDC_DMA_OUT_ENABLE) || ((MODE) == LCDC_DMA_OUT_DISABLE))

LCDC Layer Burst Size

RTL8730ERTL8721F

RTL8730E:

/* DMA burst size: 1 x 64 bytes per burst. */
#define LCDC_LAYER_BURSTSIZE_1X64BYTES (0x1)

/* DMA burst size: 2 x 64 bytes per burst. */
#define LCDC_LAYER_BURSTSIZE_2X64BYTES (0x2)

/* DMA burst size: 3 x 64 bytes per burst. */
#define LCDC_LAYER_BURSTSIZE_3X64BYTES (0x3)

/* DMA burst size: 4 x 64 bytes per burst. */
#define LCDC_LAYER_BURSTSIZE_4X64BYTES (0x4)

/* Validates that x is a legal layer DMA burst size. */
#define IS_LCDC_LAYER_BURSTSIZE (((u32)(x) - 1) < LCDC_LAYER_BURSTSIZE_4X64BYTES)

LCDC Layer IMG Format

RTL8730ERTL8721F

RTL8730E:

/* Layer image format: ARGB8888 (32-bit). */
#define LCDC_LAYER_IMG_FORMAT_ARGB8888 (0x0)

/* Layer image format: RGB888 (24-bit). */
#define LCDC_LAYER_IMG_FORMAT_RGB888 (0x1)

/* Layer image format: RGB565 (16-bit). */
#define LCDC_LAYER_IMG_FORMAT_RGB565 (0x2)

/* Layer image format: ARGB1555 (16-bit with 1-bit alpha). */
#define LCDC_LAYER_IMG_FORMAT_ARGB1555 (0x3)

/* Layer image format: ARGB4444 (16-bit with 4-bit alpha). */
#define LCDC_LAYER_IMG_FORMAT_ARGB4444 (0x4)

/* Layer image format: RGB666 (18-bit). */
#define LCDC_LAYER_IMG_FORMAT_RGB666 (0x5)

/* Layer image format: ARGB8666 (32-bit with 8-bit alpha). */
#define LCDC_LAYER_IMG_FORMAT_ARGB8666 (0x6)

/* Validates that MODE is a legal layer image format. */
#define IS_LCDC_LAYER_IMG_FORMAT ((u32)(MODE) <= LCDC_LAYER_IMG_FORMAT_ARGB8666)

LCDC Layer ID

RTL8730ERTL8721F

RTL8730E:

/* LCDC layer index: layer 1 (first layer). */
#define LCDC_LAYER_LAYER1 (0x0)

/* LCDC layer index: layer 2 (second layer). */
#define LCDC_LAYER_LAYER2 (0x1)

/* LCDC layer index: layer 3 (third layer). */
#define LCDC_LAYER_LAYER3 (0x2)

/* Total number of available LCDC layers. */
#define LCDC_LAYER_MAX_NUM (0x3)

/* Validates that LayerID is a legal LCDC layer index. */
#define IS_LCDC_A_VALID_LAYER ((u32)(LayerID) <= LCDC_LAYER_LAYER3)

LCDC MCU IF Width Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC RGB IF Width Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC DMA Underflow Mode Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC DMA Underflow Option Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC DMA Mode Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC DMA Burst Size

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC INTR Type Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC INTR Status Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC RGB Sync Mode Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC RGB DMA Mode Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC RGB Data Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC RGB Enable Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC RGB HSYNC Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC RGB VSYNC Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC RGB DCLK Active Edge Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC RGB TE Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC MCU Swap Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC MCU Mode Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC MCU Sync Mode Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC MCU VSYNC Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC MCU TE Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC MCU Data Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC MCU Read Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC MCU Write Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC MCU RS Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC MCU CS Pulse Polarity Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC Input Format Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC Output Format Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC Pre-Command Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC Shift Offset Define

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC RW Parameter

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC Peripheral Definitions

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC Exported Functions

LCDC Interrupt Functions

void LCDC_ClearAllINT(LCDC_TypeDef *LCDCx)

Clear all of the LCDC interrupt pending bits.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

void LCDC_LineINTPosConfig(LCDC_TypeDef *LCDCx, u32 LineNum)

Configure line interrupt position.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• LineNum – The specific line number at which the line interrupt is triggered.

RTL8730ERTL8721F

RTL8730E:

void LCDC_ClearINT(LCDC_TypeDef *LCDCx, u32 LCDC_IT)

Clear the LCDC’s interrupt pending bits.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• LCDC_IT –

  Specifies the interrupt to be cleared. This parameter can be any combination of the following values:

  • LCDC_BIT_FRM_START_INTS: DMA frame start interrupt

  • LCDC_BIT_LCD_LIN_INTS: Line interrupt

  • LCDC_BIT_LCD_FRD_INTS: LCD refresh frame done interrupt

  • LCDC_BIT_DMA_UN_INTS: DMA FIFO underflow interrupt

u32 LCDC_GetINTStatus(LCDC_TypeDef *LCDCx)

Get LCDC interrupt status.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

Returns:

The interrupt status register value. Each bit indicates an interrupt source:

• LCDC_BIT_FRM_START_INTS: DMA frame start interrupt status

• LCDC_BIT_LCD_LIN_INTS: Line interrupt status

• LCDC_BIT_LCD_FRD_INTS: LCD refresh frame done interrupt status

• LCDC_BIT_DMA_UN_INTS: DMA FIFO underflow interrupt status

u32 LCDC_GetRawINTStatus(LCDC_TypeDef *LCDCx)

Get LCDC Raw Interrupt Status.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

Returns:

The raw interrupt status register value. Each bit indicates an interrupt source:

• LCDC_BIT_FRM_START_INTRS: DMA frame start raw interrupt status

• LCDC_BIT_LCD_LIN_INTRS: Line raw interrupt status

• LCDC_BIT_LCD_FRD_INTRS: LCD refresh frame done raw interrupt status

• LCDC_BIT_DMA_UN_INTRS: DMA FIFO underflow raw interrupt status

void LCDC_INTConfig(LCDC_TypeDef *LCDCx, u32 LCDC_IT, u32 NewState)

Enable or disable the specified LCDC interrupts.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• LCDC_IT –

  Specifies the LCDC interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • LCDC_BIT_FRM_START_INTEN: DMA frame start interrupt

  • LCDC_BIT_LCD_LIN_INTEN: Line interrupt

  • LCDC_BIT_LCD_FRD_INTEN: LCD refresh frame done interrupt

  • LCDC_BIT_DMA_UN_INTEN: DMA FIFO underflow interrupt

• NewState – New state of the specified LCDC interrupts. This parameter can be: ENABLE or DISABLE.

void LCDC_GetDmaUnINTCnt(LCDC_TypeDef *LCDCx, u32 *DmaUnIntCnt)

Get the DMA FIFO underflow interrupt count.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• DmaUnIntCnt – The DMA underflow interrupt count pointer.

LCDC Global Functions

void LCDC_Cmd(LCDC_TypeDef *LCDCx, u32 NewState)

Enable or disable the LCDC.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• NewState – New state of the LCDC. This parameter can be: ENABLE or DISABLE.

Note

• When NewState is DISABLE, the disable action will be performed instantly.

• HW will reset LCDC internal states and disable LCDC, then clear both the disable bit and the enable bit (LCDCEN).

void LCDC_DeInit(LCDC_TypeDef *LCDCx)

Deinitialize the LCDC.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

Note

Disable LCDC instantly, clear and disable all interrupts.

void LCDC_GetCurPosStatus(LCDC_TypeDef *LCDCx, u32 *pCurPosX, u32 *pCurPosY)

Get the current position.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• pCurPosX – The current X position pointer.

• pCurPosY – The current Y position pointer.

RTL8730ERTL8721F

RTL8730E:

u8 LCDC_CheckLCDCReady(LCDC_TypeDef *LCDCx)

Check LCDC is ready to work with VO interface after LCDC is enabled.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

Returns:

Status:

• TRUE: Ready

• FALSE: Not ready

void LCDC_Init(LCDC_TypeDef *LCDCx, LCDC_InitTypeDef *LCDC_InitStruct)

Initialize the LCDC according to the specified parameters in the LCDC_InitStruct.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• LCDC_InitStruct – Pointer to a LCDC_InitTypeDef structure that contains the configuration information for all LCDC layers.

void LCDC_LayerConfig(LCDC_TypeDef *LCDCx, u8 LayerId, LCDC_LayerConfigTypeDef *EachLayer)

Initialize the LCDC Layer according to the specified parameters in the EachLayer.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• LayerId – Specifies the LCDC layer to configure.

• EachLayer – Pointer to a LCDC_LayerConfigTypeDef structure that contains the configuration information for the specified LCDC layer.

void LCDC_SetBkgColor(LCDC_TypeDef *LCDCx, u8 red_color, u8 green_color, u8 blue_color)

Set the LCDC background color.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• red_color – Red component of background color.

• green_color – Green component of background color.

• blue_color – Blue component of background color.

void LCDC_SetPlaneSize(LCDC_TypeDef *LCDCx, u32 ImageWidth, u32 ImageHeight)

Set the LCDC Plane Size.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• ImageWidth – The width of image (X-channel based), which means pixel number per line.

• ImageHeight – The height of image (Y-channel based)

void LCDC_StructInit(LCDC_InitTypeDef *LCDC_InitStruct)

Fill each LCDC_InitTypeDef member with its default value.

Parameters:

• LCDC_InitStruct – Pointer to an LCDC_InitTypeDef structure which will be initialized.

void LCDC_TrigerSHWReload(LCDC_TypeDef *LCDCx)

Trigger Layer’s shadow register reload to apply new configuration.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

Note

The shadow registers read back the active values. Until the reload has been done, the ‘old’ value is read.

LCDC DMA Configure Functions

RTL8730ERTL8721F

RTL8730E:

void LCDC_DMADebugConfig(LCDC_TypeDef *LCDCx, u32 DmaWriteBack, u32 ImgDestAddr)

Configure LCDC DMA debug write back function.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• DmaWriteBack –

  Secondary RGB output port enabled, the blended data of entire image will be written back to memory. this parameter can be one of the following values:

  • LCDC_DMA_OUT_ENABLE: Enable the debug function

  • LCDC_DMA_OUT_DISABLE: Disable the debug function

• ImgDestAddr – Image DMA destination address. (for debug)

void LCDC_DMAModeConfig(LCDC_TypeDef *LCDCx, u32 BurstSize)

Configure LCDC DMA burst size.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• BurstSize –

  DMA burst size; Unit 64 Bytes.

  • LCDC_LAYER_BURSTSIZE_1X64BYTES: Burst Transactions = 1;

  • LCDC_LAYER_BURSTSIZE_2X64BYTES: Burst Transactions = 2;

  • LCDC_LAYER_BURSTSIZE_3X64BYTES: Burst Transactions = 3;

  • LCDC_LAYER_BURSTSIZE_4X64BYTES: Burst Transactions = 4;

Note

• If the BurstSize=1, the actual burstsize = 1x64 Bytes; If the BurstSize=2, the actual burstsize = 2x64 = 128 Bytes; etc.

• The parameter “BurstSize” value range: 1 to 4.

void LCDC_DMAUnderFlowConfig(LCDC_TypeDef *LCDCx, u32 DmaUnFlwMode, u32 ErrorData)

Configure LCDC DMA underflow mode and underflow error data.

Parameters:

• LCDCx – Where LCDCx can be LCDC.

• DmaUnFlwMode –

  DMA underflow mode, this parameter can be one of the following values:

  • LCDC_DMAUNFW_OUTPUT_LASTDATA: output last data

  • LCDC_DMAUNFW_OUTPUT_ERRORDATA: output error data

• ErrorData – The output data when DMA FIFO underflow occurred. When underflow mode is configured as LCDC_DMAUNFW_OUTPUT_ERRORDATA, this parameter is needed, and otherwise it can be ignored.

LCDC MCU Interface Functions

RTL8730ERTL8721F

RTL8730E:

Not supported.

LCDC RGB Interface Functions

RTL8730ERTL8721F

RTL8730E:

Not supported.