DMAC Configuration

The general DMA configuration process is as follows:

1. Initialize clock: Enable DMA controller (DMAC) clock

2. Configure relevant DMA channel

   1. Allocate a free DMA channel

   2. Set channel control parameters according to application requirements

      1. Transfer direction and flow control: such as memory-to-peripheral, peripheral-to-memory, and whether the source or destination peripheral or DMAC controls transfer requests and pace

      2. Source port and destination port addresses

      3. Transfer width (1/2/4 Bytes)

      4. Burst length msize (1/4/8/16)

      5. Transfer block size (Block Size)

      6. Priority setting

3. Enable channel interrupt (for transfer complete/error notification, if needed)

4. Start data transfer: Set channel enable bit, start DMA channel, peripheral/DMAC initiates DMA request, and begin data transfer

5. Completion and post-processing

   1. DMA transfer generates an interrupt after completion

   2. Handle completion signal and release resources in the interrupt service routine

DMA parameter illustration:

Channel Allocation and Release

DMA implements channel allocation and release through the following two APIs:

• GDMA_ChnlAlloc(): Allocates channels sequentially, starting from channel 0.

• GDMA_ChnlFree(): Releases a channel according to the specified channel number.

During the channel allocation process, it is possible that two CPUs may request the same channel simultaneously, which can cause the program to run abnormally. To solve this issue, a hardware semaphore is used for protection during the channel allocation process.

Transfer Direction and Flow Controller

There are currently four transfer directions and two flow controller settings, resulting in eight available configurations.

• When the peripheral is set as the flow controller, the DMA transfers data based on the single/burst requests from the peripheral.

• When the DMAC is set as the flow controller, all requests from the peripheral will be processed according to the configured request type.

CTLx.TT_FC[2:0] (x is channel)	Direction	Flow Controller
000	Memory to Memory	DMAC
001	Memory to Peripheral	DMAC
010	Peripheral to Memory	DMAC
011	Peripheral to Peripheral	DMAC
100	Peripheral to Memory	Peripheral
101	Peripheral to Peripheral	Source Peripheral
110	Memory to Peripheral	Peripheral
111	Peripheral to Peripheral	Destination Peripheral

Principles of Flow Controller Configuration:

• If the block_ts is known, use DMAC as the flow controller. For example: music playback, image display, and memory copy operations.

• If the block_ts is unknown, use the peripheral as the flow controller. For example: when UART receives variable-length data, UART can be set as the flow controller so that a transfer is requested each time data arrives.

Warning

• The block_ts parameter can only be set when DMAC is used as the flow controller.

• When using a peripheral as the flow controller, make sure that the IP supports triggering DMA requests in the hardware design. For more details, please refer to the Handshake section.

Data Block Size

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The above diagram illustrates the configuration of the DMAC transfer data size. block_ts specifies the amount of data to be transferred in a single data block and should be set to total data size/SRC_TR_WIDTH, with a maximum value of {{IC_PARAM_GDMA_BLOCK_SIZE}}.

Transaction Mode and Width

The transaction size for each DMAC transfer can be configured:

• msize > 1: Burst transfer

• msize = 1: Single transfer

CTLx.SRC_MSIZE[2:0]/DEST_MSIZE[2:0]	Transfer msize
000	1
001	4
010	8
011	16
100 and above	Not supported

DMAC supports the following transfer widths:

CTLx.SRC_TR_WIDTH[2:0]/DST_TR_WIDTH[2:0]	Transfer Width/Bytes
000	1
001	2
010	4
011 and above	Not supported

• When DMAC acts as the flow controller, if the remaining data in a block is not enough for a Msize * Width transfer but is sufficient for a 1 * Width transfer, DMAC will initiate a single transfer request to complete the transfer.

• When the peripheral is the flow controller, the peripheral decides whether to issue a single transfer or burst transfer request.

Note

• When accessing peripheral: SRC_TR_WIDTH/DST_TR_WIDTH should be set according to the data width of the peripheral.

• When accessing memory:

  • If cache is disabled, the memory address does not need to be aligned, but the total data must be divisible by SRC_TR_WIDTH to ensure block_ts remains an integer.

  • If cache is enabled, the memory address must meet the buffer boundary alignment and align to the cache line.

• When the source or destination is memory (e.g., P2M, M2M modes): the hardware will force the memory side transfer width to 4 Bytes, and the configured DST_TR_WIDTH or SRC_TR_WIDTH parameter for memory will be ignored.

• To prevent FIFO underflow or overflow, SRC_MSIZE * SRC_TR_WIDTH and DST_MSIZE * DST_TR_WIDTH must remain equal.

Transfer Types

DMAC supports the following transfer types:

• Single Block: Contains only one data block

• Multi-Block: Contains multiple data blocks

  • Auto-reloading mode

  • Link List mode

  • Continuous mode

The usage scenarios and features of each mode are as follows:

DMAC Modes Features

Mode	Sub-mode	Application Scenario	Features
Single Block		Continuous address space, single transfer	DMA stops immediately after the transfer is complete
Multi-Block	auto-reload	Continuous address space where the source or destination needs to repeatedly reload a particular data block	If block interrupt is enabled, DMA pauses after each block transfer until the interrupt is processed
	Link List	Non-contiguous address space	If block interrupt is enabled, an interrupt is triggered after each block transfer, but the next block transfer starts immediately In this mode, DMA data transfer is not blocked even during interrupts
	continuous	Continuous data block in a single address space	Always uses address increment mode; if both source and destination are in continuous mode, the transfer is the same as single block mode. Typically used when only one side is continuous and the other side uses auto-reload or Link List mode

Auto-reloading Mode

In auto-reloading mode, the source and destination can independently select which method to use.

Auto-reloading transfer types	Setting	Introduction
Src auto reload	PGDMA_InitTypeDef->GDMA_ReloadSrc = 1 PGDMA_InitTypeDef->GDMA_ReloadDst = 0	For multi-block transfers, the SAR register can be auto-reloaded from the initial value at the end of each block, and DST address is contiguous, as shown in Multi-block DMA transfer with source address auto-reloaded and contiguous destination address..
Dst auto reload	PGDMA_InitTypeDef->GDMA_ReloadSrc = 0 PGDMA_InitTypeDef->GDMA_ReloadDst = 1	For multi-block transfers, the DAR register can be auto-reloaded from its initial value at the end of each block, and the SRC address is contiguous.
Src & Dst auto reload	PGDMA_InitTypeDef->GDMA_ReloadSrc = 1 PGDMA_InitTypeDef->GDMA_ReloadDst = 1	For multi-block transfers, the SAR and DAR register can be auto-reloaded from its initial value at the end of each block, as shown in Multi-block DMA transfer with source and destination address auto-reloaded..

Multi-block DMA transfer with source address auto-reloaded and contiguous destination address.

Multi-block DMA transfer with source and destination address auto-reloaded.

Link List Mode

In Link List mode, the addresses between data blocks do not have to be consecutive.

Link List transfer types	Setting	Introduction
Src: Contiguous address Dst: Link List	PGDMA_InitTypeDef->GDMA_SrcAddr = pSrc PGDMA_InitTypeDef->GDMA_LlpDstEn = 1	Source memory is a continuous data block, while destination data blocks are organized in Link List.
Src: Auto-reloading Dst: Link List	PGDMA_InitTypeDef->GDMA_ReloadSrc = 1 PGDMA_InitTypeDef->GDMA_SrcAddr = pSrc PGDMA_InitTypeDef->GDMA_LlpDstEn = 1	In source, SAR register can be auto-reloaded from the initial value at the end of each block, as shown in Multi-block DMA transfer with source address auto-reloaded and Link List destination address.
Src: Link List Dst: Contiguous address	PGDMA_InitTypeDef->GDMA_LlpSrcEn = 1 PGDMA_InitTypeDef->GDMA_DstAddr = pDst	Source memory is organized in the form of a Link List, and destination memory is a continuous data block, as shown in Multi-block DMA transfer with Link List source address and contiguous destination address.
Src: Link List Dst: Auto-reloading	PGDMA_InitTypeDef->GDMA_LlpSrcEn = 1 PGDMA_InitTypeDef->GDMA_DstAddr = pDst PGDMA_InitTypeDef->GDMA_ReloadDst = 1	The source data blocks are organized in a Link List, and the destination data blocks are auto-reloading.
Src: Link List Dst: Link List	PGDMA_InitTypeDef->GDMA_LlpSrcEn = 1 PGDMA_InitTypeDef->GDMA_LlpDstEn = 1	Both source and destination data blocks are organized in Link Lists, as shown in Multi-block DMA transfer with linked address for source and destination.

If both the destination and the source are continuous data blocks, multi-block transfer should not be used, and single-block transfer is more appropriate.

Multi-block DMA transfer with source address auto-reloaded and Link List destination address

Multi-block DMA transfer with Link List source address and contiguous destination address

Multi-block DMA transfer with linked address for source and destination

Address Increment Type

Source Address Increment

There are two modes:

• Increment: Indicates whether to increment the source address on every source transfer. Incrementing is done for alignment to the next CTLx.SRC_TR_WIDTH boundary.

• No change: If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change.

Destination Address Increment

There are two modes:

• Increment: indicates whether to increment destination address on every destination transfer. Incrementing is done for alignment to the next CTLx.DST_TR_WIDTH boundary.

• No change: If the device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No change.

Configuration Principles:

• If the source or destination is Memory, the address mode is generally set to Increment.

• If the source or destination is a Peripheral, the address mode is generally set to No Change.

FIFO

Each DMAC channel has its own independent FIFO, and the FIFO sizes of different channels are not the same.

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FIFO Size

Channel Number	CH0	CH1	CH2~CH7
FIFO size/Bytes	128	128	32

Interrupt Type

There are several supported interrupt types, which can be used independently or in combination.

Interrupt type	Introduction
block interrupt	Triggered by the completion of a data block transfer
transfer interrupt	Occurs when all data blocks have been transferred
error interrupt	There was a transfer error

Note

• In multi-block auto-reload mode, a block interrupt pauses the transfer after each block until the interrupt handler completes.

• In Link List mode, the transfer-complete condition is that the last data block’s next-block pointer is null.

• In Link List mode, a block interrupt does not pause the transfer; the next block transfer starts immediately.

Suspend and Abort

DMAC supports channel suspend resume and termination.

• To suspend a channel, just configure CFGx.CH_SUSP, but there is no guarantee that the current data transaction is completed. Combined with CFGx.INACTIVE, the channel can be safely paused without losing data.

• To resume data transmission after suspension, clear CFGx.CH_SUSP.

• To terminate data transfer, CFGx.INACTIVE must be continuously polled until this bit is set to 1, then the data transfer can be aborted.

Note

CFGx.INACTIVE indicates whether the channel is idle on the AXI bus (1 = inactive, 0 = active). It can be used together with CFGx.CH_SUSP to cleanly disable a channel when the destination is a peripheral. The channel becomes inactive in the following situations:

• After the DMAC has finished writing all pending data to memory, CFGx.INACTIVE is set to 1 automatically.

• If the peripheral data width (e.g. 4 bytes) exceeds the remaining DMAC FIFO space (e.g. 2 bytes), no write can be initiated and CFGx.INACTIVE is set to 1 immediately.

Gather and Scatter

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Not supported.

Priority

DMAC supports two kinds of channel priority:

• Software: the priority of each channel can be configured in the CFGx.CH_PRIOR. The valid value is 0 ~ (DMAC_NUM_CHANNELS-1), where 0 is the highest priority value and (DMAC_NUM_CHANNELS-1) is the lowest priority value.

• Hardware: if two channel requests have the same software priority level, or if no software priority is configured, the channel with the lower number takes priority over the channel with the higher number. For example, channel 2 takes priority over channel 4.

Handshake

DMAC supports only hardware handshake and does not support software handshake. The handshake interface needs to be configured only when transferring data between DMAC and peripherals. All hardware handshake interfaces are fixed during IC design and cannot be modified by users. The hardware handshake interfaces supported by the current IC and their corresponding IPs are listed in the following table:

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DMAC Handshake Interface

Function	Handshake No.	Description
UART0 TX	0
UART0 RX	1
UART1 TX	2
UART1 RX	3
UART2 TX	4
UART2 RX	5
SPI0 TX	6
SPI0 RX	7
SPI1 TX	8
SPI1 RX	9
SPIC TX	10
SPIC RX	11
SPORT0 TX	12	Two FIFOs, occupies 12 & 13
SPORT0 RX	14	Two FIFOs, occupies 14 & 15
SPORT1 TX	16	Two FIFOs, occupies 16 & 17
SPORT1 RX	18	Two FIFOs, occupies 18 & 19
LEDC_TX	20
I2C0 TX	21
I2C0 RX	22
I2C1 TX	23
I2C1 RX	24

Real-time Status Acquisition

DMAC supports real-time acquisition of the current transmission source address, destination address and the data size that has been transmitted. Call the corresponding APIs to read.

Note

To get the amount of data that has been transferred, the block_ts must be greater than 768, and cannot be read in an interrupt function; otherwise, the value obtained is always 0.

Security Mechanism

By default, the secure transfer feature of DMAC is disabled. When users need to use this feature, they must first enable the Trustzone feature .

DMAC supports independent configuration of the secure transfer feature for each channel. Once this feature is enabled, the DMAC will initiate secure access requests through the AXI master interface. At this point, DMAC can transfer data between secure and non-secure peripherals (or memory).

• Secure channels can only be configured within the secure world, and secure channels can access both secure peripherals (memory) and non-secure peripherals (memory).

• Non-secure channels can only access non-secure peripherals (memory).

To enable the secure transfer feature for a specific channel, set the following structure member when configuring DMAC parameters in Secure code:

PGDMA_InitTypeDef->SecureTransfer = 1;