Overview
General Direct Memory Access (GDMA) Controller, also known as DMAC, is used to transfer data between memory and peripherals. The data transfer process does not require CPU intervention, thereby reducing the CPU workload. The architecture diagram of DMAC is shown below:
Features
DMAC supports the following features:
Supports up to 8 independent channels. The source and destination ports of each channel can be freely assigned to Memory or peripherals with DMAC capability.
Supports channel priority configuration.
Supports multiple transfer directions:
Peripheral to Memory
Peripheral to Peripheral
Memory to Peripheral
Memory to Memory
Each channel is equipped with an independent FIFO. The FIFO size varies across channels to suit different application scenarios.
Flexible flow control options: users can configure the transfer request and pacing to be controlled by the source peripheral, destination peripheral, or the DMAC itself.
Supports both single and burst transfer modes.
Supports single block and multiple block data transfers.
Supports secure transfer mode.
Supports low power consumption operation.
Supports pause, resume, and disable of channels during data transfers without data loss.
Supports up to 8 independent channels. The source and destination ports of each channel can be freely assigned to Memory or peripherals with DMAC capability.
Supports channel priority configuration.
Supports multiple transfer directions:
Peripheral to Memory
Peripheral to Peripheral
Memory to Peripheral
Memory to Memory
Each channel is equipped with an independent FIFO. The FIFO size varies across channels to suit different application scenarios.
Flexible flow control options: users can configure the transfer request and pacing to be controlled by the source peripheral, destination peripheral, or the DMAC itself.
Supports both single and burst transfer modes.
Supports single block and multiple block data transfers.
Supports secure transfer mode.
Supports low power consumption operation.
Supports pause, resume, and disable of channels during data transfers without data loss.
Supports up to 8 independent channels. The source and destination ports of each channel can be freely assigned to Memory or peripherals with DMAC capability.
Supports channel priority configuration.
Supports multiple transfer directions:
Peripheral to Memory
Peripheral to Peripheral
Memory to Peripheral
Memory to Memory
Each channel is equipped with an independent FIFO. The FIFO size varies across channels to suit different application scenarios.
Flexible flow control options: users can configure the transfer request and pacing to be controlled by the source peripheral, destination peripheral, or the DMAC itself.
Supports both single and burst transfer modes.
Supports single block and multiple block data transfers.
Supports secure transfer mode.
Supports low power consumption operation.
Supports pause, resume, and disable of channels during data transfers without data loss.
Supports up to 8 independent channels. The source and destination ports of each channel can be freely assigned to Memory or peripherals with DMAC capability.
Supports channel priority configuration.
Supports multiple transfer directions:
Peripheral to Memory
Peripheral to Peripheral
Memory to Peripheral
Memory to Memory
Each channel is equipped with an independent FIFO. The FIFO size varies across channels to suit different application scenarios.
Flexible flow control options: users can configure the transfer request and pacing to be controlled by the source peripheral, destination peripheral, or the DMAC itself.
Supports both single and burst transfer modes.
Supports single block and multiple block data transfers.
Supports secure transfer mode.
Supports low power consumption operation.
Supports pause, resume, and disable of channels during data transfers without data loss.
Supports up to 8 independent channels. The source and destination ports of each channel can be freely assigned to Memory or peripherals with DMAC capability.
Supports channel priority configuration.
Supports multiple transfer directions:
Peripheral to Memory
Peripheral to Peripheral
Memory to Peripheral
Memory to Memory
Each channel is equipped with an independent FIFO. The FIFO size varies across channels to suit different application scenarios.
Flexible flow control options: users can configure the transfer request and pacing to be controlled by the source peripheral, destination peripheral, or the DMAC itself.
Supports both single and burst transfer modes.
Supports single block and multiple block data transfers.
Supports secure transfer mode.
Supports low power consumption operation.
Supports pause, resume, and disable of channels during data transfers without data loss.
Supports up to 8 independent channels. The source and destination ports of each channel can be freely assigned to Memory or peripherals with DMAC capability.
Supports channel priority configuration.
Supports multiple transfer directions:
Peripheral to Memory
Peripheral to Peripheral
Memory to Peripheral
Memory to Memory
Each channel is equipped with an independent FIFO. The FIFO size varies across channels to suit different application scenarios.
Flexible flow control options: users can configure the transfer request and pacing to be controlled by the source peripheral, destination peripheral, or the DMAC itself.
Supports both single and burst transfer modes.
Supports single block and multiple block data transfers.
Supports secure transfer mode.
Supports low power consumption operation.
Supports pause, resume, and disable of channels during data transfers without data loss.
Supports up to 8 independent channels. The source and destination ports of each channel can be freely assigned to Memory or peripherals with DMAC capability.
Supports channel priority configuration.
Supports multiple transfer directions:
Peripheral to Memory
Peripheral to Peripheral
Memory to Peripheral
Memory to Memory
Each channel is equipped with an independent FIFO. The FIFO size varies across channels to suit different application scenarios.
Flexible flow control options: users can configure the transfer request and pacing to be controlled by the source peripheral, destination peripheral, or the DMAC itself.
Supports both single and burst transfer modes.
Supports single block and multiple block data transfers.
Supports secure transfer mode.
Supports low power consumption operation.
Supports pause, resume, and disable of channels during data transfers without data loss.
Supports gather transfer for non-contiguous memory (Channel 0 ~ Channel 3).
Supports scatter transfer for contiguous memory (Channel 0 ~ Channel 3).
Supports up to 8 independent channels. The source and destination ports of each channel can be freely assigned to Memory or peripherals with DMAC capability.
Supports channel priority configuration.
Supports multiple transfer directions:
Peripheral to Memory
Peripheral to Peripheral
Memory to Peripheral
Memory to Memory
Each channel is equipped with an independent FIFO. The FIFO size varies across channels to suit different application scenarios.
Flexible flow control options: users can configure the transfer request and pacing to be controlled by the source peripheral, destination peripheral, or the DMAC itself.
Supports both single and burst transfer modes.
Supports single block and multiple block data transfers.
Supports secure transfer mode.
Supports low power consumption operation.
Supports pause, resume, and disable of channels during data transfers without data loss.
Supports gather transfer for non-contiguous memory (Channel 0 ~ Channel 3).
Supports scatter transfer for contiguous memory (Channel 0 ~ Channel 3).
Supports up to 8 independent channels (Channel 0-7). The source and destination ports of each channel can be freely assigned to Memory or peripherals with GDMA capability.
Supports channel priority configuration (0 is highest priority).
Different FIFO sizes per channel:
Channel 0-1: 128-byte FIFO
Channel 2-7: 64-byte FIFO
Supports multiple transfer directions:
Memory to Memory
Memory to Peripheral
Peripheral to Memory
Peripheral to Peripheral
Extended transfer types with flow control:
Peripheral to Memory (Peripheral controlled)
Peripheral to Peripheral (Source controlled)
Memory to Peripheral (Peripheral controlled)
Peripheral to Peripheral (Destination controlled)
Register to Memory
Flexible flow control options: users can configure the transfer request and pacing to be controlled by the source peripheral, destination peripheral, or the DMAC itself.
Supports multiple data widths: 1 byte, 2 bytes, 4 bytes.
Supports multiple burst transaction lengths (Msize): 1, 4, 8, 16.
Supports single block and multiple block data transfers (block size: 1-65535).
Supports secure transfer mode.
Supports pause, resume, and disable of channels during data transfers without data loss.
Supports gather transfer for non-contiguous memory (all channels).
Supports scatter transfer for contiguous memory (all channels).
