Reset
Overview
Reset is used to restore the system to an initial state, which can be utilized for error recovery, system software reboot, and other functionalities.
Reset Types
The chip supports multiple reset types.
Reset Type |
Description |
Usage Method |
|---|---|---|
CHIP_EN |
Reset generated by chip enable |
Refer to Chip Enable |
POR |
Reset generated at power-on |
|
BOR |
Reset generated by undervoltage |
Refer to BOD |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to Watchdog |
WDG reset |
Reset generated by system watchdog timeout |
Refer to Watchdog |
Reset Type |
Description |
Usage Method |
|---|---|---|
CHIP_EN |
Reset generated by chip enable |
Refer to Chip Enable |
POR |
Reset generated at power-on |
- |
BOR |
Reset generated by undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to Watchdog |
WDG reset |
Reset generated by system watchdog timeout |
Refer to Watchdog |
Reset Type |
Description |
Usage Method |
|---|---|---|
CHIP_EN |
Reset generated by chip enable |
Refer to Chip Enable |
POR |
Reset generated at power-on |
- |
BOR |
Reset generated by undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to Watchdog |
WDG reset |
Reset generated by system watchdog timeout |
Refer to Watchdog |
Reset Type |
Description |
Usage Method |
|---|---|---|
CHIP_EN |
Reset generated by chip enable |
Refer to Chip Enable |
POR |
Reset generated at power-on |
- |
BOR |
Reset generated by undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to Watchdog |
WDG reset |
Reset generated by system watchdog timeout |
Refer to Watchdog |
Reset Type |
Description |
Usage Method |
|---|---|---|
CHIP_EN |
Reset generated by chip enable |
Refer to Chip Enable |
POR |
Reset generated at power-on |
- |
BOR |
Reset generated by undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to Watchdog |
WDG reset |
Reset generated by system watchdog timeout |
Refer to Watchdog |
Reset Type |
Description |
Usage Method |
|---|---|---|
CHIP_EN |
Reset generated by chip enable |
Refer to Chip Enable |
POR |
Reset generated at power-on |
- |
BOR |
Reset generated by undervoltage |
Refer to BOD |
BOR ACC |
Reset generated by ACC undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
WDG/IWDG reset |
Reset generated by system watchdog timeout |
Refer to Watchdog |
Reset Type |
Description |
Usage Method |
|---|---|---|
CHIP_EN |
Reset generated by chip enable |
Refer to Chip Enable |
POR |
Reset generated at power-on |
- |
RTC POR |
Reset generated at power-on in RTC reset domain |
- |
BOR |
Reset generated by undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to Watchdog |
WDG reset |
Reset generated by system watchdog timeout |
Refer to Watchdog |
Reset Type |
Description |
Usage Method |
|---|---|---|
CHIP_EN |
Reset generated by the external CHIP_EN pin |
Refer to Chip Enable |
POR |
Reset generated at power-on |
- |
BOR |
Reset generated by undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to Watchdog |
AP WDG reset |
Reset generated by AP core (KM4TZ) watchdog timeout |
Refer to Watchdog |
NP WDG reset |
Reset generated by NP core (KM4NS) watchdog timeout |
Refer to Watchdog |
Plfm1 reset |
Platform 1 system reset |
- |
Note
Plfm1 reset is only valid in dual-chip mode.
In dual-chip mode, the function of NP WDG reset becomes the same as Plfm1 reset.
Reset Domains
Scope |
RTC |
Backup registers, Retention RAM, Wake pin, Trap pin |
Other peripherals |
|---|---|---|---|
CHIP_EN |
Y |
Y |
Y |
POR |
Y |
Y |
Y |
BOR |
N |
N |
Y |
DSLP |
N |
N |
Y |
System reset |
N |
N |
Y |
IWDG reset |
N |
N |
Y |
WDG reset |
N |
N |
Y |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Note
Warm reset is configured at system startup to reset all CPUs instead of only the local CPU. Refer to the
Peripheral_Reset()function in the Bootloader for the peripherals that are reset by warm reset.
Scope |
RTC |
Wake pin, Trap pin, Backup registers, Retention RAM |
Other peripherals |
|---|---|---|---|
CHIP_EN |
Y |
Y |
Y |
POR |
Y |
Y |
Y |
BOR |
N |
N |
Y |
Thermal reset |
N |
N |
Y |
DSLP |
N |
N |
Y |
System reset |
Y |
N |
Y |
IWDG reset |
N |
N |
Y |
WDG reset |
N |
N |
Y |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Note
Warm reset is configured at system startup to reset all CPUs instead of only the local CPU. Refer to the
Peripheral_Reset()function in the Bootloader for the peripherals that are reset by warm reset.
Scope |
RTC |
Wake pin, Trap pin, Backup registers, Retention RAM |
Other peripherals |
|---|---|---|---|
CHIP_EN |
Y |
Y |
Y |
POR |
Y |
Y |
Y |
BOR |
N |
N |
Y |
Thermal reset |
N |
N |
Y |
DSLP |
N |
N |
Y |
System reset |
Y |
N |
Y |
IWDG reset |
N |
N |
Y |
WDG reset |
N |
N |
Y |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Note
Warm reset is configured at system startup to reset all CPUs instead of only the local CPU. Refer to the
Peripheral_Reset()function in the Bootloader for the peripherals that are reset by warm reset.
Scope |
RTC |
Wake pin, Trap pin, Backup registers, Retention RAM |
Other peripherals |
|---|---|---|---|
CHIP_EN |
Y |
Y |
Y |
POR |
Y |
Y |
Y |
BOR |
N |
N |
Y |
Thermal reset |
N |
N |
Y |
DSLP |
N |
N |
Y |
System reset |
Y |
N |
Y |
IWDG reset |
N |
N |
Y |
WDG reset |
N |
N |
Y |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Note
Warm reset is configured at system startup to reset all CPUs instead of only the local CPU. Refer to the
Peripheral_Reset()function in the Bootloader for the peripherals that are reset by warm reset.
Scope |
RTC |
Wake pin, Trap pin, Backup registers, Retention RAM |
Other peripherals |
|---|---|---|---|
CHIP_EN |
Y |
Y |
Y |
POR |
Y |
Y |
Y |
BOR |
N |
N |
Y |
Thermal reset |
N |
N |
Y |
DSLP |
N |
N |
Y |
System reset |
Y |
N |
Y |
IWDG reset |
N |
N |
Y |
WDG reset |
N |
N |
Y |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Note
Warm reset is configured at system startup to reset all CPUs instead of only the local CPU. Refer to the
Peripheral_Reset()function in the Bootloader for the peripherals that are reset by warm reset.
Scope |
Wake pin, Trap pin, Backup registers |
Retention RAM |
RTC |
OTPC |
Other peripherals |
|---|---|---|---|---|---|
CHIP_EN |
Y |
Y |
Y |
Y |
Y |
POR |
Y |
Y |
Y |
Y |
Y |
BOR |
N |
N |
N |
Y |
Y |
BOR ACC |
N |
N |
N |
Y |
Y |
Thermal reset |
N |
N |
N |
Y |
Y |
DSLP |
N |
Y |
N |
N |
Y |
System reset |
N |
N |
Y |
Y |
Y |
WDG/IWDG reset |
N |
N |
N |
Y |
Y |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Note
Warm reset is configured at system startup to reset all CPUs instead of only the local CPU. Refer to the
Peripheral_Reset()function in the Bootloader for the peripherals that are reset by warm reset.
Scope |
RTC |
Wake pin, Trap pin, Backup registers, Retention RAM, AON PAD, OTP |
I2C like, Pinmux |
Other peripherals |
|---|---|---|---|---|
CHIP_EN |
N |
Y |
Y |
Y |
POR |
N |
Y |
Y |
Y |
BOR |
N |
N |
Y |
Y |
Thermal reset |
N |
N |
Y |
Y |
DSLP |
N |
N |
Y |
Y |
System reset |
N |
N |
N* |
Y |
IWDG reset |
N |
N |
N* |
Y |
WDG reset |
N |
N |
N* |
Y |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
N*: Indicates that the corresponding module will not be reset by default when the reset event occurs, but can be configured to reset.
Note
The register
REG_AON_SYSRST_MSKcan be used to control whether I2C like and Pinmux are reset under System reset, IWDG reset, and WDG reset. The register definition is located insysreg_aon.h.Warm reset is configured at system startup to reset all CPUs instead of only the local CPU. Refer to the
Peripheral_Reset()function in the Bootloader for the peripherals that are reset by warm reset.PD_RTC is only reset when a POR occurs within the PD_RTC power domain itself.
Scope |
Trap pin, backup registers |
Wake pin, OTP |
GPIO, PWM, Pinmux |
KM4NS, SDN, WIFI, AES |
Other peripherals |
|---|---|---|---|---|---|
CHIP_EN |
Y |
Y |
Y |
Y |
Y |
POR |
Y |
Y |
Y |
Y |
Y |
BOR |
N |
N |
Y |
Y |
Y |
Thermal reset |
N |
N |
Y |
Y |
Y |
DSLP |
N |
N |
Y |
Y |
Y |
System reset |
N |
N |
N* |
Y |
Y |
IWDG reset |
N |
Y |
Y |
Y |
Y |
WDG reset |
N |
N |
N* |
Y |
Y |
Plfm1 reset |
N |
N |
N |
Y |
N |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
N*: Indicates that the corresponding module will not be reset by default when the reset event occurs, but can be configured to reset.
Note
Register
REG_AON_SYSRST_MSKcan be used to control whether Pinmux is reset under System reset and WDG reset. The register definition is located insysreg_aon.h.Register
REG_LSYS_SW_RST_CTRLcan be used to control whether GPIO and PWM are reset under System reset and WDG reset. The register definition is located insysreg_lsys.h.Warm reset is configured at system startup to reset all CPUs instead of only the local CPU. Refer to the
Peripheral_Reset()function in the Bootloader for the peripherals that are reset by warm reset.Plfm1 reset is only valid in 2in1 mode. In 2in1 mode, the WDG reset domain of KM4NS changes to match that of Plfm1 reset.
Obtaining Boot Reason
User can obtain the boot reason using the BOOT_Reason() function. Refer to
Boot Reason
.
Preserving Pre-reset Information
User can store critical data in backup registers or Retention RAM located in the AON region to prevent data loss due to reset.
Note
The following reset types will still cause data loss in backup registers or Retention RAM:
CHIP_EN
POR
Backup Registers
Realtek provides 4 32-bit backup registers: BKUP_REG0(), BKUP_REG1(), BKUP_REG2(), and BKUP_REG3() for use. User can manipulate these registers using the provided APIs.
Note
The system may use certain bits in the backup registers. User should search the SDK to confirm if a specific bit is already in use before using it.
API
BKUP_Write
Item |
Description |
|---|---|
Function |
Write a value to the corresponding backup register |
Params |
|
Return |
None |
BKUP_Read
Item |
Description |
|---|---|
Function |
Read the value from the corresponding backup register |
Params |
|
Return |
The value of the corresponding backup register |
BKUP_Set
Item |
Description |
|---|---|
Function |
Set specific bits in the corresponding backup register |
Params |
|
Return |
None |
BKUP_Clear
Item |
Description |
|---|---|
Function |
Clear specific bits in the corresponding backup register |
Params |
|
Return |
None |
Retention RAM
User can use the RRAM_DEV variable to store data in Retention RAM. The structure definition of this variable is RRAM_TypeDef, located in sysreg_lsys.h. Its structure member RRAM_USER_RSVD can be freely used by users.
Note
It is recommended that users prioritize using backup registers and only use Retention RAM when dealing with larger data volumes.
User can use the RRAM_DEV variable to store data in Retention RAM. The structure definition of this variable is RRAM_TypeDef, located in sysreg_lsys.h. Its structure member RRAM_USER_RSVD can be freely used by users.
Note
It is recommended that users prioritize using backup registers and only use Retention RAM when dealing with larger data volumes.
User can use the RRAM_DEV variable to store data in Retention RAM. The structure definition of this variable is RRAM_TypeDef, located in sysreg_lsys.h. Its structure member RRAM_USER_RSVD can be freely used by users.
Note
It is recommended that users prioritize using backup registers and only use Retention RAM when dealing with larger data volumes.
User can use the RRAM_DEV variable to store data in Retention RAM. The structure definition of this variable is RRAM_TypeDef, located in sysreg_lsys.h. Its structure member RRAM_USER_RSVD can be freely used by users.
Note
It is recommended that users prioritize using backup registers and only use Retention RAM when dealing with larger data volumes.
User can use the RRAM_DEV variable to store data in Retention RAM. The structure definition of this variable is RRAM_TypeDef, located in sysreg_lsys.h. Its structure member RRAM_USER_RSVD can be freely used by users.
Note
It is recommended that users prioritize using backup registers and only use Retention RAM when dealing with larger data volumes.
User can use the RRAM_DEV variable to store data in Retention RAM. The structure definition of this variable is RRAM_TypeDef, located in sysreg_lsys.h. Its structure member RRAM_USER_RSVD can be freely used by users.
Note
It is recommended that users prioritize using backup registers and only use Retention RAM when dealing with larger data volumes.
User can use the RRAM_DEV variable to store data in Retention RAM. The structure definition of this variable is RRAM_TypeDef, located in sysreg_lsys.h. Its structure member RRAM_USER_RSVD can be freely used by users.
Note
It is recommended that users prioritize using backup registers and only use Retention RAM when dealing with larger data volumes.
Not supported.
Software Reset Trigger Methods
User can execute a system reset by calling the System_Reset() function or by issuing a command. The definition of the System_Reset() function is as follows:
Item |
Description |
|---|---|
Function |
Trigger a system software reset |
Params |
None |
Return |
None |
Alternatively, the following command can be issued to any CPU to trigger a system software reset:
AT+RST