Real-Time Clock (RTC)

Overview

The Real-Time Clock (RTC) is an independent BCD-format timer/counter. As a core low-power timing peripheral of the chip, it provides continuous timekeeping, precise timing, and security protection capabilities. It can maintain uninterrupted operation across all chip operating states, meeting the needs of embedded devices for time management, low-power wakeup, and timed triggering.

The RTC of the Ameba series SOC implements only time and date counting; calendar and year management are handled by software. It supports a digital calibration feature for time correction, is equipped with backup registers that retain data even in deep sleep mode, and supports daylight saving time compensation, scheduled wakeup, and periodic wakeup functions.

Features

• Hardware counting of seconds, minutes, hours (12- or 24-hour format), and days; year and calendar logic implemented by software

• Daylight saving compensation programmable by software

• One programmable alarm, triggerable by any combination of time fields

• Maskable interrupt/event:

  • Alarm

  • Day threshold

  • Periodic wakeup timer

• Supports scheduled wakeup and periodic auto-wakeup

• Built-in digital calibration circuit

• Register write protection mechanism to prevent erroneous write accesses

• Backup registers with data retention in deep sleep mode

Block Diagram

The RTC module uses SDM32K as the clock source, generates a time base through two-stage frequency division and calibration, and provides time counting, alarm, and multiple clock output functions.

1. Clock Chain

   • The input clock RTCCLK (32.768 kHz) first passes through an asynchronous prescaler (division factor 128), outputting a 256 Hz clk_apre signal.

   • clk_apre then enters a synchronous prescaler with calibration capability (division factor 256), ultimately generating a 1 Hz clk_spre signal as the reference clock for the time counter.

   • The synchronous prescaler supports frequency calibration, fine-tuning the output frequency through the formula (-1)^DCS * DC / ((PREDIV_S+1) * (CALP+1) * 60) to compensate for crystal oscillator errors.

2. Time Counting and Alarm

   • The time counter uses clk_spre (1 Hz) as the clock, incrementing in day:hh:mm:ss format to maintain system time.

   • The alarm module supports configuring alarm time in day:hh:mm:ss format. When the time counter matches the alarm register value, an alarm_out signal is output, which can be used to trigger an interrupt or wakeup event.

3. Output Selection

   • The final output RTC_OUT of the RTC module is configured by OSEL[1:0], which can output clk_spre (1 Hz), clk_apre (256 Hz), or alarm_out signal to meet clock or event output requirements in different application scenarios.

The RTC system block diagram is shown below.

RTC Clock Select Diagram

The RTC clock select diagram is shown below. When the system boots, the default RTC clock source (RTCCLK) is from SDM32K.

Power Supply

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730ERTL8721F

RTL8721Dx:

VDH_RTC is the independent power supply pin for the RTC_IO module, available only in certain packages. Users can design a separate power supply circuit for this pin. When the main chip power is on, the RTC will periodically and automatically back up to RTC_IO. When the main chip power is off, RTC_IO will continue counting using the OSC131K clock domain. After the main system power is restored, SW processing time is required to recover and maintain system time continuity. During the power-off operation of the main system, the RTC timing accuracy is limited by the inherent accuracy of the OSC131K clock; this oscillator is calibrated once by software during power-on, but due to its process characteristics, the actual timing error during power-off operation may be higher than the nominal value at the time of calibration.

RTC_IO

Overview

VDH_RTC can independently power the OSC131K and RTC_IO circuits to continue timekeeping when the system main power is off. RTC_IO has an internal memory to store time data obtained from the RTC, as well as a counter. RTC_IO periodically reads RTC time data and saves it to the RTC_IO module’s memory, while also resetting the counter. When RTC_IO detects a main power loss, it stops reading RTC time and continues timekeeping using the internal counter. When the system powers on again, SW needs to read back the RTC time before power-off and the counter value to restore the system RTC time.

The RTC domain diagram is shown in the following figure.

Features

• rtc_sio transmits RTC time data to the RTC_IO module in the RTC module at an interval of 1/256s.

• The RTC_IO module retains RTC time data and count during power-off.

• The OSC32K calibration value LDO_RCAL can be retained in the RTC_IO domain to maintain the OSC32K calibration function during power-off.

Operation Flow

To shift LDO_RCAL into RTC_IO and shift out time data from RTC_IO, perform the configuration steps illustrated in the following table.

Step	What to do	How to do
1	Manually put RTC_IO into rtc_mode (optional)	Write 2’d2 to register rtc_io_ctrl[1:0]
2	Acquire LDO_RCAL[5:0] value	Read register LDO_BASE-> LDO_32K_OSC_CTRL[5:0]
3	Prepare data into the register that will be shifted into RTC_IO	Write step 2’s value to register rtc_io_test_din[63:58]
4	Enter MODE_SHIFT_ENABLE mode to start shift operation	Write 2’d1 to register rtc_io_ctrl[1:0]
5	Wait some time for rtc_sio to send command to RTC_IO	Wait 15ms
6	Read the stored time data and counter for further processing	Read registers rtc_io_test_dout[127:0]
7	Enter MODE_SHIFT_DISABLE mode to allow HW to recover periodic update of RTC time data into shd_reg	Write 2’d0 to register rtc_io_ctrl[1:0]
8	Process the read-back time data in step 6	Acquire the time data read from rtc_io_test_dout Parse the stored time and separate it into sec, min, hour, day and year Parse the counter during power-off period Calculate new time and set it to the device

To calculate the new time, the following formula can be referenced:

new_rtc_time_data = rtc_io_test_dout[33:0] + rtc_io_test_dout[83:59]

However, some complex situations need to be taken into consideration, such as seconds carrying over to minutes, minutes carrying over to hours, leap year, etc.

Note

• The command that rtc_sio sends to RTC_IO in step 4 takes 5.78ms when osc131k has no frequency deviation.

• If the RTC module initializes the time format in 12-hour format, the RTC_IO module will convert it to 24-hour format and store it. Therefore, when parsing the respective time fields and calculating the new time, this format conversion needs to be considered.

Registers

Name	Address	Width	Description
REG_AON_RTC_IO_CTRL	0x41008048	32 bits	0x41008048[4]: RTC IO mode flag (Read Only) 1: RTC IO domain enabled 0: Disabled (default)
			0x41008048[1:0]: RTC IO control mode (R/W) 0: Shift disable 1: Shift enable 2: RTC mode (once enable , it can’t be disabled)
rtc_io_test_din	0x420080E0	128 bits	0x410080E0[63:58]: LDO_RCAL value receive LDO_RCAL value written by software
rtc_io_test_dout	0x410080C0	128 bits	0x410080C0[33:0]: Binary storage for year/day/hour/minute/second (e.g.: 33sec saved as sec[5:0]=6’b10_0001) sec: 6’b0; 0x4100_80C0[5:0] min: 6’b0; 0x4100_80C0[11:6] hour: 5’b0; 0x4100_80C0[16:12] day: 9’b0; 0x4100_80C0[25:17] year: 8’b0; 0x4100_80C0[33:26]
			0x410080C0 [83:42]: Counter during power-off period, the counter clock is OSC131K.

Functional Description

Clock and Prescaler

A programmable prescaler stage generates a 1Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers.

• A 9-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register.

• A 9-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register.

Note

It is recommended to configure the asynchronous prescaler to a high value to minimize consumption.

By default, the asynchronous prescaler division factor is set to 128, and the synchronous division factor is set to 256, to obtain an internal clock frequency of 1Hz (clk_spre) with 32.768kHz as RTCCLK.

fclk_apre is given by the following formula:

f_clk_apre = f_RTCCLK / (PREDIV_A + 1)

fclk_spre is given by the following formula:

f_clk_spre = f_clk_apre / (PREDIV_S + 1)

Programmable Alarm

The RTC unit provides one programmable alarm.

The programmable alarm function is enabled through the ALME bit in the RTC_CR register. The ALMF is set to ‘1’ if the calendar seconds, minutes, hours or days match the values programmed in the alarm registers RTC_ALMR1L and RTL_ALMR1H. Each calendar field can be independently selected through the MSKx bits. The alarm interrupt is enabled through the ALMIE bit in the RTC_CR register.

Alarm (if enabled by the OSEL [1:0] bits in RTC_CR) can be routed to the RTC_OUT output except when system is in deepsleep mode. The alarm output is a pulse which width is 1/RTCCLK.

Write Protection

After RTC domain reset, all the RTC registers are write-protected. Writing to the RTC registers is enabled by writing a key into the RTC_WPR register.

The following steps are required to unlock the write protection on all the RTC registers except for ALMF in RTC_ISR.

1. Write ‘0xCA’ into the RTC_WPR register.

2. Write ‘0x53’ into the RTC_WPR register.

Writing a wrong key reactivates the write protection. The protection mechanism is not affected by system reset.

Digital Calibration

The digital calibration can be used to compensate RTCCLK inaccuracy by adding (positive calibration) or masking (negative calibration) clock cycles at the output of the asynchronous prescaler (clk_apre).

Positive and negative calibrations are selected by setting the DCS bit to ‘0’ and ‘1’ in RTC_CALIBR register, respectively.

• When positive calibration is enabled (DCS = ‘0’), DC clk_apre cycles are added every (CALP + 1) minutes, which causes the calendar to be updated sooner, thereby adjusting the effective RTC frequency to be a bit higher.

• When negative calibration is enabled (DCS = ‘1’), DC clk_apre cycles are removed every (CALP + 1) minutes, which causes the calendar to be updated later, thereby adjusting the effective RTC frequency to be a bit lower.

DC and CALP can be configured through the RTC_CALIBR register. DC must be less than PREDIV_S in the RTC_PRER register.

The calibration parameter can be configured on-the-fly. Calibration resolution is determined by the frequency of clk_apre and the calibration period. The formula is as follows:

The example is illustrated below:

resolution = period_clk_apre / calp

CALP	clk_apre (128Hz)	clk_apre (256Hz)	clk_apre (512Hz)
1 min.	130.2ppm	65.1ppm	32.55ppm
2 min.	65.1ppm	32.55ppm	16.27ppm
4 min.	32.55ppm	16.27ppm	8.14ppm
8 min.	16.27ppm	8.14ppm	4.07ppm

Re-calibration on-the-fly:

The calibration register (RTC_CALIBR) can be updated on-the-fly while INITF = 0, by following these steps:

• Poll the RECALPF (re-calibration pending flag).

• If RECALPF is set to 0, write a new value to RTC_CALIBR if necessary; RECALPF is then automatically set to 1.

• Within three clk_apre cycles after the write operation to RTC_CALIBR, the new calibration settings take effect.

Day Threshold Program

The RTC provides a day interrupt for users. When the day interrupt is needed, DAY_THRES [8:0] must be programmed first in RTC_CR, and then the DOVTHIE bit in RTC_CR must be set to enable the day over-threshold interrupt.

Daylight Saving

The daylight saving time management is performed through the SUB1H, ADD1H, and BKP bits of the RTC_CR register.

Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in a single operation without going through the initialization procedure. In addition, the software can use the BKP bit to memorize this operation. It is recommended not to change the hour during the calendar hour increment as it could mask the incrementing of the calendar hour. (HW can handle this condition; if this condition occurs, HW will delay the SUB1H or ADD1H operation for 1 second.) When the calendar hour is 0 in the 24-hour system, SUB1H is not supported.

RTC Output

There are two types of RTC output pins which are in different power domains. One type is in the AON domain, which has power in active, sleep, and deep sleep modes. The other type is in the SYSON domain, which can output in active mode and sleep mode, but has no power and cannot output in deep sleep mode. If it had output before, the output continues after wakeup from deep sleep.

The output of rtc_out is determined by the OSEL [1:0] bits in RTC_CR.

Periodic Auto-wakeup

The wakeup function is enabled by setting the WUTE bit in the RTC_CR register.

The clock source of the wakeup timer is ck_spre (usually a 1Hz internal clock). When the ck_spre frequency is 1Hz, this allows a wakeup time from 1 second to around 36 hours with one-second resolution. 3 to 4 wakeup timer cycles after the initialization sequence is complete (refer to programming the wakeup timer), the timer starts counting down. The down-counting remains active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value).

The WUTF flag must then be cleared by software.

When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR register, it can exit the device from low-power modes.

System resets as well as low-power modes have no influence on the wakeup timer.

Once the wakeup timer is initialized and enabled, the wakeup auto-reload value can be changed according to the steps in programming the wakeup timer.

Each time the wakeup timer is enabled, 3 to 4 wakeup timer cycles (usually 3 to 4 seconds) are needed before the wakeup timer works and counting actually begins. Because the enable command is generated in the APB domain, it costs 2 RTC clocks to sync to the RTC domain; another 2 wakeup timer cycles are needed to sync to the wakeup timer domain, and one more wakeup cycle is needed before counting starts. After the sync process of the WUTE bit is complete, the WUTRSF flag bit is set for users to check.

Backup Register

The backup register contains four 32-bit registers, which are used for Realtek and users to save some data before reset happens.

The following table illustrates two reset types which can reset RTC module and backup register, which are both in AON domain. Other reset types can’t reset RTC and backup register.

Reset signal	Reset type	Description
por_rstb	POR	A power on reset is generated when power on
pdr_rstb	PDR	A power down reset is generated when a low level on the CHIP_EN pin (external reset) occurs

The power domain of RTC and backup register is illustrated below.

Item	Sleep (WoWLAN)	Deepsleep
RTC	√	√
Backup register	√	√

Note

√ means this module has power.

Registers

RTC Registers

RTL8721DxRTL8720ERTL8710ERTL8726ERTL8713ERTL8730ERTL8721F

RTL8721Dx:

Base Address: 0x41008A00

Name	Address offset	Access	Description
REG_RTC_TR	000h	R/W	This register is the calendar time shadow register. This register is write protected, and must be written in initialization mode only
REG_RTC_CR	004h	R/W	This register is write protected. Bit[7] (FMT) of this register can be written in initialization mode only when INITF = 1. ADD1H and SUB1H changes are effective in 2~3 seconds. Don’t write this register continuously without any delay when RTC is in free run mode. Software can use the RSF bit in RTC_ISR register to handle the delay.
REG_RTC_ISR	008h	R/W	The ALMF/WUTF/DOVTHF bit can be written without unlocking the write protection. Two APB clock cycles after programming it to 1, this bit is cleaned.
REG_RTC_PRER	00Ch	R/W	This register is write protected, and must be written in initialization mode only.
REG_RTC_CALIBR	010h	R/W	This register is write protected, and can be dynamically configured when RTC is running.
REG_RTC_ALMR1L	014h	R/W	This register is write protected, and can be written only when ALMWF is set to 1 in RTC_ISR register, or in initialization mode.
REG_RTC_ALMR1H	018h	R/W	This register is write protected, and can be written only when ALMWF is set to 1 in RTC_ISR register, or in initialization mode
REG_RTC_WPR	01Ch	R/W	Write “0xCA” then write “0x53” to disable write protection, and write “0xFF” to enable write protection.
REG_RTC_YEAR	020h	R/W	This register is controlled by software.
REG_RTC_WUTR	024h	R/W	This register is used to set wakeup timer value.
REG_RTC_DUMMY	028h	R/W

REG_RTC_TR

• Name: RTC Time Register

• Size: 32

• Address offset: 000h

• Read/write access: R/W

This register is the calendar time shadow register. This register is write protected, and must be

written in initialization mode only

Bit	Symbol	Access	INI	Description
31:23	DAY	R/W	0	DAY in binary format
22	PM	R/W	0	PM:AM/PM notation 0: AM or 24-hour format 1: PM
21:20	HT	R/W	0	Hour tens in BCD format
19:16	HU	R/W	0	Hour units in BCD format
15	RSVD	R	-	Reserved
14:12	MNT	R/W	0	Minute tens in BCD format
11:8	MNU	R/W	0	Minute units in BCD format
7	RSVD	R	-	Reserved
6:4	ST	R/W	0	Second tens in BCD format
3:0	SU	R/W	0	Second units in BCD format

REG_RTC_CR

• Name: RTC Control Register

• Size: 32

• Address offset: 004h

• Read/write access: R/W

This register is write protected. Bit[7] (FMT) of this register can be written in initialization

mode only when INITF = 1. ADD1H and SUB1H changes are effective in 2~3 seconds. Don’t write this

register continuously without any delay when RTC is in free run mode. Software can use the RSF bit

in RTC_ISR register to handle the delay.

Bit	Symbol	Access	INI	Description
31:23	DAY_THRES	R	1FFh	Day threshold in binary format
22:17	RSVD	R	-	Reserved
16	DOVTHIE	R/W	0	Day over threshold interrupt enable 0: Day over threshold interrupt disabled 1: Day over threshold interrupt enabled
15	RSVD	R	-	Reserved
14	WUTIE	R/W	0	Wakeup timer interrupt enable 0: Wakeup timer interrupt disabled 1: Wakeup timer interrupt enabled
13	RSVD	R	-	Reserved
12	ALMIE	R/W	0	Alarm interrupt enable 0: Alarm interrupt disabled 1: Alarm interrupt enabled
11	RSVD	R	-	Reserved
10	WUTE	R/W	0	Wakeup timer enable 0: Wakeup timer disabled 1: Wakeup timer enabled
9	RSVD	R	-	Reserved
8	ALME	R/W	0	Alarm enable 0: Alarm disabled 1: Alarm enabled
7	FMT	R/W	0	Hour format 0: 24 hour/day format 1: AM/PM hour format
6:5	OSEL	R/W	0	Output selection. These bits are used to select the flag to be routed to RTC_OUT output. 00: Output disabled 01: Alarm output enabled 10: Clock output is clk_spre (default: 1Hz) 11: Clock output is clk_apre (default: 256Hz)
4	RSVD	R	-	Reserved
3	BYPSHAD	R/W	0	Bypass the shadow registers. 0: Calendar values (when reading from RTC_TR) are taken from the shadow register, which are updated once every two RTCCLK cycles. 1: Calendar values (when reading from RTC_TR) are taken directly from the calendar counters.
2	BKP	R/W	0	Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
1	SUB1H	R/W	0	Subtract one hour (winter time changes) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0, and this bit is always read as 0. 0: No effect 1: Subtract one hour to the current time
0	ADD1H	R/W	0	Add one hour (summer time changes) When this bit is set outside initialization mode, 1 hour is added to the calendar time, and this bit is always read as 0. 0: No effect 1: Add one hour to the current time

REG_RTC_ISR

• Name: RTC Init Mode and Status Register

• Size: 32

• Address offset: 008h

• Read/write access: R/W

The ALMF/WUTF/DOVTHF bit can be written without unlocking the write protection. Two APB clock cycles

after programming it to 1, this bit is cleaned.

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	RECALPF	R	0	Recalibration pending flag The RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALIBR register, indicating that the RTCCALIBR register is blocked. When the new calibration settings are taken into account, this bit returns to ‘0’. Refer to Re-calibration on-the-fly.
15	DOVTHF	R/W	0	Day over threshold flag This flag is set by hardware when the Day in RTC_TR over the DAY_THRES set in RTC_CR register.
14:11	RSVD	R	-	Reserved
10	WUTF	R/W	0	Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches to. This flag must be cleared by software at least 2 RTCCLK periods before WUTF is set to ‘1’ again.
9	RSVD	R	-	Reserved
8	ALMF	R/W	0	Alarm flag This flag is set by hardware when the time register (RTC_TR) matches the Alarm registers (RTC_ALMR1L and RTC_ALMR1H).
7	INIT	R/W	0	Initialization mode 0: Free running mode. 1: Initialization mode used to program time and date register (RTC_TR) and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is set.
6	INITF	R	0	Initialization flag. When this bit is set to ‘1’, the RTC is in initialization state, and the time, date, and prescaler registers can be updated. 0: Calendar registers update is not allowed. 1: Calendar registers update is allowed.
5	RSF	R/W	0	Registers synchronization flag. This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_TR). This bit is cleared by hardware in initialization mode or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0: Calendar shadow registers are not yet synchronized. 1: Calendar shadow registers are synchronized.
4	INITS	R	0	This bit is set by hardware when the calendar day field is different from 0 (RTC domain reset state). 0: Calendar has not been initialized. 1: Calendar has been initialized.
3	RSVD	R	-	Reserved
2	WUTWF	R	0	Wakeup timer write flag This flag is set by hardware when WUT value can be changed, after the WUTE bit has been set to ‘0’ in RTC_CR. 0: Wakeup timer configuration update not allowed except in initialization mode 1: Wakeup timer configuration update allowed
1	WUTRSF	R/W	0	This bit is set by hardware each time the WUTE bit is copied into the shadow register. This bit is cleared by hardware in initialization mode. This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0: WUTE is not yet synchronized. 1: WUTE is synchronized.
0	ALMWF	R	0	Alarm write flag This bit is set by hardware when Alarm values can be changed, after the ALME bit has been set to ‘0’ in RTC_CR. It is cleared by hardware when ALME bit has been set to ‘1’ in RTC_CR. 0: Alarm update not allowed 1: Alarm update allowed

REG_RTC_PRER

• Name: RTC Prescaler Register

• Size: 32

• Address offset: 00Ch

• Read/write access: R/W

This register is write protected, and must be written in initialization mode only.

Bit	Symbol	Access	INI	Description
31:25	RSVD	R	-	Reserved
24:16	PREDIV_A	R/W	7Fh	Asynchronous prescaler factor This is the asynchronous division factor: clk_apre freq = RTCCLK freq/(PREDIV_A + 1)
15:9	RSVD	R	-	Reserved
8:0	PREDIV_S	R/W	FFh	Synchronous prescaler factor This is the synchronous division factor: clk_spre freq = clk_apre freq/(PREDIV_S + 1)

REG_RTC_CALIBR

• Name: RTC Calibration Register

• Size: 32

• Address offset: 010h

• Read/write access: R/W

This register is write protected, and can be dynamically configured when RTC is running.

Bit	Symbol	Access	INI	Description
31:19	RSVD	R	-	Reserved
18:16	CALP	R/W	0	Calibration period
15	DCE	R/W	0	Digital calibration enable 0: Digital calibration disabled 1: Digital calibration enabled
14	DCS	R/W	0	Digital calibration signal 0: Positive calibration, time update frequency is increased. 1: Negative calibration, time update frequency is decreased.
13:7	RSVD	R	-	Reserved
6:0	DC	R/W	0	Digital calibration

REG_RTC_ALMR1L

• Name: RTC Alarm 1 Register Low

• Size: 32

• Address offset: 014h

• Read/write access: R/W

This register is write protected, and can be written only when ALMWF is set to 1 in RTC_ISR

register, or in initialization mode.

Bit	Symbol	Access	INI	Description
31:24	RSVD	R	-	Reserved
23	MSK2	R/W	0	Alarm hour mask 0: Alarm set if the hours match 1: Hours don’t care in Alarm comparison
22	ALR_PM	R/W	0	AM/PM notation. 0: AM or 24-hour format 1: PM
21:20	ALR_HT	R/W	0	Hour tens in BCD format
19:16	ALR_HU	R/W	0	Hour units in BCD format
15	MSK1	R/W	0	Alarm minutes mask. 0: Alarm set if the minutes match 1: Minutes don’t care in Alarm comparison
14:12	ALR_MNT	R/W	0	Minute tens in BCD format
11:8	ALR_MNU	R/W	0	Minute units in BCD format
7	MSK0	R/W	0	Alarm seconds mask 0: Alarm set if the seconds match 1: Seconds don’t care in Alarm comparison
6:4	ALR_ST	R/W	0	Second tens in BCD format
3:0	ALR_SU	R/W	0	Second units in BCD format

REG_RTC_ALMR1H

• Name: RTC Alarm 1 Register High

• Size: 32

• Address offset: 018h

• Read/write access: R/W

This register is write protected, and can be written only when ALMWF is set to 1 in RTC_ISR

register, or in initialization mode

Bit	Symbol	Access	INI	Description
31:10	RSVD	R	-	Reserved
9	MSK3	R/W	0	Alarm day mask 0: Alarm set if the days match 1: Days don’t care in Alarm comparison
8:0	ALR_DAY	R/W	0	DAY in binary format

REG_RTC_WPR

• Name: RTC Write Protection Register

• Size: 32

• Address offset: 01Ch

• Read/write access: R/W

Write “0xCA” then write “0x53” to disable write protection, and write “0xFF” to enable write

protection.

Bit	Symbol	Access	INI	Description
31:8	RSVD	R	-	Reserved
7:0	KEY	R/W	0	Write protection key This byte is written by software. Refer to RTC register write protection for a description of how to unlock RTC register write protection.

REG_RTC_YEAR

• Name: RTC Year Register

• Size: 32

• Address offset: 020h

• Read/write access: R/W

This register is controlled by software.

Bit	Symbol	Access	INI	Description
31	RESTORE	R/W	0	Reset Flag. Indicates whether any reset conditions have occurred (except POR/PDR/BOD), so that the bit is set to ‘1’ before reset, and then the global variable that determines whether the recovery time information is needed depending on whether the bit is ‘1’.
30:8	RSVD	R	-	Reserved
7:0	YEAR	R/W	0	Year in binary format

REG_RTC_WUTR

• Name: RTC Wakeup Timer Register

• Size: 32

• Address offset: 024h

• Read/write access: R/W

This register is used to set wakeup timer value.

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16:0	WUT	R/W	0	Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE is set to ‘1’), the WUTF flag is set every (WUT[16:0]+1) cycles. The first assertion of WUTF occurs between WUT and (WUT+1) cycles after WUTE is set.

REG_RTC_DUMMY

• Name: RTC Dummy Register

• Size: 32

• Address offset: 028h

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31:0	DUMMY	R/W	ffffh	Dummy register