Basic Timer

Introduction

The Basic Timer is a compact and efficient 32-bit timer peripheral that adopts a pure 32-bit counter architecture without prescaler functionality. Once enabled, the timer starts counting up from its initial value. When the count reaches the user-configured reload register value, it automatically generates a timer update event, clears the counter, and restarts counting, thereby implementing auto-reload continuous cyclic timing functionality.

Features

The features of the basic timer are listed below.

• 32-bit resolution

• Up-counting mode

• Interrupt support

• Auto-reload support

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Name	LS: TIM0 ~ TIM7	HP: TIM10 ~ TIM13
Clock Source	SDM32kHz	XTAL40M

Note

The clock source of TIM10 ~ TIM13 is derived from XTAL40MHz, divided by 40.

Block Diagram

The basic timer mainly consists of a 32-bit counter and a preload register. The block diagram is shown below.

Functional Description

Upcounting Mode

This timer is a 32-bit counter with its related auto-reload register. The counter, as well as the auto-reload register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter register (TIMx_CNT)

• Auto-reload register (TIMx_ARR)

Timer is in count-up mode where the counter counts from 0 to the auto-reload value (the content of the TIMx_ARR register). A counter overflow event is generated after the counter reaches the auto-reload value.

Preloaded Auto-Reload Register

The auto-reload register supports a preload mechanism. Read and write operations to this register actually access the corresponding preload register. The timing of transferring the value from the preload register to the shadow register is controlled by the auto-reload preload enable bit ARPE in the timer control register TIMx_CR: if ARPE is set, the preload value is transferred to the shadow register only when each update event (UEV) occurs; if ARPE is cleared, the preload value is written to the shadow register immediately.

The trigger conditions for an update event (UEV) are divided into two categories: hardware triggers and software triggers. The prerequisite for the operation to take effect is that the update disable bit UDIS in the TIMx_CR register is 0, meaning all update functions are enabled.

1. Hardware trigger: When the counter operates in count-up mode and the count value reaches the overflow state, the hardware automatically generates an update event;

2. Software trigger: This is achieved by setting the update generation bit UG in the timer event generation register TIMx_EGR via software. The prerequisite for this operation to take effect is that the update disable bit URS in the TIMx_CR register is 0, meaning the software update function is not masked.

By setting the UDIS bit in the TIMx_CR register, the generation of update events can be globally disabled. This prevents the shadow register from being synchronously updated while writing a new reload value to the preload register, ensuring the stability of the configuration write. No trigger condition will generate an update event until the UDIS bit is cleared.

When an update event effectively occurs, the timer-related registers are updated. Meanwhile, the auto-reload shadow register loads the current value from the preload register TIMx_ARR, completing the synchronous update of the reload value.

Interrupt Event

Interrupt events can be enabled through the TIMx_DIER register. When the UIE bit is 1, an interrupt event occurrence will trigger a system interrupt. Hardware overflow and software-triggered updates both generate interrupts. The corresponding interrupt status can be checked via the UIF bit in TIMx_SR, and the interrupt can be cleared by writing to UIF.

Security Attribution

Basic Timer peripherals do not independently occupy a peripheral port on a per-timer basis. Their port resources are typically shared by multiple timers within the same peripheral port, corresponding to a single PPC (Peripheral Permission Controller). Since the security attribution of a shared port is configured uniformly by the PPC, independent configuration of individual timer security attribution is not achievable. To support flexible configuration of each basic timer’s security attribution, every basic timer integrates a dedicated security control register. This security control register contains a security enable bit for independently configuring the security attribution of the corresponding timer. It is accessible only from the secure world; the non-secure world cannot perform read or write operations on it. When the timer security enable bit is set, the timer is configured as a secure timer. All of its registers are accessible only through secure addresses, and non-secure address access is prohibited. When the security enable bit is cleared, the timer is configured as a non-secure timer. With the exception of the security control register, all other registers can be accessed through both secure and non-secure addresses.

Registers

Basic Timer Registers

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Base Address:

• TIMER0_REG : 0x41017000

• TIMER1_REG : 0x41017200

• TIMER2_REG : 0x41017400

• TIMER3_REG : 0x41017600

• TIMER4_REG : 0x41017800

• TIMER5_REG : 0x41017A00

• TIMER6_REG : 0x41017C00

• TIMER7_REG : 0x41017E00

• TIMER10_REG : 0x41100400

• TIMER11_REG : 0x41100600

Name	Address offset	Access	Description
REG_TIM_EN	000h	R/W	Users can configure and observe the counter operation.
REG_TIM_CR	004h	R/W	This register is about the update operation.
REG_TIM_DIER	008h	R/W	This is the interrupt enable register.
REG_TIM_SR	00Ch	R/W	This register is about timer interrupt and update status.
REG_TIM_EGR	010h	R/W	This register is about update generation, and is user defined.
REG_TIM_CNT	014h	R	This is the timer count register.
REG_TIM_ARR	01Ch	R/W	This is the auto-reload value register.
REG_TIM_SEC	020h	R/W	This register is about security status.
REG_TIM_BASIC_DUMMY	024h	R/W

REG_TIM_EN

• Name: TIM enable register

• Size: 32

• Address offset: 000h

• Read/write access: R/W

Users can configure and observe the counter operation.

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	CNT_EN	R	0x0	Counter working status 0: Counter is stopped 1: Counter is working
15:9	RSVD	R	-	Reserved
8	CNT_RUN	R	0x0	Counter run status 0: Counter is disabled 1: Counter is enabled
7:2	RSVD	R	-	Reserved
1	CNT_STOP	R/W	0x0	Disable the counter Poll CNT_RUN to see the counter status. If CNT_RUN is 0, it means that the counter has been disabled internally.
0	CNT_START	R/W	0x0	Enable the counter Poll CNT_RUN to see the counter status. If CNT_RUN is 1, it means that the counter has been enabled internally.

REG_TIM_CR

• Name: TIM control register

• Size: 32

• Address offset: 004h

• Read/write access: R/W

This register is about the update operation.

Bit	Symbol	Access	INI	Description
31:5	RSVD	R	-	Reserved
4	ARPE	R/W	0x0	Enable auto-reload preloading 0: TIM_ARR register is not buffered. 1: TIM_ARR register is buffered.
3	RSVD	R	-	Reserved
2	URS	R/W	0x0	Update request source 0: Counter overflow and setting the UG bit 1: Counter overflow
1	UDIS	R/W	0x0	Disable UEV Shadow registers keep their values. Otherwise, buffered registers are then loaded with their preload values when UEV happens.
0	RSVD	R	-	Reserved

REG_TIM_DIER

• Name: TIM interrupt enable register

• Size: 32

• Address offset: 008h

• Read/write access: R/W

This is the interrupt enable register.

Bit	Symbol	Access	INI	Description
31:1	RSVD	R	-	Reserved
0	UIE	R/W	0x0	Enable update interrupt

REG_TIM_SR

• Name: TIM status register

• Size: 32

• Address offset: 00Ch

• Read/write access: R/W

This register is about timer interrupt and update status.

Bit	Symbol	Access	INI	Description
31	UG_DONE	R	0x1	UG operation status This bit is cleared by hardware when the UG bit in the TIMx_EGR register is set. When the UG operation is done, hardware set this bit to ‘1’. So, software can poll this bit to see the UG operation status.
30:1	RSVD	R	-	Reserved
0	UIF	R/W	0x0	Update interrupt flag

REG_TIM_EGR

• Name: TIM event generation register

• Size: 32

• Address offset: 010h

• Read/write access: R/W

This register is about update generation, and is user defined.

Bit	Symbol	Access	INI	Description
31:1	RSVD	R	-	Reserved
0	UG	R/W	0x0	Update generation Re-initialize the counter and generate an update of registers. Note that the prescaler counter is cleared too. (anyway the prescaler ratio is not affected)

REG_TIM_CNT

• Name: TIM counter register

• Size: 32

• Address offset: 014h

• Read/write access: R

This is the timer count register.

Bit	Symbol	Access	INI	Description
31:0	CNT	R	0x0	Counter value

REG_TIM_ARR

• Name: TIM auto-reload register

• Size: 32

• Address offset: 01Ch

• Read/write access: R/W

This is the auto-reload value register.

Bit	Symbol	Access	INI	Description
31:0	ARR	R/W	0xFFFFFFFF	The value to be loaded in the actual auto-reload register. It can be preloaded by setting ARPE bit in TIM_CR.

REG_TIM_SEC

• Name: TIM security control register

• Size: 32

• Address offset: 020h

• Read/write access: R/W

This register is about security status.

Bit	Symbol	Access	INI	Description
31:1	RSVD	R	-	Reserved
0	SEC	R/W	0x0	Secure timer enable 0: This is a non-secure timer. All its registers except TIMx_SEC can be accessed from both secure and non-secure address. As a result, both secure and non-secure code can access it. 1: This is a secure timer. All its registers can only be accessed from secure address. As a result, only secure code can access it. Non-secure code can’t access it through non-secure address.

REG_TIM_BASIC_DUMMY

• Name: Timer Basic Dummy Register

• Size: 32

• Address offset: 024h

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31:0	DUMMY	R/W	ffffh	Dummy register