Analog-to-Digital Converter
Introduction
Analog-to-digital converter (ADC) is a successive-approximation register (SAR) ADC, which includes external channels and internal channels.
ADC supports multiple sampling modes, e.g. continuous sampling, software-trigger sampling and timer-trigger sampling. The ADC conversion result is stored in the result register and can be read on demand.
Features
The features of ADC are listed below:
Resolution: 12-bit SAR
Available channel number
7x external channels and 1x VBAT channel
3x internal channels
Input voltage range
External channels: 0V ~ min(VAH_ADC, 3.3 V)
VBAT channel: 0V ~ 5V (for battery)
ADC supply requirement (VAH_ADC): 1.8V to 3.63 V
Contain 64 x 20-bit FIFO entries for storing the conversion results
Multiple sampling mode:
Auto continuous sampling
Hardware oversample for higher SNR
Available channel number
6x external channels
3x internal channels
Input voltage range: 0V ~ min(VAH_AUX, 3.3 V)
ADC supply requirement (VAH_AUX): 2.97 V to 3.63 V
Contain 64 x 16-bit FIFO entries for storing the conversion results
Multiple sampling mode:
Auto continuous sampling
Software-trigger sampling
Timer-trigger sampling
Available channel number
6x external channels
3x internal channels
Input voltage range: 0V ~ min(VAH_AUX, 3.3 V)
ADC supply requirement (VAH_AUX): 2.97 V to 3.63 V
Contain 64 x 16-bit FIFO entries for storing the conversion results
Multiple sampling mode:
Auto continuous sampling
Software-trigger sampling
Timer-trigger sampling
Available channel number
6x external channels
3x internal channels
Input voltage range: 0V ~ min(VAH_AUX, 3.3 V)
ADC supply requirement (VAH_AUX): 2.97 V to 3.63 V
Contain 64 x 16-bit FIFO entries for storing the conversion results
Multiple sampling mode:
Auto continuous sampling
Software-trigger sampling
Timer-trigger sampling
Available channel number
6x external channels
3x internal channels
Input voltage range: 0V ~ min(VAH_AUX, 3.3 V)
ADC supply requirement (VAH_AUX): 2.97 V to 3.63 V
Contain 64 x 16-bit FIFO entries for storing the conversion results
Multiple sampling mode:
Auto continuous sampling
Software-trigger sampling
Timer-trigger sampling
Available channel number
6x external channels and 1x VBAT channel
3x internal channels
Input voltage range
External channels: 0V ~ 1.8V
VBAT channel: 0V ~ 5V (for battery)
ADC supply requirement (VAH_PLL): 2.97 V to 3.63 V
Contain 64 x 16-bit FIFO entries for storing the conversion results
Multiple sampling mode:
Auto continuous sampling
Software-trigger sampling
Timer-trigger sampling
Available channel number
8x external channels
4x internal channels
Input voltage range: 0V ~ min(VAH_ADC, 3.3 V)
ADC supply requirement (VAH_ADC): 2.97 V to 3.63 V
Contain 64 x 20-bit FIFO entries for storing the conversion results
Multiple sampling mode:
Auto continuous sampling
Software-trigger sampling
Timer-trigger sampling
Hardware oversample for higher SNR
Configurable ADC clock source and sampling rate
Configurable channel switch order and channel number through the channel list
Individual channel register for storing the conversion results and status
Built-in calibration
Multiple interrupts:
End of channel list scan
End of the specific channel scan
Independent comparison event of each channel
Data overwritten situation
FIFO empty, FIFO overflow and FIFO full status
Block Diagram
The following figure shows the block diagram of the 12-bit ADC.
Functional Description
Channel Switch List
The ADC provides a mechanism that allows software to configure the complete conversion sequence via an ADC channel switch list. Software can specify the target channel numbers to be converted with two registers (REG_ADC_CHSW_LIST_0 and REG_ADC_CHSW_LIST_1). The list length field in the REG_ADC_CONF[7:4] register can be configured to configure the number of channels in the sequence.
For example, consider the values configured for REG_ADC_CHSW_LIST_0 and REG_ADC_CHSW_LIST_1 as shown in the following table:
Register |
[3:0] |
[7:4] |
[11:8] |
[15:12] |
[19:16] |
[23:20] |
[27:24] |
[31:28] |
|---|---|---|---|---|---|---|---|---|
REG_ADC_CHSW_LIST_0 |
0 |
1 |
2 |
3 |
4 |
5 |
9 |
0 |
REG_ADC_CHSW_LIST_1 |
1 |
9 |
5 |
4 |
3 |
2 |
1 |
0 |
If REG_ADC_CONF[7:4] is set to 9, the ADC converts only the first 10(the value of REG_ADC_CONF[7:4] + 1) channels in the list. When operating in Auto mode, the ADC performs conversions sequentially from the first channel to the last channel specified in the list. Once the channel length count reaches the value configured in REG_ADC_CONF[7:4], the ADC restarts the conversion sequence from the first channel (as illustrated in the following figure).
Auto_Mode_Waveform
The REG_ADC_LAST_CH[3:0] field indicates the last converted channel, which helps in tracking the current position within the sequence. Additionally, the REG_ADC_BUSY_STS[0] bit indicates the ADC’s busy status; it remains 1 while the ADC is actively processing a channel conversion.
Operation Mode
Ameba supports only one operation mode: auto mode.
Auto Mode
In auto mode, ADC continuously executes conversions without any trigger sources after auto channel switch register is set. Auto mode would not stop conversions until auto channel switch register is clear (register REG_ADC_AUTO_CSW_CTRL [0]) or the auto channel switch is disabled (register REG_ADC_CONF[3:1]).
In auto mode, ADC samples automatically by hardware without assistance of core or other modules, it can be applied to the situation where core resources are limited and real-time detection is required. Refer to Auto_Mode_Waveform for the auto mode waveform.
The ADC will scan the channels in the list in order. There is no interval between the adjacent channels, and the scanning speed only depends on the sampling rate of the ADC. At the end of the sampling period, the ADC immediately outputs the data to register and FIFO. So there is no need to set the CH switching time and settling time.
Because the sampled data is continuously filled into the register and FIFO when the REG_ADC_AUTO_CSW_CTRL [0] is set, if the data cannot be taken out, the data will be lost and the overflowed data will not be filled into the FIFO. For intermittent data getting from FIFO, FIFO clearing is recommended before getting.
However, there is a situation that needs to be paid attention to: if the internal resistance of the signal source sampled by ADC is very large, the input signal is easy to receive interference.
The solution is as follows:
Reduce the impedance
As shown in the following figure, operational amplifier (OA) provides extremely low output impedance.
Arrange Grounding Isolation Channel in channel list
As shown in the following figure, using a GND channel (internal GND channel or external channel which is connected to GND), configure the channel list of ADC to: CH0, CH_GND, CH1, CH_GND, CH2 … CH5, CH_GND. This avoids crosstalk, and the resulting inter-channel delay depends on the sampling rate of the ADC and the configuration of the channel list.
Ameba supports three different operation modes: auto mode, timer-trigger mode, and software-trigger mode.
Although various modes are available to meet specific requirements, only one operation mode can be active at a time. All modes execute conversions based on the channel switch list. The primary distinction between these operation modes lies in the trigger source, which drives the ADC module to perform conversions.
Auto Mode
In auto mode, ADC continuously executes conversions without any trigger sources after auto channel switch register is set. Auto mode would not stop conversions until auto channel switch register is clear (register REG_ADC_AUTO_CSW_CTRL [0]) or the auto channel switch is disabled (register REG_ADC_CONF[3:1]).
In auto mode, ADC samples automatically by hardware without assistance of core or other modules, it can be applied to the situation where core resources are limited and real-time detection is required. Refer to Auto_Mode_Waveform for the auto mode waveform.
The ADC will scan the channels in the list in order. There is no interval between the adjacent channels, and the scanning speed only depends on the sampling rate of the ADC. At the end of the sampling period, the ADC immediately outputs the data to register and FIFO. So there is no need to set the CH switching time and settling time.
Because the sampled data is continuously filled into the register and FIFO when the REG_ADC_AUTO_CSW_CTRL [0] is set, if the data cannot be taken out, the data will be lost and the overflowed data will not be filled into the FIFO. For intermittent data getting from FIFO, FIFO clearing is recommended before getting.
However, there is a situation that needs to be paid attention to: if the internal resistance of the signal source sampled by ADC is very large, the input signal is easy to receive interference.
The solution is as follows:
Reduce the impedance
As shown in the following figure, operational amplifier (OA) provides extremely low output impedance.
Arrange Grounding Isolation Channel in channel list
As shown in the following figure, using a GND channel (internal GND channel or external channel which is connected to GND), configure the channel list of ADC to: CH0, CH_GND, CH1, CH_GND, CH2 … CH5, CH_GND. This avoids crosstalk, and the resulting inter-channel delay depends on the sampling rate of the ADC and the configuration of the channel list.
Timer-trigger Mode
In timer-trigger mode, ADC can cooperate with timer modules to do conversions. System software sets timer trigger control register to enable timer module and set an appropriate timer event period. After that, ADC do one conversions when one timer event occurs based on system design.
Same as auto mode, the time- trigger mode can work independently without system software, which means it can reduce the core resources partly. What’s more, ADC can automatically go to shut down mode between two timer trigger events that can largely reduce the ADC power consumption itself. Refer to the following figure for the timer-trigger mode waveform.
After each trigger, ADC will power on and perform the sampling conversion, and immediately store the results in the register and FIFO, after which ADC will power down. Until the next trigger signal arrives, ADC will re-power on and perform the entire list channel sampling conversion.
Therefore, the interval time between adjacent trigger is limited by the power-on time of ADC, and the recommended interval is not less than 1ms. Sampling during the power-on of ADC is not complete, which may result in data errors. After power-on, ADC starts sampling immediately, and the sampling period is determined by the sampling rate.
Same as auto mode, at the end of the sampling period, the ADC immediately outputs the data to register and FIFO.
Note
The current IC supports up to 8 timer sources (timer 0~7).
Every time trigger source is generated, only one channel in the channel list will be sampled.
Software-trigger Mode
The software-trigger mode is similar with timer-trigger mode, and the difference between them is the trigger source. For general usage, system software tends to handle ADC conversion timing. Every time software trigger register (REG_ADC_SW_TRIG[0]) is set, ADC module performs channel sampling conversion. System software checks ready/busy register (REG_ADC_BUSY_STS[0]) before reading conversion data register (REG_ADC_DATA_GLOBAL[15:0]).
Compared with timer-trigger mode, this mode is more flexible. Software can manually trigger ADC sampling according to the actual situation, and the trigger time is not fixed. Refer to the following figure for the software-trigger mode waveform.
Similar to timer-trigger mode, between every two triggers, ADC enters the sleep state, and the trigger needs to be re-power on. As a result, the trigger interval should not be too short. It is recommended that the trigger interval should not be less than 1ms.
Note
Every time trigger source is generated, only one channel in the channel list will be sampled.
Summary
The following table shows the differences and applications of different operation modes.
Operation mode |
Configuration |
Difference |
Applications |
|---|---|---|---|
Auto mode |
REG_ADC_CONF[3:1] = 1 |
|
The case that needs real-time detection and more consumption. |
Timer-trigger mode |
REG_ADC_CONF[3:1] = 2 |
|
The case that needs periodic monitoring and less consumption. |
Software-trigger mode |
REG_ADC_CONF[3:1] = 0 REG_ADC_SW_TRIG[0] = 1 |
Need software but be more flexible |
The case that flexibly triggers ADC according to the current environment. |
Ameba supports three different operation modes: auto mode, timer-trigger mode, and software-trigger mode.
Although various modes are available to meet specific requirements, only one operation mode can be active at a time. All modes execute conversions based on the channel switch list. The primary distinction between these operation modes lies in the trigger source, which drives the ADC module to perform conversions.
Auto Mode
In auto mode, ADC continuously executes conversions without any trigger sources after auto channel switch register is set. Auto mode would not stop conversions until auto channel switch register is clear (register REG_ADC_AUTO_CSW_CTRL [0]) or the auto channel switch is disabled (register REG_ADC_CONF[3:1]).
In auto mode, ADC samples automatically by hardware without assistance of core or other modules, it can be applied to the situation where core resources are limited and real-time detection is required. Refer to Auto_Mode_Waveform for the auto mode waveform.
The ADC will scan the channels in the list in order. There is no interval between the adjacent channels, and the scanning speed only depends on the sampling rate of the ADC. At the end of the sampling period, the ADC immediately outputs the data to register and FIFO. So there is no need to set the CH switching time and settling time.
Because the sampled data is continuously filled into the register and FIFO when the REG_ADC_AUTO_CSW_CTRL [0] is set, if the data cannot be taken out, the data will be lost and the overflowed data will not be filled into the FIFO. For intermittent data getting from FIFO, FIFO clearing is recommended before getting.
However, there is a situation that needs to be paid attention to: if the internal resistance of the signal source sampled by ADC is very large, the input signal is easy to receive interference.
The solution is as follows:
Reduce the impedance
As shown in the following figure, operational amplifier (OA) provides extremely low output impedance.
Arrange Grounding Isolation Channel in channel list
As shown in the following figure, using a GND channel (internal GND channel or external channel which is connected to GND), configure the channel list of ADC to: CH0, CH_GND, CH1, CH_GND, CH2 … CH5, CH_GND. This avoids crosstalk, and the resulting inter-channel delay depends on the sampling rate of the ADC and the configuration of the channel list.
Timer-trigger Mode
In timer-trigger mode, ADC can cooperate with timer modules to do conversions. System software sets timer trigger control register to enable timer module and set an appropriate timer event period. After that, ADC do one conversions when one timer event occurs based on system design.
Same as auto mode, the time- trigger mode can work independently without system software, which means it can reduce the core resources partly. What’s more, ADC can automatically go to shut down mode between two timer trigger events that can largely reduce the ADC power consumption itself. Refer to the following figure for the timer-trigger mode waveform.
After each trigger, ADC will power on and perform the sampling conversion, and immediately store the results in the register and FIFO, after which ADC will power down. Until the next trigger signal arrives, ADC will re-power on and perform the entire list channel sampling conversion.
Therefore, the interval time between adjacent trigger is limited by the power-on time of ADC, and the recommended interval is not less than 1ms. Sampling during the power-on of ADC is not complete, which may result in data errors. After power-on, ADC starts sampling immediately, and the sampling period is determined by the sampling rate.
Same as auto mode, at the end of the sampling period, the ADC immediately outputs the data to register and FIFO.
Note
The current IC supports up to 8 timer sources (timer 0~7).
Every time trigger source is generated, only one channel in the channel list will be sampled.
Software-trigger Mode
The software-trigger mode is similar with timer-trigger mode, and the difference between them is the trigger source. For general usage, system software tends to handle ADC conversion timing. Every time software trigger register (REG_ADC_SW_TRIG[0]) is set, ADC module performs channel sampling conversion. System software checks ready/busy register (REG_ADC_BUSY_STS[0]) before reading conversion data register (REG_ADC_DATA_GLOBAL[15:0]).
Compared with timer-trigger mode, this mode is more flexible. Software can manually trigger ADC sampling according to the actual situation, and the trigger time is not fixed. Refer to the following figure for the software-trigger mode waveform.
Similar to timer-trigger mode, between every two triggers, ADC enters the sleep state, and the trigger needs to be re-power on. As a result, the trigger interval should not be too short. It is recommended that the trigger interval should not be less than 1ms.
Note
Every time trigger source is generated, only one channel in the channel list will be sampled.
Summary
The following table shows the differences and applications of different operation modes.
Operation mode |
Configuration |
Difference |
Applications |
|---|---|---|---|
Auto mode |
REG_ADC_CONF[3:1] = 1 |
|
The case that needs real-time detection and more consumption. |
Timer-trigger mode |
REG_ADC_CONF[3:1] = 2 |
|
The case that needs periodic monitoring and less consumption. |
Software-trigger mode |
REG_ADC_CONF[3:1] = 0 REG_ADC_SW_TRIG[0] = 1 |
Need software but be more flexible |
The case that flexibly triggers ADC according to the current environment. |
Ameba supports three different operation modes: auto mode, timer-trigger mode, and software-trigger mode.
Although various modes are available to meet specific requirements, only one operation mode can be active at a time. All modes execute conversions based on the channel switch list. The primary distinction between these operation modes lies in the trigger source, which drives the ADC module to perform conversions.
Auto Mode
In auto mode, ADC continuously executes conversions without any trigger sources after auto channel switch register is set. Auto mode would not stop conversions until auto channel switch register is clear (register REG_ADC_AUTO_CSW_CTRL [0]) or the auto channel switch is disabled (register REG_ADC_CONF[3:1]).
In auto mode, ADC samples automatically by hardware without assistance of core or other modules, it can be applied to the situation where core resources are limited and real-time detection is required. Refer to Auto_Mode_Waveform for the auto mode waveform.
The ADC will scan the channels in the list in order. There is no interval between the adjacent channels, and the scanning speed only depends on the sampling rate of the ADC. At the end of the sampling period, the ADC immediately outputs the data to register and FIFO. So there is no need to set the CH switching time and settling time.
Because the sampled data is continuously filled into the register and FIFO when the REG_ADC_AUTO_CSW_CTRL [0] is set, if the data cannot be taken out, the data will be lost and the overflowed data will not be filled into the FIFO. For intermittent data getting from FIFO, FIFO clearing is recommended before getting.
However, there is a situation that needs to be paid attention to: if the internal resistance of the signal source sampled by ADC is very large, the input signal is easy to receive interference.
The solution is as follows:
Reduce the impedance
As shown in the following figure, operational amplifier (OA) provides extremely low output impedance.
Arrange Grounding Isolation Channel in channel list
As shown in the following figure, using a GND channel (internal GND channel or external channel which is connected to GND), configure the channel list of ADC to: CH0, CH_GND, CH1, CH_GND, CH2 … CH5, CH_GND. This avoids crosstalk, and the resulting inter-channel delay depends on the sampling rate of the ADC and the configuration of the channel list.
Timer-trigger Mode
In timer-trigger mode, ADC can cooperate with timer modules to do conversions. System software sets timer trigger control register to enable timer module and set an appropriate timer event period. After that, ADC do one conversions when one timer event occurs based on system design.
Same as auto mode, the time- trigger mode can work independently without system software, which means it can reduce the core resources partly. What’s more, ADC can automatically go to shut down mode between two timer trigger events that can largely reduce the ADC power consumption itself. Refer to the following figure for the timer-trigger mode waveform.
After each trigger, ADC will power on and perform the sampling conversion, and immediately store the results in the register and FIFO, after which ADC will power down. Until the next trigger signal arrives, ADC will re-power on and perform the entire list channel sampling conversion.
Therefore, the interval time between adjacent trigger is limited by the power-on time of ADC, and the recommended interval is not less than 1ms. Sampling during the power-on of ADC is not complete, which may result in data errors. After power-on, ADC starts sampling immediately, and the sampling period is determined by the sampling rate.
Same as auto mode, at the end of the sampling period, the ADC immediately outputs the data to register and FIFO.
Note
The current IC supports up to 8 timer sources (timer 0~7).
Every time trigger source is generated, only one channel in the channel list will be sampled.
Software-trigger Mode
The software-trigger mode is similar with timer-trigger mode, and the difference between them is the trigger source. For general usage, system software tends to handle ADC conversion timing. Every time software trigger register (REG_ADC_SW_TRIG[0]) is set, ADC module performs channel sampling conversion. System software checks ready/busy register (REG_ADC_BUSY_STS[0]) before reading conversion data register (REG_ADC_DATA_GLOBAL[15:0]).
Compared with timer-trigger mode, this mode is more flexible. Software can manually trigger ADC sampling according to the actual situation, and the trigger time is not fixed. Refer to the following figure for the software-trigger mode waveform.
Similar to timer-trigger mode, between every two triggers, ADC enters the sleep state, and the trigger needs to be re-power on. As a result, the trigger interval should not be too short. It is recommended that the trigger interval should not be less than 1ms.
Note
Every time trigger source is generated, only one channel in the channel list will be sampled.
Summary
The following table shows the differences and applications of different operation modes.
Operation mode |
Configuration |
Difference |
Applications |
|---|---|---|---|
Auto mode |
REG_ADC_CONF[3:1] = 1 |
|
The case that needs real-time detection and more consumption. |
Timer-trigger mode |
REG_ADC_CONF[3:1] = 2 |
|
The case that needs periodic monitoring and less consumption. |
Software-trigger mode |
REG_ADC_CONF[3:1] = 0 REG_ADC_SW_TRIG[0] = 1 |
Need software but be more flexible |
The case that flexibly triggers ADC according to the current environment. |
Ameba supports three different operation modes: auto mode, timer-trigger mode, and software-trigger mode.
Although various modes are available to meet specific requirements, only one operation mode can be active at a time. All modes execute conversions based on the channel switch list. The primary distinction between these operation modes lies in the trigger source, which drives the ADC module to perform conversions.
Auto Mode
In auto mode, ADC continuously executes conversions without any trigger sources after auto channel switch register is set. Auto mode would not stop conversions until auto channel switch register is clear (register REG_ADC_AUTO_CSW_CTRL [0]) or the auto channel switch is disabled (register REG_ADC_CONF[3:1]).
In auto mode, ADC samples automatically by hardware without assistance of core or other modules, it can be applied to the situation where core resources are limited and real-time detection is required. Refer to Auto_Mode_Waveform for the auto mode waveform.
The ADC will scan the channels in the list in order. There is no interval between the adjacent channels, and the scanning speed only depends on the sampling rate of the ADC. At the end of the sampling period, the ADC immediately outputs the data to register and FIFO. So there is no need to set the CH switching time and settling time.
Because the sampled data is continuously filled into the register and FIFO when the REG_ADC_AUTO_CSW_CTRL [0] is set, if the data cannot be taken out, the data will be lost and the overflowed data will not be filled into the FIFO. For intermittent data getting from FIFO, FIFO clearing is recommended before getting.
However, there is a situation that needs to be paid attention to: if the internal resistance of the signal source sampled by ADC is very large, the input signal is easy to receive interference.
The solution is as follows:
Reduce the impedance
As shown in the following figure, operational amplifier (OA) provides extremely low output impedance.
Arrange Grounding Isolation Channel in channel list
As shown in the following figure, using a GND channel (internal GND channel or external channel which is connected to GND), configure the channel list of ADC to: CH0, CH_GND, CH1, CH_GND, CH2 … CH5, CH_GND. This avoids crosstalk, and the resulting inter-channel delay depends on the sampling rate of the ADC and the configuration of the channel list.
Timer-trigger Mode
In timer-trigger mode, ADC can cooperate with timer modules to do conversions. System software sets timer trigger control register to enable timer module and set an appropriate timer event period. After that, ADC do one conversions when one timer event occurs based on system design.
Same as auto mode, the time- trigger mode can work independently without system software, which means it can reduce the core resources partly. What’s more, ADC can automatically go to shut down mode between two timer trigger events that can largely reduce the ADC power consumption itself. Refer to the following figure for the timer-trigger mode waveform.
After each trigger, ADC will power on and perform the sampling conversion, and immediately store the results in the register and FIFO, after which ADC will power down. Until the next trigger signal arrives, ADC will re-power on and perform the entire list channel sampling conversion.
Therefore, the interval time between adjacent trigger is limited by the power-on time of ADC, and the recommended interval is not less than 1ms. Sampling during the power-on of ADC is not complete, which may result in data errors. After power-on, ADC starts sampling immediately, and the sampling period is determined by the sampling rate.
Same as auto mode, at the end of the sampling period, the ADC immediately outputs the data to register and FIFO.
Note
The current IC supports up to 8 timer sources (timer 0~7).
Every time trigger source is generated, only one channel in the channel list will be sampled.
Software-trigger Mode
The software-trigger mode is similar with timer-trigger mode, and the difference between them is the trigger source. For general usage, system software tends to handle ADC conversion timing. Every time software trigger register (REG_ADC_SW_TRIG[0]) is set, ADC module performs channel sampling conversion. System software checks ready/busy register (REG_ADC_BUSY_STS[0]) before reading conversion data register (REG_ADC_DATA_GLOBAL[15:0]).
Compared with timer-trigger mode, this mode is more flexible. Software can manually trigger ADC sampling according to the actual situation, and the trigger time is not fixed. Refer to the following figure for the software-trigger mode waveform.
Similar to timer-trigger mode, between every two triggers, ADC enters the sleep state, and the trigger needs to be re-power on. As a result, the trigger interval should not be too short. It is recommended that the trigger interval should not be less than 1ms.
Note
Every time trigger source is generated, only one channel in the channel list will be sampled.
Summary
The following table shows the differences and applications of different operation modes.
Operation mode |
Configuration |
Difference |
Applications |
|---|---|---|---|
Auto mode |
REG_ADC_CONF[3:1] = 1 |
|
The case that needs real-time detection and more consumption. |
Timer-trigger mode |
REG_ADC_CONF[3:1] = 2 |
|
The case that needs periodic monitoring and less consumption. |
Software-trigger mode |
REG_ADC_CONF[3:1] = 0 REG_ADC_SW_TRIG[0] = 1 |
Need software but be more flexible |
The case that flexibly triggers ADC according to the current environment. |
Ameba supports three different operation modes: auto mode, timer-trigger mode, and software-trigger mode.
Although various modes are available to meet specific requirements, only one operation mode can be active at a time. All modes execute conversions based on the channel switch list. The primary distinction between these operation modes lies in the trigger source, which drives the ADC module to perform conversions.
Auto Mode
In auto mode, ADC continuously executes conversions without any trigger sources after auto channel switch register is set. Auto mode would not stop conversions until auto channel switch register is clear (register REG_ADC_AUTO_CSW_CTRL [0]) or the auto channel switch is disabled (register REG_ADC_CONF[3:1]).
In auto mode, ADC samples automatically by hardware without assistance of core or other modules, it can be applied to the situation where core resources are limited and real-time detection is required. Refer to Auto_Mode_Waveform for the auto mode waveform.
The ADC will scan the channels in the list in order. There is no interval between the adjacent channels, and the scanning speed only depends on the sampling rate of the ADC. At the end of the sampling period, the ADC immediately outputs the data to register and FIFO. So there is no need to set the CH switching time and settling time.
Because the sampled data is continuously filled into the register and FIFO when the REG_ADC_AUTO_CSW_CTRL [0] is set, if the data cannot be taken out, the data will be lost and the overflowed data will not be filled into the FIFO. For intermittent data getting from FIFO, FIFO clearing is recommended before getting.
However, there is a situation that needs to be paid attention to: if the internal resistance of the signal source sampled by ADC is very large, the input signal is easy to receive interference.
The solution is as follows:
Reduce the impedance
As shown in the following figure, operational amplifier (OA) provides extremely low output impedance.
Arrange Grounding Isolation Channel in channel list
As shown in the following figure, using a GND channel (internal GND channel or external channel which is connected to GND), configure the channel list of ADC to: CH0, CH_GND, CH1, CH_GND, CH2 … CH5, CH_GND. This avoids crosstalk, and the resulting inter-channel delay depends on the sampling rate of the ADC and the configuration of the channel list.
Timer-trigger Mode
In timer-trigger mode, ADC can cooperate with timer modules to do conversions. System software sets timer trigger control register to enable timer module and set an appropriate timer event period. After that, ADC do one conversions when one timer event occurs based on system design.
Same as auto mode, the time- trigger mode can work independently without system software, which means it can reduce the core resources partly. What’s more, ADC can automatically go to shut down mode between two timer trigger events that can largely reduce the ADC power consumption itself. Refer to the following figure for the timer-trigger mode waveform.
After each trigger, ADC will power on and perform the sampling conversion, and immediately store the results in the register and FIFO, after which ADC will power down. Until the next trigger signal arrives, ADC will re-power on and perform the entire list channel sampling conversion.
Therefore, the interval time between adjacent trigger is limited by the power-on time of ADC, and the recommended interval is not less than 1ms. Sampling during the power-on of ADC is not complete, which may result in data errors. After power-on, ADC starts sampling immediately, and the sampling period is determined by the sampling rate.
Same as auto mode, at the end of the sampling period, the ADC immediately outputs the data to register and FIFO.
Note
The current IC supports up to 8 timer sources (timer 0~7).
Every time trigger source is generated, only one channel in the channel list will be sampled.
Software-trigger Mode
The software-trigger mode is similar with timer-trigger mode, and the difference between them is the trigger source. For general usage, system software tends to handle ADC conversion timing. Every time software trigger register (REG_ADC_SW_TRIG[0]) is set, ADC module performs channel sampling conversion. System software checks ready/busy register (REG_ADC_BUSY_STS[0]) before reading conversion data register (REG_ADC_DATA_GLOBAL[15:0]).
Compared with timer-trigger mode, this mode is more flexible. Software can manually trigger ADC sampling according to the actual situation, and the trigger time is not fixed. Refer to the following figure for the software-trigger mode waveform.
Similar to timer-trigger mode, between every two triggers, ADC enters the sleep state, and the trigger needs to be re-power on. As a result, the trigger interval should not be too short. It is recommended that the trigger interval should not be less than 1ms.
Note
Every time trigger source is generated, only one channel in the channel list will be sampled.
Summary
The following table shows the differences and applications of different operation modes.
Operation mode |
Configuration |
Difference |
Applications |
|---|---|---|---|
Auto mode |
REG_ADC_CONF[3:1] = 1 |
|
The case that needs real-time detection and more consumption. |
Timer-trigger mode |
REG_ADC_CONF[3:1] = 2 |
|
The case that needs periodic monitoring and less consumption. |
Software-trigger mode |
REG_ADC_CONF[3:1] = 0 REG_ADC_SW_TRIG[0] = 1 |
Need software but be more flexible |
The case that flexibly triggers ADC according to the current environment. |
Ameba supports three different operation modes: auto mode, timer-trigger mode, and software-trigger mode.
Although various modes are available to meet specific requirements, only one operation mode can be active at a time. All modes execute conversions based on the channel switch list. The primary distinction between these operation modes lies in the trigger source, which drives the ADC module to perform conversions.
Auto Mode
In auto mode, ADC continuously executes conversions without any trigger sources after auto channel switch register is set. Auto mode would not stop conversions until auto channel switch register is clear (register REG_ADC_AUTO_CSW_CTRL [0]) or the auto channel switch is disabled (register REG_ADC_CONF[3:1]).
In auto mode, ADC samples automatically by hardware without assistance of core or other modules, it can be applied to the situation where core resources are limited and real-time detection is required. Refer to Auto_Mode_Waveform for the auto mode waveform.
The ADC will scan the channels in the list in order. There is no interval between the adjacent channels, and the scanning speed only depends on the sampling rate of the ADC. At the end of the sampling period, the ADC immediately outputs the data to register and FIFO. So there is no need to set the CH switching time and settling time.
Because the sampled data is continuously filled into the register and FIFO when the REG_ADC_AUTO_CSW_CTRL [0] is set, if the data cannot be taken out, the data will be lost and the overflowed data will not be filled into the FIFO. For intermittent data getting from FIFO, FIFO clearing is recommended before getting.
However, there is a situation that needs to be paid attention to: if the internal resistance of the signal source sampled by ADC is very large, the input signal is easy to receive interference.
The solution is as follows:
Reduce the impedance
As shown in the following figure, operational amplifier (OA) provides extremely low output impedance.
Arrange Grounding Isolation Channel in channel list
As shown in the following figure, using a GND channel (internal GND channel or external channel which is connected to GND), configure the channel list of ADC to: CH0, CH_GND, CH1, CH_GND, CH2 … CH5, CH_GND. This avoids crosstalk, and the resulting inter-channel delay depends on the sampling rate of the ADC and the configuration of the channel list.
Note
If CH14(internal GND channel) is filled into the list as a channel, the output of CH14 (which remains 0) will not be stored in FIFO, so users can easily obtain sample data of other channels from FIFO.
Timer-trigger Mode
In timer-trigger mode, ADC can cooperate with timer modules to do conversions. System software sets timer trigger control register to enable timer module and set an appropriate timer event period. After that, ADC do one conversions when one timer event occurs based on system design.
Same as auto mode, the time- trigger mode can work independently without system software, which means it can reduce the core resources partly. What’s more, ADC can automatically go to shut down mode between two timer trigger events that can largely reduce the ADC power consumption itself. Refer to the following figure for the timer-trigger mode waveform.
After each trigger, ADC will power on and perform the sampling conversion, and immediately store the results in the register and FIFO, after which ADC will power down. Until the next trigger signal arrives, ADC will re-power on and perform the entire list channel sampling conversion.
Therefore, the interval time between adjacent trigger is limited by the power-on time of ADC, and the recommended interval is not less than 1ms. Sampling during the power-on of ADC is not complete, which may result in data errors. After power-on, ADC starts sampling immediately, and the sampling period is determined by the sampling rate.
Same as auto mode, at the end of the sampling period, the ADC immediately outputs the data to register and FIFO.
Note
The current IC supports up to 4 timer sources (timer 0~3).
Every time trigger source is generated, all the channels in the channel list will be sampled.
Software-trigger Mode
The software-trigger mode is similar with timer-trigger mode, and the difference between them is the trigger source. For general usage, system software tends to handle ADC conversion timing. Every time software trigger register (REG_ADC_SW_TRIG[0]) is set, ADC module performs channel sampling conversion. System software checks ready/busy register (REG_ADC_BUSY_STS[0]) before reading conversion data register (REG_ADC_DATA_GLOBAL[15:0]).
Compared with timer-trigger mode, this mode is more flexible. Software can manually trigger ADC sampling according to the actual situation, and the trigger time is not fixed. Refer to the following figure for the software-trigger mode waveform.
Similar to timer-trigger mode, between every two triggers, ADC enters the sleep state, and the trigger needs to be re-power on. As a result, the trigger interval should not be too short. It is recommended that the trigger interval should not be less than 1ms.
Note
Every time trigger source is generated, all the channels in the channel list will be sampled.
Summary
The following table shows the differences and applications of different operation modes.
Operation mode |
Configuration |
Difference |
Applications |
|---|---|---|---|
Auto mode |
REG_ADC_CONF[3:1] = 1 |
|
The case that needs real-time detection and more consumption. |
Timer-trigger mode |
REG_ADC_CONF[3:1] = 2 |
|
The case that needs periodic monitoring and less consumption. |
Software-trigger mode |
REG_ADC_CONF[3:1] = 0 REG_ADC_SW_TRIG[0] = 1 |
Need software but be more flexible |
The case that flexibly triggers ADC according to the current environment. |
Low Power Mode
The following figure shows the ADC clock generation tree. Users can configure ADC sample frequency by setting register REG_ADC_CLK_DIV[2:0].
After the system enters the low-power state, the ADC can execute sampling operations via auto mode, and the system can be woken up by an ADC interrupt.
Under auto mode, the ADC hardware automatically and continuously samples the external analog voltage. Users can preset high/low thresholds as well as comparison criteria. The CPU remains completely in sleep mode throughout the entire process, and the system is woken up only when the sampled voltage meets the predefined comparison criteria.
In the low-power state, only OSC clock can be selected as the ADC clock, allowing the system to be woken up.
The following figure shows the ADC clock generation tree. Users can configure ADC sample frequency by setting register REG_ADC_CLK_DIV[2:0].
After the system enters the low-power state, the ADC can execute sampling operations via auto mode or timer-trigger mode, and the system can be woken up by an ADC interrupt.
Auto mode: The ADC hardware automatically and continuously samples the external analog voltage. Users can preset high/low thresholds as well as comparison criteria. The CPU remains completely in sleep mode throughout the entire process, and the system is woken up only when the sampled voltage meets the predefined comparison criteria.
Timer-trigger mode: In the low-power state, the timer periodically sends a signal to trigger the ADC to perform a sampling operation, and the system can be woken up upon the completion of the sampling.
In the low-power state, only OSC clock can be selected as the ADC clock, allowing the system to be woken up.
The following figure shows the ADC clock generation tree. Users can configure ADC sample frequency by setting register REG_ADC_CLK_DIV[2:0].
After the system enters the low-power state, the ADC can execute sampling operations via auto mode or timer-trigger mode, and the system can be woken up by an ADC interrupt.
Auto mode: The ADC hardware automatically and continuously samples the external analog voltage. Users can preset high/low thresholds as well as comparison criteria. The CPU remains completely in sleep mode throughout the entire process, and the system is woken up only when the sampled voltage meets the predefined comparison criteria.
Timer-trigger mode: In the low-power state, the timer periodically sends a signal to trigger the ADC to perform a sampling operation, and the system can be woken up upon the completion of the sampling.
In the low-power state, only OSC clock can be selected as the ADC clock, allowing the system to be woken up.
The following figure shows the ADC clock generation tree. Users can configure ADC sample frequency by setting register REG_ADC_CLK_DIV[2:0].
After the system enters the low-power state, the ADC can execute sampling operations via auto mode or timer-trigger mode, and the system can be woken up by an ADC interrupt.
Auto mode: The ADC hardware automatically and continuously samples the external analog voltage. Users can preset high/low thresholds as well as comparison criteria. The CPU remains completely in sleep mode throughout the entire process, and the system is woken up only when the sampled voltage meets the predefined comparison criteria.
Timer-trigger mode: In the low-power state, the timer periodically sends a signal to trigger the ADC to perform a sampling operation, and the system can be woken up upon the completion of the sampling.
In the low-power state, only OSC clock can be selected as the ADC clock, allowing the system to be woken up.
The following figure shows the ADC clock generation tree. Users can configure ADC sample frequency by setting register REG_ADC_CLK_DIV[2:0].
After the system enters the low-power state, the ADC can execute sampling operations via auto mode or timer-trigger mode, and the system can be woken up by an ADC interrupt.
Auto mode: The ADC hardware automatically and continuously samples the external analog voltage. Users can preset high/low thresholds as well as comparison criteria. The CPU remains completely in sleep mode throughout the entire process, and the system is woken up only when the sampled voltage meets the predefined comparison criteria.
Timer-trigger mode: In the low-power state, the timer periodically sends a signal to trigger the ADC to perform a sampling operation, and the system can be woken up upon the completion of the sampling.
In the low-power state, only OSC clock can be selected as the ADC clock, allowing the system to be woken up.
The following figure shows the ADC clock generation tree. Users can configure ADC sample frequency by setting register REG_ADC_CLK_DIV[2:0].
After the system enters the low-power state, the ADC can execute sampling operations via auto mode or timer-trigger mode, and the system can be woken up by an ADC interrupt.
Auto mode: The ADC hardware automatically and continuously samples the external analog voltage. Users can preset high/low thresholds as well as comparison criteria. The CPU remains completely in sleep mode throughout the entire process, and the system is woken up only when the sampled voltage meets the predefined comparison criteria.
Timer-trigger mode: In the low-power state, the timer periodically sends a signal to trigger the ADC to perform a sampling operation, and the system can be woken up upon the completion of the sampling.
In the low-power state, only OSC clock can be selected as the ADC clock, allowing the system to be woken up.
Note
To use OSC as the ADC clock, set keep_osc4m_on in ps_config to TRUE in ameba_sleepcfg.c.
The following figure shows the ADC clock generation tree. Users can configure both the sampling and conversion time of each channel by setting register ADC_CLK_HCNTx and register ADC_CLK_LCNT0_DIV. The ADC supports both OSC and XTAL clock sources; the XTAL clock offers higher performance, while the OSC clock consumes less power.
After the system enters the low-power state, the ADC can execute sampling operations via auto mode or timer-trigger mode, and the system can be woken up by an ADC interrupt.
Auto mode: The ADC hardware automatically and continuously samples the external analog voltage. Users can preset high/low thresholds as well as comparison criteria. The CPU remains completely in sleep mode throughout the entire process, and the system is woken up only when the sampled voltage meets the predefined comparison criteria.
Timer-trigger mode: In the low-power state, the timer periodically sends a signal to trigger the ADC to perform a sampling operation, and the system can be woken up upon the completion of the sampling.
In the low-power state, only OSC clock can be selected as the ADC clock, allowing the system to be woken up.
Independent Comparison Event of Each Channel
The voltage monitoring function can be realized by using ADC, and each CH of ADC can be configured with two independent comparison thresholds and different comparison criterion. When the sample value of ADC reaches the configured condition, an interrupt can be detected in REG_ADC_INTR_STS.
The threshold of each channel can be configured in REG_ADC_COMP_TH_CHx, which contains both high threshold and low threshold. The comparison criterion of each channel can be configured in REG_ADC_COMP_CTRL. ADC comparison supports four different comparison criterion:
Vin < bit_adc_comp_th_l_chx
Vin > bit_adc_comp_th_h_chx
Vin >= bit_adc_comp_th_l_chx and Vin <= bit_adc_comp_th_h_chx
Vin < bit_adc_comp_th_l_chx or Vin > bit_adc_comp_th_h_chx.
For example, when configured as Vin < bit_adc_comp_th_l_chx or Vin > bit_adc_comp_th_h_chx, if the ADC conversion data exceeds the higher and lower threshold, an interrupt event will occur.
Two different interrupt generation modes (level detection and edge detection) is used to inform CPU of comparison match events. The level detection mode continuously reports the interrupt, while the edge detection mode reports it only once when the interrupt is generated.
Two different interrupt generation modes (level detection and edge detection) is used to inform CPU of comparison match events. The level detection mode continuously reports the interrupt, while the edge detection mode reports it only once when the interrupt is generated.
Two different interrupt generation modes (level detection and edge detection) is used to inform CPU of comparison match events. The level detection mode continuously reports the interrupt, while the edge detection mode reports it only once when the interrupt is generated.
Two different interrupt generation modes (level detection and edge detection) is used to inform CPU of comparison match events. The level detection mode continuously reports the interrupt, while the edge detection mode reports it only once when the interrupt is generated.
Two different interrupt generation modes (level detection and edge detection) is used to inform CPU of comparison match events. The level detection mode continuously reports the interrupt, while the edge detection mode reports it only once when the interrupt is generated.
Level detection interrupt generation mode is used to inform CPU of comparison match events and it continuously reports the interrupt
Two different interrupt generation modes (level detection and edge detection) is used to inform CPU of comparison match events. The level detection mode continuously reports the interrupt, while the edge detection mode reports it only once when the interrupt is generated.
Acquisition of Sampling Results
FIFO
Users can easily acquire ADC sample results from the ADC FIFO by reading the REG_ADC_DATA_GLOBAL register. The ADC stores all sampled results within this FIFO. The ADC FIFO has 64 entries, and each 20-bit FIFO data entry consists of a 4-bit channel number and 16-bit conversion data, as shown in the following figure.
Because the FIFO acts as a buffer between the data acquisition and data processing systems operating at different speeds, timely data retrieval is crucial to prevent data loss.
During normal operation, the ADC continuously writes data to the FIFO, while the system reads from it. If the system reads data slower than the ADC writes it, a FIFO overflow will occur. In the event of an overflow, any newly sampled data is discarded and will not be written to the FIFO, as shown in the figure above.
Users can easily acquire ADC sample results from the ADC FIFO by reading the REG_ADC_DATA_GLOBAL register. The ADC stores all sampled results within this FIFO. The ADC FIFO has 64 entries, and each 16-bit FIFO data entry consists of a 4-bit channel number and 12-bit conversion data, as shown in the following figure.
Because the FIFO acts as a buffer between the data acquisition and data processing systems operating at different speeds, timely data retrieval is crucial to prevent data loss.
During normal operation, the ADC continuously writes data to the FIFO, while the system reads from it. If the system reads data slower than the ADC writes it, a FIFO overflow will occur. In the event of an overflow, any newly sampled data is discarded and will not be written to the FIFO, as shown in the figure above.
Users can easily acquire ADC sample results from the ADC FIFO by reading the REG_ADC_DATA_GLOBAL register. The ADC stores all sampled results within this FIFO. The ADC FIFO has 64 entries, and each 16-bit FIFO data entry consists of a 4-bit channel number and 12-bit conversion data, as shown in the following figure.
Because the FIFO acts as a buffer between the data acquisition and data processing systems operating at different speeds, timely data retrieval is crucial to prevent data loss.
During normal operation, the ADC continuously writes data to the FIFO, while the system reads from it. If the system reads data slower than the ADC writes it, a FIFO overflow will occur. In the event of an overflow, any newly sampled data is discarded and will not be written to the FIFO, as shown in the figure above.
Users can easily acquire ADC sample results from the ADC FIFO by reading the REG_ADC_DATA_GLOBAL register. The ADC stores all sampled results within this FIFO. The ADC FIFO has 64 entries, and each 16-bit FIFO data entry consists of a 4-bit channel number and 12-bit conversion data, as shown in the following figure.
Because the FIFO acts as a buffer between the data acquisition and data processing systems operating at different speeds, timely data retrieval is crucial to prevent data loss.
During normal operation, the ADC continuously writes data to the FIFO, while the system reads from it. If the system reads data slower than the ADC writes it, a FIFO overflow will occur. In the event of an overflow, any newly sampled data is discarded and will not be written to the FIFO, as shown in the figure above.
Users can easily acquire ADC sample results from the ADC FIFO by reading the REG_ADC_DATA_GLOBAL register. The ADC stores all sampled results within this FIFO. The ADC FIFO has 64 entries, and each 16-bit FIFO data entry consists of a 4-bit channel number and 12-bit conversion data, as shown in the following figure.
Because the FIFO acts as a buffer between the data acquisition and data processing systems operating at different speeds, timely data retrieval is crucial to prevent data loss.
During normal operation, the ADC continuously writes data to the FIFO, while the system reads from it. If the system reads data slower than the ADC writes it, a FIFO overflow will occur. In the event of an overflow, any newly sampled data is discarded and will not be written to the FIFO, as shown in the figure above.
Users can easily acquire ADC sample results from the ADC FIFO by reading the REG_ADC_DATA_GLOBAL register. The ADC stores all sampled results within this FIFO. The ADC FIFO has 64 entries, and each 16-bit FIFO data entry consists of a 4-bit channel number and 12-bit conversion data, as shown in the following figure.
Because the FIFO acts as a buffer between the data acquisition and data processing systems operating at different speeds, timely data retrieval is crucial to prevent data loss.
During normal operation, the ADC continuously writes data to the FIFO, while the system reads from it. If the system reads data slower than the ADC writes it, a FIFO overflow will occur. In the event of an overflow, any newly sampled data is discarded and will not be written to the FIFO, as shown in the figure above.
Users can easily acquire ADC sample results from the ADC FIFO by reading the REG_ADC_DATA_GLOBAL register. The ADC stores all sampled results within this FIFO. The ADC FIFO has 64 entries, and each 20-bit FIFO data entry consists of a 4-bit channel number and 16-bit conversion data, as shown in the following figure.
Because the FIFO acts as a buffer between the data acquisition and data processing systems operating at different speeds, timely data retrieval is crucial to prevent data loss.
During normal operation, the ADC continuously writes data to the FIFO, while the system reads from it. If the system reads data slower than the ADC writes it, a FIFO overflow will occur. In the event of an overflow, any newly sampled data is discarded and will not be written to the FIFO, as shown in the figure above.
In addition to retrieving data promptly to avoid overflows, it is highly recommended to clear the ADC FIFO by setting REG_ADC_CLR_FIFO[0] before initiating any new data sampling process.
If the FIFO overflow interrupt (ADC_BIT_IT_FIFO_OVER_EN) is enabled, an interrupt signal is sent to the CPU NVIC upon a FIFO overflow. Similarly, if the FIFO empty interrupt (ADC_BIT_IT_FIFO_EMPTY_EN) is enabled, an interrupt is triggered when the FIFO becomes empty.
Additionally, users can set a custom FIFO full threshold by configuring REG_ADC_FULL_LVL[5:0]. When the FIFO full interrupt (ADC_BIT_IT_FIFO_FULL_EN) is enabled, an interrupt is sent to the CPU NVIC once the number of FIFO entries reaches this configured threshold, as shown in the following figure.
REG_ADC_FLR[5:0] indicates the current number of entries in the ADC FIFO.
Individual Channel Register
Each channel has its own data register to store its latest conversion result. These registers are named REG_ADC_DATA_CHx, where x represents the specific channel number (e.g., CH0).
REG_ADC_DATA_CHx[15:0] contains the latest conversion data for CHx.
REG_ADC_DATA_CHx[19:16] indicates the channel number associated with the latest conversion data.
REG_ADC_DATA_CHx[20] is a flag indicating a data overwrite event.
REG_ADC_DATA_CHx[21] is a flag indicating that a conversion is complete.
REG_ADC_DATA_CHx[11:0] contains the latest conversion data for CHx.
REG_ADC_DATA_CHx[15:12] indicates the channel number associated with the latest conversion data.
REG_ADC_DATA_CHx[16] is a flag indicating a data overwrite event.
REG_ADC_DATA_CHx[17] is a flag indicating that a conversion is complete.
REG_ADC_DATA_CHx[11:0] contains the latest conversion data for CHx.
REG_ADC_DATA_CHx[15:12] indicates the channel number associated with the latest conversion data.
REG_ADC_DATA_CHx[16] is a flag indicating a data overwrite event.
REG_ADC_DATA_CHx[17] is a flag indicating that a conversion is complete.
REG_ADC_DATA_CHx[11:0] contains the latest conversion data for CHx.
REG_ADC_DATA_CHx[15:12] indicates the channel number associated with the latest conversion data.
REG_ADC_DATA_CHx[16] is a flag indicating a data overwrite event.
REG_ADC_DATA_CHx[17] is a flag indicating that a conversion is complete.
REG_ADC_DATA_CHx[11:0] contains the latest conversion data for CHx.
REG_ADC_DATA_CHx[15:12] indicates the channel number associated with the latest conversion data.
REG_ADC_DATA_CHx[16] is a flag indicating a data overwrite event.
REG_ADC_DATA_CHx[17] is a flag indicating that a conversion is complete.
REG_ADC_DATA_CHx[11:0] contains the latest conversion data for CHx.
REG_ADC_DATA_CHx[15:12] indicates the channel number associated with the latest conversion data.
REG_ADC_DATA_CHx[16] is a flag indicating a data overwrite event.
REG_ADC_DATA_CHx[17] is a flag indicating that a conversion is complete.
REG_ADC_DATA_CHx[15:0] contains the latest conversion data for CHx.
REG_ADC_DATA_CHx[19:16] indicates the channel number associated with the latest conversion data.
REG_ADC_DATA_CHx[20] is a flag indicating a data overwrite event.
REG_ADC_DATA_CHx[21] is a flag indicating that a conversion is complete.
PAD Configuration
The ADC analog front-end(AFE) is an analog device and the analog signal enters the chip through the chip pins. Therefore there should be no significant digital signal interference and pull-up/pull-down circuits on this path.
If users want to use a GPIO pin as an ADC input pin, besides configuring the pin function as ADC, the digital circuit function of the selected pin should be disabled and the pin should be set as no pull state (including sleep state) as well.
Calibration
Each IC’s ADC is factory calibrated. The users can directly obtain the exact voltage conversion results that have been calibrated by calling ADC_GetVoltage() with conversion data as parameter.
Registers
Base Address: 0x41011000
Name |
Address offset |
Access |
Description |
|---|---|---|---|
000h |
R/W |
The basic configuration of ADC includes enable and operation mode. |
|
004h |
R/W |
This register is used to configure analog ADC input type. |
|
008h |
R/W |
||
00Ch |
R/W |
||
010h |
R/W |
||
014h |
R/W |
||
018h |
R/W |
||
01Ch |
R/W |
||
020h |
R/W |
||
024h |
R/W |
||
028h |
R/W |
||
02Ch |
R/W |
||
030h |
R/W |
||
034h |
R/W |
This is channel comparison criterion control register, which can be used to control every channel’s comparison criterion. There are 3 kinds of criterions. |
|
038h |
R |
This is the register about comparison status of every channel. |
|
03Ch |
R/W |
Software channel list 0, used to define the analog channels to own channel list. |
|
040h |
R/W |
Software channel list 1, refer to REG_ADC_CHSW_LIST_0. |
|
048h |
R/W |
This is the register about automatic switch channel function. |
|
04Ch |
R/W |
Software controls to trigger the channel switch. |
|
050h |
R |
This register records the last channel. |
|
054h |
R |
This register reflects the ADC FSM and FIFO status. |
|
058h |
R/W |
This register is used to enable or disable the different kinds of interrupts. |
|
05Ch |
R |
This register is used to record the different kinds of interrupt raw status (bypass the enable register’s control). |
|
060h |
R/W |
This register is used to record the different kinds of interrupt status. |
|
064h |
R/W |
This register is about the specific channel to trigger interrupts. |
|
068h |
R/W |
||
06Ch |
R/W |
This register is used to select the specific external timer source. |
|
070h |
R |
This register is used to store the channel data, ready and overwritten information. |
|
074h |
R |
This register is used to store the channel data, ready and overwritten information. |
|
078h |
R |
This register is used to store the channel data, ready and overwritten information. |
|
07Ch |
R |
This register is used to store the channel data, ready and overwritten information. |
|
080h |
R |
This register is used to store the channel data, ready and overwritten information. |
|
084h |
R |
This register is used to store the channel data, ready and overwritten information. |
|
088h |
R |
This register is used to store the channel data, ready and overwritten information. |
|
08Ch |
R |
This register is used to store the channel data, ready and overwritten information. |
|
090h |
R |
This register is used to store the channel data, ready and overwritten information. |
|
094h |
R |
This register is used to store the channel data, ready and overwritten information. |
|
098h |
R |
This register is used to store the channel data, ready and overwritten information. |
|
09Ch |
R |
This register is used to store global data, ready, channel and overwritten information. |
|
0A0h |
R |
This register is used to store FIFO entry number. |
|
0A4h |
R/W |
This register is used to clear FIFO. |
|
0A8h |
R/W |
This register is used to control clock dividend and channel unmask. |
|
0ACh |
R/W |
This register is used to configure ADC over sample. |
|
0B0h |
R/W |
This register is used to control the ADC power and debug configuration. |
|
0B4h |
R/W |
This register is used to set the software test mode. |
|
0B8h |
R/W |
REG_ADC_CONF
Name: ADC Configuration Register
Size: 32
Address offset: 000h
Read/write access: R/W
The basic configuration of ADC includes enable and operation mode.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:10 |
RSVD |
R |
- |
Reserved |
9 |
BIT_ADC_ENABLE |
R/W |
0h |
This bit is for ADC enable control |
8 |
RSVD |
R |
- |
Reserved |
7:4 |
BIT_ADC_CVLIST_LEN |
R/W |
0h |
This field defines the number of items in the ADC conversion channel list. |
3:1 |
BIT_ADC_OP_MOD |
R/W |
0h |
These bits selects ADC operation mode.
|
0 |
RSVD |
R |
- |
Reserved |
REG_ADC_IN_TYPE
Name: ADC Input Type Register
Size: 32
Address offset: 004h
Read/write access: R/W
This register is used to configure analog ADC input type.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:11 |
RSVD |
R |
- |
Reserved |
10 |
BIT_ADC_IN_TYPE_CH10 |
R |
0 |
This bit reflects which kind of input type channel 10 is. Since channel 10 is a fixed internal channel. |
9 |
BIT_ADC_IN_TYPE_CH9 |
R |
0 |
This bit reflects which kind of input type channel 9 is. Since channel 9 is a fixed internal channel. |
8 |
BIT_ADC_IN_TYPE_CH8 |
R |
0 |
This bit reflects which kind of input type channel 8 is. Since channel 8 is a fixed internal channel. |
7 |
BIT_ADC_IN_TYPE_CH7 |
R |
0 |
This bit reflects which kind of input type channel 7 is. Since channel 7 is a fixed internal channel. |
6 |
BIT_ADC_IN_TYPE_CH6 |
R |
0 |
This bit reflects which kind of input type channel 6 is. Since channel 6 is a fixed single-end input channel. |
5 |
BIT_ADC_IN_TYPE_CH5 |
R/W |
0 |
This bit controls channel 5 input type. If it’s set to differential types (value of this bit is 1), channel 4 should also be set to differential type since they are hardware-fixed differential pair.
|
4 |
BIT_ADC_IN_TYPE_CH4 |
R/W |
0 |
This bit controls channel 4 input type. If it’s set to differential types (value of this bit is 1), channel 5 should also be set to differential type since they are hardware-fixed differential pair.
|
3 |
BIT_ADC_IN_TYPE_CH3 |
R/W |
0 |
This bit controls channel 3 input type. If it’s set to differential types (value of this bit is 1), channel 2 should also be set to differential type since they are hardware-fixed differential pair.
|
2 |
BIT_ADC_IN_TYPE_CH2 |
R/W |
0 |
This bit controls channel 2 input type. If it’s set to differential types (value of this bit is 1), channel 3 should also be set to differential type since they are hardware-fixed differential pair.
|
1 |
BIT_ADC_IN_TYPE_CH1 |
R/W |
0 |
This bit controls channel 1 input type. If it’s set to differential types (value of this bit is 1), channel 0 should also be set to differential type since they are hardware-fixed differential pair.
|
0 |
BIT_ADC_IN_TYPE_CH0 |
R/W |
0 |
This bit controls channel 0 input type. If it’s set to differential types (value of this bit is 1), channel 1 should also be set to differential type since they are hardware-fixed differential pair.
|
REG_ADC_COMP_TH_CHx
Name: ADC Channel x Comparison Threshold Register
Size: 32
Address offset: 008h + 04h * x (x=0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CHx |
R/W |
0h |
This field defines the higher threshold of channel x for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CHx |
R/W |
0h |
This field defines the lower threshold of channel x for ADC automatic comparison. |
REG_ADC_COMP_CTRL
Name: ADC Comparison Control Register
Size: 32
Address offset: 034h
Read/write access: R/W
This is channel comparison criterion control register, which can be used to control every channel’s
comparison criterion. There are 3 kinds of criterions.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21:20 |
BIT_ADC_COMP_CTRL_CH10 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
19:18 |
BIT_ADC_COMP_CTRL_CH9 |
R/W |
0h |
The function is the same as BIT_ADC_COMP_CTRL_CH10. |
17:16 |
BIT_ADC_COMP_CTRL_CH8 |
R/W |
0h |
The function is the same as BIT_ADC_COMP_CTRL_CH10. |
15:14 |
BIT_ADC_COMP_CTRL_CH7 |
R/W |
0h |
The function is the same as BIT_ADC_COMP_CTRL_CH10. |
13:12 |
BIT_ADC_COMP_CTRL_CH6 |
R/W |
0h |
The function is the same as BIT_ADC_COMP_CTRL_CH10. |
11:10 |
BIT_ADC_COMP_CTRL_CH5 |
R/W |
0h |
The function is the same as BIT_ADC_COMP_CTRL_CH10. |
9:8 |
BIT_ADC_COMP_CTRL_CH4 |
R/W |
0h |
The function is the same as BIT_ADC_COMP_CTRL_CH10. |
7:6 |
BIT_ADC_COMP_CTRL_CH3 |
R/W |
0h |
The function is the same as BIT_ADC_COMP_CTRL_CH10. |
5:4 |
BIT_ADC_COMP_CTRL_CH2 |
R/W |
0h |
The function is the same as BIT_ADC_COMP_CTRL_CH10. |
3:2 |
BIT_ADC_COMP_CTRL_CH1 |
R/W |
0h |
The function is the same as BIT_ADC_COMP_CTRL_CH10. |
1:0 |
BIT_ADC_COMP_CTRL_CH0 |
R/W |
0h |
The function is the same as BIT_ADC_COMP_CTRL_CH10. |
REG_ADC_COMP_STS
Name: ADC Comparison Status Register
Size: 32
Address offset: 038h
Read/write access: R
This is the register about comparison status of every channel.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21:20 |
BIT_ADC_COMP_STS_CH10 |
R |
0h |
This field reflects the comparison result of channel 10 immediately |
19:18 |
BIT_ADC_COMP_STS_CH9 |
R |
0h |
This field reflects the comparison result of channel 9 immediately |
17:16 |
BIT_ADC_COMP_STS_CH8 |
R |
0h |
This field reflects the comparison result of channel 8 immediately |
15:14 |
BIT_ADC_COMP_STS_CH7 |
R |
0h |
This field reflects the comparison result of channel 7 immediately |
13:12 |
BIT_ADC_COMP_STS_CH6 |
R |
0h |
This field reflects the comparison result of channel 6 immediately |
11:10 |
BIT_ADC_COMP_STS_CH5 |
R |
0h |
This field reflects the comparison result of channel 5 immediately |
9:8 |
BIT_ADC_COMP_STS_CH4 |
R |
0h |
This field reflects the comparison result of channel 4 immediately |
7:6 |
BIT_ADC_COMP_STS_CH3 |
R |
0h |
This field reflects the comparison result of channel 3 immediately |
5:4 |
BIT_ADC_COMP_STS_CH2 |
R |
0h |
This field reflects the comparison result of channel 2 immediately |
3:2 |
BIT_ADC_COMP_STS_CH1 |
R |
0h |
This field reflects the comparison result of channel 1 immediately |
1:0 |
BIT_ADC_COMP_STS_CH0 |
R |
0h |
This field reflects the comparison result of channel 0 immediately |
REG_ADC_CHSW_LIST_0
Name: ADC Channel Switch List 0 Register
Size: 32
Address offset: 03Ch
Read/write access: R/W
Software channel list 0, used to define the analog channels to own channel list.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:28 |
BIT_ADC_CHSW_7 |
R/W |
0h |
This field defines the number 7 channel to do a conversion when a conversion event takes place. |
27:24 |
BIT_ADC_CHSW_6 |
R/W |
0h |
This field defines the number 6 channel to do a conversion when a conversion event takes place. |
23:20 |
BIT_ADC_CHSW_5 |
R/W |
0h |
This field defines the number 5 channel to do a conversion when a conversion event takes place. |
19:16 |
BIT_ADC_CHSW_4 |
R/W |
0h |
This field defines the number 4 channel to do a conversion when a conversion event takes place. |
15:12 |
BIT_ADC_CHSW_3 |
R/W |
0h |
This field defines the number 3 channel to do a conversion when a conversion event takes place. |
11:8 |
BIT_ADC_CHSW_2 |
R/W |
0h |
This field defines the number 2 channel to do a conversion when a conversion event takes place. |
7:4 |
BIT_ADC_CHSW_1 |
R/W |
0h |
This field defines the number 1 channel to do a conversion when a conversion event takes place. |
3:0 |
BIT_ADC_CHSW_0 |
R/W |
0h |
This field defines the number 0 channel to do a conversion when a conversion event takes place. |
REG_ADC_CHSW_LIST_1
Name: ADC Channel Switch List 1 Register
Size: 32
Address offset: 040h
Read/write access: R/W
Software channel list 1, refer to REG_ADC_CHSW_LIST_0.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:28 |
BIT_ADC_CHSW_15 |
R/W |
0h |
This field defines the number 15 channel to do a conversion when a conversion event takes place. |
27:24 |
BIT_ADC_CHSW_14 |
R/W |
0h |
This field defines the number 14 channel to do a conversion when a conversion event takes place. |
23:20 |
BIT_ADC_CHSW_13 |
R/W |
0h |
This field defines the number 13 channel to do a conversion when a conversion event takes place. |
19:16 |
BIT_ADC_CHSW_12 |
R/W |
0h |
This field defines the number 12 channel to do a conversion when a conversion event takes place. |
15:12 |
BIT_ADC_CHSW_11 |
R/W |
0h |
This field defines the number 11 channel to do a conversion when a conversion event takes place. |
11:8 |
BIT_ADC_CHSW_10 |
R/W |
0h |
This field defines the number 10 channel to do a conversion when a conversion event takes place. |
7:4 |
BIT_ADC_CHSW_9 |
R/W |
0h |
This field defines the number 9 channel to do a conversion when a conversion event takes place. |
3:0 |
BIT_ADC_CHSW_8 |
R/W |
0h |
This field defines the number 8 channel to do a conversion when a conversion event takes place. |
REG_ADC_AUTO_CSW_CTRL
Name: ADC Automatic Channel Switch Control Register
Size: 32
Address offset: 048h
Read/write access: R/W
This is the register about automatic switch channel function.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_AUTOSW_EN |
R/W |
0h |
This bit controls the automatic channel switch enabled or disabled.
|
REG_ADC_SW_TRIG
Name: ADC Software Trigger Register
Size: 32
Address offset: 04Ch
Read/write access: R/W
Software controls to trigger the channel switch.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_SW_TRIG |
R/W |
0h |
This bit controls the ADC module to do a conversion. Every time this bit is set to 1, ADC module would switch to a new channel and do one conversion. Therefore, this bit could be used as a start-convert event which is controlled by software. Every time a conversion is done, software MUST clear this bit manually. The interval between clearing and restart this bit must exceed one sample clock period.
|
REG_ADC_LAST_CH
Name: ADC Last Channel Register
Size: 32
Address offset: 050h
Read/write access: R
This register records the last channel.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
- |
Reserved |
3:0 |
BIT_ADC_LAST_CH |
R |
0h |
This field reflects the last used channel. |
REG_ADC_BUSY_STS
Name: ADC Busy Status Register
Size: 32
Address offset: 054h
Read/write access: R
This register reflects the ADC FSM and FIFO status.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
- |
Reserved |
2 |
BIT_ADC_FIFO_EMPTY |
R |
1 |
|
1 |
BIT_ADC_FIFO_FULL_REAL |
R |
0 |
|
0 |
BIT_ADC_BUSY_STS |
R |
0 |
This bit reflects the ADC is busy or not. If the ADC is processing a conversion of a channel, this bit remains 1 which indicates it’s busy. Once a conversion is done, this bit becomes 0 which indicates it’s ready to do another conversion.
|
REG_ADC_INTR_CTRL
Name: ADC Interrupt Control Register
Size: 32
Address offset: 058h
Read/write access: R/W
This register is used to enable or disable the different kinds of interrupts.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31 |
BIT_ADC_IT_COMP_DET_MOD |
R/W |
0h |
This bit controls the interrupt bit_adc_it_comp_chx operation. Comparison criterion matching is rising edge.
|
30:19 |
RSVD |
R |
- |
Reserved |
18 |
BIT_ADC_IT_COMP_CH10_EN |
R/W |
0h |
The function is the same as BIT_ADC_IT_COMP_CH0_EN |
17 |
BIT_ADC_IT_COMP_CH9_EN |
R/W |
0h |
The function is the same as BIT_ADC_IT_COMP_CH0_EN |
16 |
BIT_ADC_IT_COMP_CH8_EN |
R/W |
0h |
The function is the same as BIT_ADC_IT_COMP_CH0_EN |
15 |
BIT_ADC_IT_COMP_CH7_EN |
R/W |
0h |
The function is the same as BIT_ADC_IT_COMP_CH0_EN |
14 |
BIT_ADC_IT_COMP_CH6_EN |
R/W |
0h |
The function is the same as BIT_ADC_IT_COMP_CH0_EN |
13 |
BIT_ADC_IT_COMP_CH5_EN |
R/W |
0h |
The function is the same as BIT_ADC_IT_COMP_CH0_EN |
12 |
BIT_ADC_IT_COMP_CH4_EN |
R/W |
0h |
The function is the same as BIT_ADC_IT_COMP_CH0_EN |
11 |
BIT_ADC_IT_COMP_CH3_EN |
R/W |
0h |
The function is the same as BIT_ADC_IT_COMP_CH0_EN |
10 |
BIT_ADC_IT_COMP_CH2_EN |
R/W |
0h |
The function is the same as BIT_ADC_IT_COMP_CH0_EN |
9 |
BIT_ADC_IT_COMP_CH1_EN |
R/W |
0h |
The function is the same as BIT_ADC_IT_COMP_CH0_EN |
8 |
BIT_ADC_IT_COMP_CH0_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 0 comparison criterion matches.
|
7 |
BIT_ADC_IT_ERR_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when an error state takes place.
|
6 |
BIT_ADC_IT_DAT_OVW_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a data overwritten situation takes place.
|
5 |
BIT_ADC_IT_FIFO_EMPTY_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO empty state takes place.
|
4 |
BIT_ADC_IT_FIFO_OVER_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO overflow state takes place.
|
3 |
BIT_ADC_IT_FIFO_FULL_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO full state takes place.
|
2 |
BIT_ADC_IT_CHCV_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a particular channel conversion is done. refer to reg_adc_it_chno_con.
|
1 |
BIT_ADC_IT_CV_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not every time a conversion is done. No matter ADC module is in what kind of operation mode. Every time a conversion is executed, ADC module would notify system if This bit is set.
|
0 |
BIT_ADC_IT_CVLIST_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a conversion of the last channel in the list is done. For example, in automatic mode conversions would be executed continuously. Every time the last channel conversion is done, which means all channel conversions in the list is done, ADC could notify system if This bit is set.
|
REG_ADC_INTR_RAW_STS
Name: ADC Interrupt Raw Status Register
Size: 32
Address offset: 05Ch
Read/write access: R
This register is used to record the different kinds of interrupt raw status (bypass the enable
register’s control).
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:19 |
RSVD |
R |
- |
Reserved |
18 |
BIT_ADC_IT_COMP_CH10_RAW_STS |
R |
0h |
|
17 |
BIT_ADC_IT_COMP_CH9_RAW_STS |
R |
0h |
Merged |
16 |
BIT_ADC_IT_COMP_CH8_RAW_STS |
R |
0h |
Merged |
15 |
BIT_ADC_IT_COMP_CH7_RAW_STS |
R |
0h |
Merged |
14 |
BIT_ADC_IT_COMP_CH6_RAW_STS |
R |
0h |
Merged |
13 |
BIT_ADC_IT_COMP_CH5_RAW_STS |
R |
0h |
Merged |
12 |
BIT_ADC_IT_COMP_CH4_RAW_STS |
R |
0h |
Merged |
11 |
BIT_ADC_IT_COMP_CH3_RAW_STS |
R |
0h |
Merged |
10 |
BIT_ADC_IT_COMP_CH2_RAW_STS |
R |
0h |
Merged |
9 |
BIT_ADC_IT_COMP_CH1_RAW_STS |
R |
0h |
Merged |
8 |
BIT_ADC_IT_COMP_CH0_RAW_STS |
R |
0h |
Merged |
7 |
BIT_ADC_IT_ERR_RAW_STS |
R |
0h |
Merged |
6 |
BIT_ADC_IT_DAT_OVW_RAW_STS |
R |
0h |
Merged |
5 |
BIT_ADC_IT_FIFO_EMPTY_RAW_STS |
R |
1h |
Merged |
4 |
BIT_ADC_IT_FIFO_OVER_RAW_STS |
R |
0h |
Merged |
3 |
BIT_ADC_IT_FIFO_FULL_RAW_STS |
R |
0h |
Merged |
2 |
BIT_ADC_IT_CHCV_END_RAW_STS |
R |
0h |
Merged |
1 |
BIT_ADC_IT_CV_END_RAW_STS |
R |
0h |
Merged |
0 |
BIT_ADC_IT_CVLIST_END_RAW_STS |
R |
0h |
Merged |
REG_ADC_INTR_STS
Name: ADC Interrupt Status Register
Size: 32
Address offset: 060h
Read/write access: R/W
This register is used to record the different kinds of interrupt status.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:19 |
RSVD |
R |
- |
Reserved |
18 |
BIT_ADC_IT_COMP_CH10_STS |
R/W |
0h |
|
17 |
BIT_ADC_IT_COMP_CH9_STS |
R/W |
0h |
Merged |
16 |
BIT_ADC_IT_COMP_CH8_STS |
R/W |
0h |
Merged |
15 |
BIT_ADC_IT_COMP_CH7_STS |
R/W |
0h |
Merged |
14 |
BIT_ADC_IT_COMP_CH6_STS |
R/W |
0h |
Merged |
13 |
BIT_ADC_IT_COMP_CH5_STS |
R/W |
0h |
Merged |
12 |
BIT_ADC_IT_COMP_CH4_STS |
R/W |
0h |
Merged |
11 |
BIT_ADC_IT_COMP_CH3_STS |
R/W |
0h |
Merged |
10 |
BIT_ADC_IT_COMP_CH2_STS |
R/W |
0h |
Merged |
9 |
BIT_ADC_IT_COMP_CH1_STS |
R/W |
0h |
Merged |
8 |
BIT_ADC_IT_COMP_CH0_STS |
R/W |
0h |
Merged |
7 |
BIT_ADC_IT_ERR_STS |
R/W |
0h |
Merged |
6 |
BIT_ADC_IT_DAT_OVW_STS |
R/W |
0h |
Merged |
5 |
BIT_ADC_IT_FIFO_EMPTY_STS |
R/W |
0h |
Merged |
4 |
BIT_ADC_IT_FIFO_OVER_STS |
R/W |
0h |
Merged |
3 |
BIT_ADC_IT_FIFO_FULL_STS |
R/W |
0h |
Merged |
2 |
BIT_ADC_IT_CHCV_END_STS |
R/W |
0h |
Merged |
1 |
BIT_ADC_IT_CV_END_STS |
R/W |
0h |
Merged |
0 |
BIT_ADC_IT_CVLIST_END_STS |
R/W |
0h |
Merged |
REG_ADC_IT_CHNO_CON
Name: ADC Interrupt Channel Number Configuration Register
Size: 32
Address offset: 064h
Read/write access: R/W
This register is about the specific channel to trigger interrupts.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
- |
Reserved |
3:0 |
BIT_ADC_IT_CHNO_CON |
R/W |
0h |
This field defines that ADC module should send interrupt signal to system when a conversion which of channel number is the same as this field. This register is only valid when bit_adc_it_chcv_end_en is set. Bit_adc_it_chno_con: channel number |
REG_ADC_FULL_LVL
Name: ADC FIFO Full Threshold Register
Size: 32
Address offset: 068h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:6 |
RSVD |
R |
- |
Reserved |
5:0 |
BIT_ADC_FULL_LVL |
R/W |
0h |
This field defines the FIFO full entry threshold level and it’s used for FIFO full interrupt. It should be set according to ADC FIFO depth. A value of 0 sets the threshold for 1 entry, and a value of 15 sets the threshold for 16 entries. |
REG_ADC_EXT_TRIG_TIMER_SEL
Name: ADC External Trigger Timer Select Register
Size: 32
Address offset: 06Ch
Read/write access: R/W
This register is used to select the specific external timer source.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
- |
Reserved |
2:0 |
BIT_ADC_EXT_TRIG_TIMER_SEL |
R/W |
0h |
These three bits defines which timer channel would be used to make ADC module do a conversion.
|
REG_ADC_DATA_CHx
Name: ADC Channel x Data Register
Size: 32
Address offset: 070h + 04h * x (x=0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
Read/write access: R
This register is used to store the channel data, ready and overwritten information.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CHx |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_chx. |
20 |
BIT_ADC_DAT_OVW_CHx |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global taking place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_chx.
|
19:16 |
BIT_ADC_NUM_CHx |
R |
0 |
This field contains the newest conversion data of channel x [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CHx |
R |
0 |
This field contains the newest conversion data of channel x [15:0]: newest data |
REG_ADC_DATA_GLOBAL
Name: ADC Global Data Register
Size: 32
Address offset: 09Ch
Read/write access: R
This register is used to store global data, ready, channel and overwritten information.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_GLOBAL |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_global |
20 |
BIT_ADC_DAT_OVW_GLOBAL |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global taking place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field.
|
19:16 |
BIT_ADC_CH_NUM_GLOBAL |
R |
0 |
This field contains the newest conversion data of channel in the list. [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_GLOBAL |
R |
0 |
This field contains the newest conversion data of channel in the list. [15:0]: newest data |
REG_ADC_FLR
Name: ADC FIFO Level Register
Size: 32
Address offset: 0A0h
Read/write access: R
This register is used to store FIFO entry number.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:6 |
RSVD |
R |
- |
Reserved |
5:0 |
BIT_ADC_FLR |
R |
0 |
This field records the current ADC FIFO entry number. |
REG_ADC_CLR_FIFO
Name: ADC Clear FIFO Register
Size: 32
Address offset: 0A4h
Read/write access: R/W
This register is used to clear FIFO.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_CLR_FIFO |
R/W |
0 |
This bit is used to clear FIFO contents and makes it to the default status. Every time this bit is set to 1. FIFO would be cleared to the default status. Software should set this bit to 0 after FIFO is cleared.
|
REG_ADC_CLK_DIV
Name: ADC Clock Divider Register
Size: 32
Address offset: 0A8h
Read/write access: R/W
This register is used to control clock dividend and channel unmask.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:15 |
BIT_ADC_DUMMY_CHN_SCNT |
R/W |
0h |
Dummy channel time counter. In auto mode, ADC shares the dummy channel for Cap-Touch. This register controls the time of dummy channel, the unit is 4MHz. |
14:8 |
RSVD |
R |
- |
Reserved |
7:4 |
BIT_SETTLE_CTC_TO_ADC |
R/W |
0h |
Settle count for sample data from Cap-Touch to ADC, the unit is ADC sample clock.
|
3 |
RSVD |
R |
- |
Reserved |
2:0 |
BIT_ADC_CLK_DIV |
R/W |
3h |
This field defines clock driver level of ADC module. The source clock is OSC4M. A value of 0 is for clock divided by 4. A value of 1 is for clock divided by 8. A value of 2 is for clock divided by 16. A value of 3 is for clock divided by 24. A value of 4 is for clock divided by 32. A value of 5 is for clock divided by 64. A value of 6 is for clock divided by 128. |
REG_ADC_OVERSAMPLE
Name: ADC Oversample Register
Size: 32
Address offset: 0ACh
Read/write access: R/W
This register is used to configure ADC over sample.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:9 |
RSVD |
R |
- |
Reserved |
8:6 |
BIT_ADC_OSF |
R/W |
0 |
Oversampling right shift
|
5:3 |
BIT_ADC_OSR |
R/W |
0 |
Oversample ratio
|
2 |
RSVD |
R |
- |
Reserved |
1 |
BIT_OV_MODE |
R/W |
0 |
Oversample mode
|
0 |
BIT_ADC_OS_EN |
R/W |
0 |
Oversample enable
|
REG_ADC_PWR_CTRL
Name: ADC Power Control Register
Size: 32
Address offset: 0B0h
Read/write access: R/W
This register is used to control the ADC power and debug configuration.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
- |
Reserved |
3 |
BIT_ADC_DBG_EN |
R/W |
0 |
Debug port enable |
2:1 |
BIT_ADC_DBG_SEL |
R/W |
0 |
Debug port select |
0 |
BIT_ADC_PWR_CTRL |
R/W |
0 |
This field is used to power control. |
REG_ADC_SW_TMODE
Name: ADC Software Test Mode
Size: 32
Address offset: 0B4h
Read/write access: R/W
This register is used to set the software test mode.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_SW_TMODE |
R/W |
0 |
This bit is used to change the high 4 bits in FIFO.
|
REG_ADC_DUMMY
Name: ADC Dummy Register
Size: 32
Address offset: 0B8h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DUMMY |
R/W |
ffffh |
Dummy register |
Base Address: 0x4101C000
Name |
Address offset |
Access |
Description |
|---|---|---|---|
000h |
R/W |
Basic configuration of ADC including enable and operation mode |
|
004h |
R/W |
Analog ADC input type configuration |
|
008h |
R/W |
Channel comparison threshold |
|
00Ch |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
010h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
014h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
018h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
01Ch |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
020h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
024h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
028h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
02Ch |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
030h |
R/W |
This register can be used to control every channel’s comparison criterion. There are 3 kinds of criterions. |
|
034h |
R |
The comparison status of every channel |
|
038h |
R/W |
Software channel list 0, to define the analog channels to own channel list |
|
03Ch |
R/W |
Software channel list 1, refer to REG_ADC_CHSW_LIST_0 |
|
040h |
R/W |
Reset the channel list to default status |
|
044h |
R/W |
Automatic switch channel function |
|
048h |
R/W |
Software controls to trigger the channel switch |
|
04Ch |
R |
This register records the last channel |
|
050h |
R |
This register reflects the ADC FSM and fifo status |
|
054h |
R/W |
This register to enable or disable the different kinds of interrupts |
|
058h |
R |
This register to record the different kinds of interrupt raw status (bypass the enable register’s control) |
|
05Ch |
R/W |
This register to record the different kinds of interrupt status |
|
060h |
R/W |
The specific channel to trigger interrupt |
|
064h |
R/W |
The FIFO full threshold |
|
068h |
R/W |
This register is used to select the specific external timer source |
|
06Ch |
R |
This register is used to store the channel data , ready and overwritten information |
|
070h |
R |
Refer to REG_ADC_DATA_CH0 |
|
074h |
R |
Refer to REG_ADC_DATA_CH0 |
|
078h |
R |
Refer to REG_ADC_DATA_CH0 |
|
07Ch |
R |
Refer to REG_ADC_DATA_CH0 |
|
080h |
R |
Refer to REG_ADC_DATA_CH0 |
|
084h |
R |
Refer to REG_ADC_DATA_CH0 |
|
088h |
R |
Refer to REG_ADC_DATA_CH0 |
|
08Ch |
R |
Refer to REG_ADC_DATA_CH0 |
|
090h |
R |
Refer to REG_ADC_DATA_CH0 |
|
094h |
R |
This register is used to store global data, ready, channel and overwritten information. |
|
098h |
R |
This register is used to store fifo entry number. |
|
09Ch |
R/W |
This register is used to clear FIFO. |
|
0A0h |
R/W |
This register is used to control clock dividend. |
|
0A4h |
R/W |
This register is used to configure ADC delay and channel unmask. |
|
0A8h |
R/W |
This register is used to control the ADC power and debug configuration. |
|
0ACh |
R/W |
This register is used to set the software test mode. |
|
0B0h |
R/W |
Dummy register |
REG_ADC_CONF
Name: ADC Configuration Register
Size: 32
Address offset: 000h
Read/write access: R/W
Basic configuration of ADC including enable and operation mode
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:10 |
RSVD |
R |
- |
Reserved |
9 |
BIT_ADC_ENABLE |
R/W |
0h |
This bit is for ADC enable control |
8 |
RSVD |
R |
- |
Reserved |
7:4 |
BIT_ADC_CVLIST_LEN |
R/W |
0h |
This field defines the number of items in the ADC conversion channel list. |
3:1 |
BIT_ADC_OP_MOD |
R/W |
0h |
These bits selects ADC operation mode.
|
0 |
BIT_ADC_REF_IN_SEL |
R/W |
0h |
This bit selects ADC reference voltage input.
|
REG_ADC_IN_TYPE
Name: ADC Input Type Register
Size: 32
Address offset: 004h
Read/write access: R/W
Analog ADC input type configuration
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:10 |
RSVD |
R |
- |
Reserved |
9 |
BIT_ADC_IN_TYPE_CH9 |
R |
0 |
This bit reflects which kind of input type channel 9 is. Since channel 9 is a fixed internal channel. |
8 |
BIT_ADC_IN_TYPE_CH8 |
R |
0 |
This bit reflects which kind of input type channel 8 is. Since channel 8 is a fixed internal channel. |
7 |
BIT_ADC_IN_TYPE_CH7 |
R |
0 |
This bit reflects which kind of input type channel 7 is. Since channel 7 is a fixed internal channel. |
6 |
BIT_ADC_IN_TYPE_CH6 |
R |
0 |
This bit reflects which kind of input type channel 6 is. Since channel 6 is a fixed internal channel. |
5 |
BIT_ADC_IN_TYPE_CH5 |
R/W |
0 |
This bit controls channel 5 input type. If it’s set to differential type(value of this bit is 1), channel 4 should also be set to differential type since they are hardware-fixed differential pair.
|
4 |
BIT_ADC_IN_TYPE_CH4 |
R/W |
0 |
This bit controls channel 4 input type. If it’s set to differential type(value of this bit is 1), channel 5 should also be set to differential type since they are hardware-fixed differential pair.
|
3 |
BIT_ADC_IN_TYPE_CH3 |
R/W |
0 |
This bit controls channel 3 input type. If it’s set to differential type(value of this bit is 1), channel 2 should also be set to differential type since they are hardware-fixed differential pair.
|
2 |
BIT_ADC_IN_TYPE_CH2 |
R/W |
0 |
This bit controls channel 2 input type. If it’s set to differential type(value of this bit is 1), channel 3 should also be set to differential type since they are hardware-fixed differential pair.
|
1 |
BIT_ADC_IN_TYPE_CH1 |
R/W |
0 |
This bit controls channel 1 input type. If it’s set to differential type(value of this bit is 1), channel 0 should also be set to differential type since they are hardware-fixed differential pair.
|
0 |
BIT_ADC_IN_TYPE_CH0 |
R/W |
0 |
This bit controls channel 0 input type. If it’s set to differential type(value of this bit is 1), channel 1 should also be set to differential type since they are hardware-fixed differential pair.
|
REG_ADC_COMP_TH_CHx
Name: ADC Channel x Comparison Threshold Register
Size: 32
Address offset: 008h + 04h * x (x=0, 1, 2, 3, 4, 5, 6, 7, 8, 9)
Read/write access: R/W
Channel comparison threshold
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:28 |
RSVD |
R |
- |
Reserved |
27:16 |
BIT_ADC_COMP_TH_H_CHx |
R/W |
0h |
This field defines the higher threshold of channel x for ADC automatic comparison. |
15:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_COMP_TH_L_CHx |
R/W |
0h |
This field defines the lower threshold of channel x for ADC automatic comparison. |
REG_ADC_COMP_CTRL
Name: ADC Comparison Control Register
Size: 32
Address offset: 030h
Read/write access: R/W
This register can be used to control every channel’s comparison criterion. There are 3 kinds of
criterions.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:20 |
RSVD |
R |
- |
Reserved |
19:18 |
BIT_ADC_COMP_CTRL_CH9 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
17:16 |
BIT_ADC_COMP_CTRL_CH8 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
15:14 |
BIT_ADC_COMP_CTRL_CH7 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
13:12 |
BIT_ADC_COMP_CTRL_CH6 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
11:10 |
BIT_ADC_COMP_CTRL_CH5 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
9:8 |
BIT_ADC_COMP_CTRL_CH4 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
7:6 |
BIT_ADC_COMP_CTRL_CH3 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
5:4 |
BIT_ADC_COMP_CTRL_CH2 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
3:2 |
BIT_ADC_COMP_CTRL_CH1 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
1:0 |
BIT_ADC_COMP_CTRL_CH0 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
REG_ADC_COMP_STS
Name: ADC Comparison Status Register
Size: 32
Address offset: 034h
Read/write access: R
The comparison status of every channel
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:20 |
RSVD |
R |
- |
Reserved |
19:18 |
BIT_ADC_COMP_STS_CH9 |
R |
0h |
This field reflects the comparison result of channel 9 immediately. |
17:16 |
BIT_ADC_COMP_STS_CH8 |
R |
0h |
This field reflects the comparison result of channel 8 immediately. |
15:14 |
BIT_ADC_COMP_STS_CH7 |
R |
0h |
This field reflects the comparison result of channel 7 immediately. |
13:12 |
BIT_ADC_COMP_STS_CH6 |
R |
0h |
This field reflects the comparison result of channel 6 immediately. |
11:10 |
BIT_ADC_COMP_STS_CH5 |
R |
0h |
This field reflects the comparison result of channel 5 immediately. |
9:8 |
BIT_ADC_COMP_STS_CH4 |
R |
0h |
This field reflects the comparison result of channel 4 immediately. |
7:6 |
BIT_ADC_COMP_STS_CH3 |
R |
0h |
This field reflects the comparison result of channel 3 immediately. |
5:4 |
BIT_ADC_COMP_STS_CH2 |
R |
0h |
This field reflects the comparison result of channel 2 immediately. |
3:2 |
BIT_ADC_COMP_STS_CH1 |
R |
0h |
This field reflects the comparison result of channel 1 immediately. |
1:0 |
BIT_ADC_COMP_STS_CH0 |
R |
0h |
This field reflects the comparison result of channel 0 immediately. |
REG_ADC_CHSW_LIST_0
Name: ADC Channel Switch List 0 Register
Size: 32
Address offset: 038h
Read/write access: R/W
Software channel list 0, to define the analog channels to own channel list
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:28 |
BIT_ADC_CHSW_7 |
R/W |
0h |
This field defines the number 7 channel to do a conversion when a conversion event takes place. |
27:24 |
BIT_ADC_CHSW_6 |
R/W |
0h |
This field defines the number 6 channel to do a conversion when a conversion event takes place. |
23:20 |
BIT_ADC_CHSW_5 |
R/W |
0h |
This field defines the number 5 channel to do a conversion when a conversion event takes place. |
19:16 |
BIT_ADC_CHSW_4 |
R/W |
0h |
This field defines the number 4 channel to do a conversion when a conversion event takes place. |
15:12 |
BIT_ADC_CHSW_3 |
R/W |
0h |
This field defines the number 3 channel to do a conversion when a conversion event takes place. |
11:8 |
BIT_ADC_CHSW_2 |
R/W |
0h |
This field defines the number 2 channel to do a conversion when a conversion event takes place. |
7:4 |
BIT_ADC_CHSW_1 |
R/W |
0h |
This field defines the number 1 channel to do a conversion when a conversion event takes place. |
3:0 |
BIT_ADC_CHSW_0 |
R/W |
0h |
This field defines the number 0 channel to do a conversion when a conversion event takes place. |
REG_ADC_CHSW_LIST_1
Name: ADC Channel Switch List 1 Register
Size: 32
Address offset: 03Ch
Read/write access: R/W
Software channel list 1, refer to REG_ADC_CHSW_LIST_0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:28 |
BIT_ADC_CHSW_15 |
R/W |
0h |
This field defines the number 15 channel to do a conversion when a conversion event takes place. |
27:24 |
BIT_ADC_CHSW_14 |
R/W |
0h |
This field defines the number 14 channel to do a conversion when a conversion event takes place. |
23:20 |
BIT_ADC_CHSW_13 |
R/W |
0h |
This field defines the number 13 channel to do a conversion when a conversion event takes place. |
19:16 |
BIT_ADC_CHSW_12 |
R/W |
0h |
This field defines the number 12 channel to do a conversion when a conversion event takes place. |
15:12 |
BIT_ADC_CHSW_11 |
R/W |
0h |
This field defines the number 11 channel to do a conversion when a conversion event takes place. |
11:8 |
BIT_ADC_CHSW_10 |
R/W |
0h |
This field defines the number 10 channel to do a conversion when a conversion event takes place. |
7:4 |
BIT_ADC_CHSW_9 |
R/W |
0h |
This field defines the number 9 channel to do a conversion when a conversion event takes place. |
3:0 |
BIT_ADC_CHSW_8 |
R/W |
0h |
This field defines the number 8 channel to do a conversion when a conversion event takes place. |
REG_ADC_RST_LIST
Name: ADC Reset Channel List Register
Size: 32
Address offset: 040h
Read/write access: R/W
Reset the channel list to default status
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_RST_LIST |
R/W |
0h |
This bit controls to reset the channel switch to default state or not. Once this bit is set, the auto/manual channel switch goes to the first channel as a default state.
|
REG_ADC_AUTO_CSW_CTRL
Name: ADC Automatic Channel Switch Control Register
Size: 32
Address offset: 044h
Read/write access: R/W
Automatic switch channel function
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_AUTO_CSW_EN |
R/W |
0h |
This bit controls the automatic channel switch enabled or disabled.
|
REG_ADC_SW_TRIG
Name: ADC Software Trigger Register
Size: 32
Address offset: 048h
Read/write access: R/W
Software controls to trigger the channel switch
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_SW_TRIG |
R/W |
0h |
This bit controls the ADC module to do a conversion. Every time this bit is set to 1, ADC module would switch to a new channel and do one conversion. Therefore, this bit could be used as a start-convert event which is controlled by software. Every time a conversion is done, software MUST clear this bit manually.
|
REG_ADC_LAST_CH
Name: ADC Last Channel Register
Size: 32
Address offset: 04Ch
Read/write access: R
This register records the last channel
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
- |
Reserved |
3:0 |
BIT_ADC_LAST_CH |
R |
0h |
This field reflects the last used channel |
REG_ADC_BUSY_STS
Name: ADC Busy Status Register
Size: 32
Address offset: 050h
Read/write access: R
This register reflects the ADC FSM and fifo status
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
- |
Reserved |
2 |
BIT_ADC_FIFO_EMPTY |
R |
1 |
|
1 |
BIT_ADC_FIFO_FULL_REAL |
R |
0 |
|
0 |
BIT_ADC_BUSY_STS |
R |
0 |
This bit reflects the ADC is busy or not. If the ADC is processing a conversion of a channel, this bit remains 1 which indicates it’s busy. Once a conversion is done, this bit becomes 0 which indicates it’s ready to do another conversion.
|
REG_ADC_INTR_CTRL
Name: ADC Interrupt Control Register
Size: 32
Address offset: 054h
Read/write access: R/W
This register to enable or disable the different kinds of interrupts
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:29 |
RSVD |
R |
- |
Reserved |
28 |
BIT_ADC_IT_COMPRE_CH9_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 9 comparison criterion matching is rising edge.
|
27 |
BIT_ADC_IT_COMPRE_CH8_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 8 comparison criterion matching is rising edge.
|
26 |
BIT_ADC_IT_COMPRE_CH7_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 7 comparison criterion matching is rising edge.
|
25 |
BIT_ADC_IT_COMPRE_CH6_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 6 comparison criterion matching is rising edge.
|
24 |
BIT_ADC_IT_COMPRE_CH5_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 5 comparison criterion matching is rising edge.
|
23 |
BIT_ADC_IT_COMPRE_CH4_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 4 comparison criterion matching is rising edge.
|
22 |
BIT_ADC_IT_COMPRE_CH3_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 3 comparison criterion matching is rising edge.
|
21 |
BIT_ADC_IT_COMPRE_CH2_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 2 comparison criterion matching is rising edge.
|
20 |
BIT_ADC_IT_COMPRE_CH1_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 1 comparison criterion matching is rising edge.
|
19 |
BIT_ADC_IT_COMPRE_CH0_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 0 comparison criterion matching is rising edge.
|
18 |
RSVD |
R |
- |
Reserved |
17 |
BIT_ADC_IT_COMP_CH9_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 9 comparison criterion matches.
|
16 |
BIT_ADC_IT_COMP_CH8_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 8 comparison criterion matches.
|
15 |
BIT_ADC_IT_COMP_CH7_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 7 comparison criterion matches.
|
14 |
BIT_ADC_IT_COMP_CH6_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 6 comparison criterion matches.
|
13 |
BIT_ADC_IT_COMP_CH5_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 5 comparison criterion matches.
|
12 |
BIT_ADC_IT_COMP_CH4_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 4 comparison criterion matches.
|
11 |
BIT_ADC_IT_COMP_CH3_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 3 comparison criterion matches.
|
10 |
BIT_ADC_IT_COMP_CH2_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 2 comparison criterion matches.
|
9 |
BIT_ADC_IT_COMP_CH1_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 1 comparison criterion matches.
|
8 |
BIT_ADC_IT_COMP_CH0_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 0 comparison criterion matches.
|
7 |
BIT_ADC_IT_ERR_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when an error state takes place.
|
6 |
BIT_ADC_IT_DAT_OVW_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a data overwritten situation takes place.
|
5 |
BIT_ADC_IT_FIFO_EMPTY_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO empty state takes place.
|
4 |
BIT_ADC_IT_FIFO_OVER_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO overflow state takes place.
|
3 |
BIT_ADC_IT_FIFO_FULL_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO full state takes place.
|
2 |
BIT_ADC_IT_CHCV_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a particular channel conversion is done. Please refer to reg_adc_it_chno_con
|
1 |
BIT_ADC_IT_CV_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not every time a conversion is done. No matter ADC module is in what kind of operation mode. Every time a conversion is executed, ADC module would notify system if This bit is set.
|
0 |
BIT_ADC_IT_CVLIST_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a conversion of the last channel in the list is done. For example, in automatic mode conversions would be executed continuously. Every time the last channel conversion is done, which means all channel conversions in the list is done, ADC could notify system if This bit is set.
|
REG_ADC_INTR_RAW_STS
Name: ADC Interrupt Raw Status Register
Size: 32
Address offset: 058h
Read/write access: R
This register to record the different kinds of interrupt raw status (bypass the enable register’s
control)
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:29 |
RSVD |
R |
- |
Reserved |
28 |
BIT_ADC_IT_COMPRE_CH9_RAW_STS |
R |
0h |
|
27 |
BIT_ADC_IT_COMPRE_CH8_RAW_STS |
R |
0h |
Merged |
26 |
BIT_ADC_IT_COMPRE_CH7_RAW_STS |
R |
0h |
Merged |
25 |
BIT_ADC_IT_COMPRE_CH6_RAW_STS |
R |
0h |
Merged |
24 |
BIT_ADC_IT_COMPRE_CH5_RAW_STS |
R |
0h |
Merged |
23 |
BIT_ADC_IT_COMPRE_CH4_RAW_STS |
R |
0h |
Merged |
22 |
BIT_ADC_IT_COMPRE_CH3_RAW_STS |
R |
0h |
Merged |
21 |
BIT_ADC_IT_COMPRE_CH2_RAW_STS |
R |
0h |
Merged |
20 |
BIT_ADC_IT_COMPRE_CH1_RAW_STS |
R |
0h |
Merged |
19 |
BIT_ADC_IT_COMPRE_CH0_RAW_STS |
R |
0h |
Merged |
18 |
RSVD |
R |
- |
Reserved |
17 |
BIT_ADC_IT_COMP_CH9_RAW_STS |
R |
0h |
Merged |
16 |
BIT_ADC_IT_COMP_CH8_RAW_STS |
R |
0h |
Merged |
15 |
BIT_ADC_IT_COMP_CH7_RAW_STS |
R |
0h |
Merged |
14 |
BIT_ADC_IT_COMP_CH6_RAW_STS |
R |
0h |
Merged |
13 |
BIT_ADC_IT_COMP_CH5_RAW_STS |
R |
0h |
Merged |
12 |
BIT_ADC_IT_COMP_CH4_RAW_STS |
R |
0h |
Merged |
11 |
BIT_ADC_IT_COMP_CH3_RAW_STS |
R |
0h |
Merged |
10 |
BIT_ADC_IT_COMP_CH2_RAW_STS |
R |
0h |
Merged |
9 |
BIT_ADC_IT_COMP_CH1_RAW_STS |
R |
0h |
Merged |
8 |
BIT_ADC_IT_COMP_CH0_RAW_STS |
R |
0h |
Merged |
7 |
BIT_ADC_IT_ERR_RAW_STS |
R |
0h |
Merged |
6 |
BIT_ADC_IT_DAT_OVW_RAW_STS |
R |
0h |
Merged |
5 |
BIT_ADC_IT_FIFO_EMPTY_RAW_STS |
R |
1h |
Merged |
4 |
BIT_ADC_IT_FIFO_OVER_RAW_STS |
R |
0h |
Merged |
3 |
BIT_ADC_IT_FIFO_FULL_RAW_STS |
R |
0h |
Merged |
2 |
BIT_ADC_IT_CHCV_END_RAW_STS |
R |
0h |
Merged |
1 |
BIT_ADC_IT_CV_END_RAW_STS |
R |
0h |
Merged |
0 |
BIT_ADC_IT_CVLIST_END_RAW_STS |
R |
0h |
Merged |
REG_ADC_INTR_STS
Name: ADC Interrupt Status Register
Size: 32
Address offset: 05Ch
Read/write access: R/W
This register to record the different kinds of interrupt status
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:29 |
RSVD |
R |
- |
Reserved |
28 |
BIT_ADC_IT_COMPRE_CH9_STS |
R/W |
0h |
|
27 |
BIT_ADC_IT_COMPRE_CH8_STS |
R/W |
0h |
Merged |
26 |
BIT_ADC_IT_COMPRE_CH7_STS |
R/W |
0h |
Merged |
25 |
BIT_ADC_IT_COMPRE_CH6_STS |
R/W |
0h |
Merged |
24 |
BIT_ADC_IT_COMPRE_CH5_STS |
R/W |
0h |
Merged |
23 |
BIT_ADC_IT_COMPRE_CH4_STS |
R/W |
0h |
Merged |
22 |
BIT_ADC_IT_COMPRE_CH3_STS |
R/W |
0h |
Merged |
21 |
BIT_ADC_IT_COMPRE_CH2_STS |
R/W |
0h |
Merged |
20 |
BIT_ADC_IT_COMPRE_CH1_STS |
R/W |
0h |
Merged |
19 |
BIT_ADC_IT_COMPRE_CH0_STS |
R/W |
0h |
Merged |
18 |
RSVD |
R |
- |
Reserved |
17 |
BIT_ADC_IT_COMP_CH9_STS |
R/W |
0h |
Merged |
16 |
BIT_ADC_IT_COMP_CH8_STS |
R/W |
0h |
Merged |
15 |
BIT_ADC_IT_COMP_CH7_STS |
R/W |
0h |
Merged |
14 |
BIT_ADC_IT_COMP_CH6_STS |
R/W |
0h |
Merged |
13 |
BIT_ADC_IT_COMP_CH5_STS |
R/W |
0h |
Merged |
12 |
BIT_ADC_IT_COMP_CH4_STS |
R/W |
0h |
Merged |
11 |
BIT_ADC_IT_COMP_CH3_STS |
R/W |
0h |
Merged |
10 |
BIT_ADC_IT_COMP_CH2_STS |
R/W |
0h |
Merged |
9 |
BIT_ADC_IT_COMP_CH1_STS |
R/W |
0h |
Merged |
8 |
BIT_ADC_IT_COMP_CH0_STS |
R/W |
0h |
Merged |
7 |
BIT_ADC_IT_ERR_STS |
R/W |
0h |
Merged |
6 |
BIT_ADC_IT_DAT_OVW_STS |
R/W |
0h |
Merged |
5 |
BIT_ADC_IT_FIFO_EMPTY_STS |
R/W |
0h |
Merged |
4 |
BIT_ADC_FIFO_OVER_STS |
R/W |
0h |
Merged |
3 |
BIT_ADC_FIFO_FULL_STS |
R/W |
0h |
Merged |
2 |
BIT_ADC_CHCV_END_STS |
R/W |
0h |
Merged |
1 |
BIT_ADC_CV_END_STS |
R/W |
0h |
Merged |
0 |
BIT_ADC_CVLIST_END_STS |
R/W |
0h |
Merged |
REG_ADC_IT_CHNO_CON
Name: ADC Interrupt Channel Number Configuration Register
Size: 32
Address offset: 060h
Read/write access: R/W
The specific channel to trigger interrupt
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
- |
Reserved |
3:0 |
BIT_ADC_IT_CHNO_CON |
R/W |
0h |
This field defines that ADC module should send interrupt signal to system when a conversion which of channel number is the same as this field. This register is only valid when bit_adc_it_chcv_end_en is set. Bit_adc_it_chno_con: channel number |
REG_ADC_FULL_LVL
Name: ADC FIFO Full Threshold Register
Size: 32
Address offset: 064h
Read/write access: R/W
The FIFO full threshold
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:6 |
RSVD |
R |
- |
Reserved |
5:0 |
BIT_ADC_FULL_LVL |
R/W |
0h |
This field defines the FIFO full entry thredshold level and it’s used for FIFO full interrupt. It should be set according to ADC FIFO depth. A value of 0 sets the threshold for 1 entry, and a value of 15 sets the threshold for 16 entries. |
REG_ADC_EXT_TRIG_TIMER_SEL
Name: ADC External Trigger Timer Select Register
Size: 32
Address offset: 068h
Read/write access: R/W
This register is used to select the specific external timer source
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
- |
Reserved |
2:0 |
BIT_ADC_EXT_TRIG_TIMER_SEL |
R/W |
0h |
These three bits defines which timer channel would be used to make ADC module do a conversion.
|
REG_ADC_DATA_CHx
Name: ADC Channel x Data Register
Size: 32
Address offset: 06Ch + 04h * x (x=0, 1, 2, 3, 4, 5, 6, 7, 8, 9)
Read/write access: R
This register is used to store the channel data , ready and overwritten information
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:18 |
RSVD |
R |
- |
Reserved |
17 |
BIT_ADC_DAT_RDY_CHx |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_chx. |
16 |
BIT_ADC_DAT_OVW_CHx |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_chx taking place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_chx.
|
15:12 |
BIT_ADC_NUM_CHx |
R |
0 |
This field contains the newest conversion data of channel x [15:12]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
11:0 |
BIT_ADC_DATA_CHx |
R |
0 |
This field contains the newest conversion data of channel x [11:0]: newest data |
REG_ADC_DATA_GLOBAL
Name: ADC Global Data Register
Size: 32
Address offset: 094h
Read/write access: R
This register is used to store global data, ready, channel and overwritten information.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21:18 |
BIT_ADC_DAT_CH |
R |
0 |
This field indicates which channel data is procedd right now |
17 |
BIT_ADC_DAT_RDY_GLOBAL |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_global |
16 |
BIT_ADC_DAT_OVW_GLOBAL |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global taking place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field.
|
15:12 |
BIT_ADC_CH_NUM_GLOBAL |
R |
0 |
This field contains the newest conversion data of channel in the list. [15:12]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
11:0 |
BIT_ADC_DATA_GLOBAL |
R |
0 |
This field contains the newest conversion data of channel in the list. [11:0]: newest data |
REG_ADC_FLR
Name: ADC FIFO Level Register
Size: 32
Address offset: 098h
Read/write access: R
This register is used to store fifo entry number.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:5 |
RSVD |
R |
- |
Reserved |
4:0 |
BIT_ADC_FLR |
R |
0 |
This field records the current ADC FIFO entry number. |
REG_ADC_CLR_FIFO
Name: ADC Clear FIFO Register
Size: 32
Address offset: 09Ch
Read/write access: R/W
This register is used to clear FIFO.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_CLR_FIFO |
R/W |
0 |
This bit is used to clear FIFO contents and makes it to the default status. Every time this bit is set to 1. FIFO would be cleared to the default status. Software should set this bit to 0 after FIFO is cleared.
|
REG_ADC_CLK_DIV
Name: ADC Clock Divider Register
Size: 32
Address offset: 0A0h
Read/write access: R/W
This register is used to control clock dividend.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
- |
Reserved |
2:0 |
BIT_ADC_CLK_DIV |
R/W |
3h |
This field defines clock driver level of ADC module. A value of 0 is for clock divided by 2. A value of 1 is for clock divided by 4. A value of 2 is for clock divided by 8. A value of 3 is for clock divided by 12. A value of 4 is for clock divided by 16. A value of 5 is for clock divided by 32. A value of 6 is for clock divided by 64. |
REG_ADC_DELAY_CNT
Name: ADC Delay Count Register
Size: 32
Address offset: 0A4h
Read/write access: R/W
This register is used to configure ADC delay and channel unmask.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31 |
BIT_ADC_CH_UNMASK |
R/W |
0 |
Enable BIT_ADC_DAT_CHID |
30:10 |
RSVD |
R |
- |
Reserved |
9:8 |
BIT_ADC_CLK_SEL |
R/W |
0 |
Just config to 00 |
7:4 |
RSVD |
R |
- |
Reserved |
3:2 |
BIT_ADC_DELAY |
R/W |
0 |
This field defines channel switch data delay count. A value of 0 is for using default count of hardware. |
1:0 |
BIT_ADC_CTRL_DELAY |
R/W |
0 |
This field defines channel switch ctrl delay count. A value of 0 is for using default count of hardware. |
REG_ADC_PWR_CTRL
Name: ADC Power Control Register
Size: 32
Address offset: 0A8h
Read/write access: R/W
This register is used to control the ADC power and debug configuration.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
- |
Reserved |
3 |
BIT_ADC_DBG_EN |
R/W |
0 |
Debug port enable |
2:1 |
BIT_ADC_DBG_SEL |
R/W |
0 |
Debug port select |
0 |
BIT_ADC_PWR_CTRL |
R/W |
0 |
This field is used to power control |
REG_ADC_SW_TMODE
Name: ADC Software Test Mode
Size: 32
Address offset: 0ACh
Read/write access: R/W
This register is used to set the software test mode.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_SW_TMODE |
R/W |
0 |
This bit is used to change the high 4 bits in FIFO.
|
REG_ADC_DUMMY
Name: ADC Dummy Register
Size: 32
Address offset: 0B0h
Read/write access: R/W
Dummy register
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DUMMY |
R/W |
ffffh |
Dummy register |
REGISTER_CONTENTS=RTL8720E
REGISTER_CONTENTS=RTL8720E
REGISTER_CONTENTS=RTL8720E
Base Address: 0x42012000
Name |
Address offset |
Access |
Description |
|---|---|---|---|
000h |
R/W |
Basic configuration of ADC including enable and operation mode |
|
004h |
R/W |
Analog ADC input type configuration |
|
008h |
R/W |
Channel comparison threshold |
|
00Ch |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
010h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
014h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
018h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
01Ch |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
020h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
024h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
028h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
02Ch |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
030h |
R/W |
Channel comparison criterion control register, can be used to control every channel’s comparison criterion. There are 3 kinds of criterions. |
|
034h |
R |
The comparison status of every channel |
|
038h |
R/W |
Software channel list 0, to define the analog channels to own channel list |
|
03Ch |
R/W |
Software channel list 1, refer to REG_ADC_CHSW_LIST_0 |
|
040h |
R/W |
Reset the channel list to default status |
|
044h |
R/W |
Automatic switch channel function |
|
048h |
R/W |
Software controls to trigger the channel switch |
|
04Ch |
R |
The register records the last channel |
|
050h |
R |
The register reflects the ADC FSM and fifo status |
|
054h |
R/W |
The register to enable or disable the different kinds of interrupts |
|
058h |
R |
The register to record the different kinds of interrupt raw status (bypass the enable register’s control) |
|
05Ch |
R/W |
The register to record the different kinds of interrupt status |
|
060h |
R/W |
The specific channel to trigger interrupt |
|
064h |
R/W |
The fifo full threshold |
|
068h |
R/W |
The register to select the specific external timer source |
|
06Ch |
R |
The register to store the channel data, ready and overwritten information |
|
070h |
R |
Refer to REG_ADC_DATA_CH0 |
|
074h |
R |
Refer to REG_ADC_DATA_CH0 |
|
078h |
R |
Refer to REG_ADC_DATA_CH0 |
|
07Ch |
R |
Refer to REG_ADC_DATA_CH0 |
|
080h |
R |
Refer to REG_ADC_DATA_CH0 |
|
084h |
R |
Refer to REG_ADC_DATA_CH0 |
|
088h |
R |
Refer to REG_ADC_DATA_CH0 |
|
08Ch |
R |
Refer to REG_ADC_DATA_CH0 |
|
090h |
R |
Refer to REG_ADC_DATA_CH0 |
|
094h |
R |
The register to store global data, ready, channel and overwritten information |
|
098h |
R |
The register to store fifo entry number |
|
09Ch |
R/W |
The register to clear fifo |
|
0A0h |
R/W |
The register to control clock dividend |
|
0A4h |
R/W |
The register to configure ADC delay and channel unmask |
|
0A8h |
R/W |
The register to control the ADC power and debug configuration |
|
0ACh |
R/W |
The register to set the software test mode |
REG_ADC_CONF
Name: ADC Configuration Register
Size: 32
Address offset: 000h
Read/write access: R/W
Basic configuration of ADC including enable and operation mode
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:10 |
RSVD |
R |
- |
Reserved |
9 |
BIT_ADC_ENABLE |
R/W |
0h |
This bit is for ADC enable control |
8 |
RSVD |
R |
- |
Reserved |
7:4 |
BIT_ADC_CVLIST_LEN |
R/W |
0h |
This field defines the number of items in the ADC conversion channel list. |
3:1 |
BIT_ADC_OP_MOD |
R/W |
0h |
These bits selects ADC operation mode. 0: software trigger mode.
|
0 |
BIT_ADC_REF_IN_SEL |
R/W |
0h |
This bit selects ADC reference voltage input.
|
REG_ADC_IN_TYPE
Name: ADC Input Type Register
Size: 32
Address offset: 004h
Read/write access: R/W
Analog ADC input type configuration
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:10 |
RSVD |
R |
- |
Reserved |
9 |
BIT_ADC_IN_TYPE_CH9 |
R |
0 |
This bit reflects which kind of input type channel 9 is. Since channel 9 is a fixed internal channel. |
8 |
BIT_ADC_IN_TYPE_CH8 |
R |
0 |
This bit reflects which kind of input type channel 8 is. Since channel 8 is a fixed internal channel. |
7 |
BIT_ADC_IN_TYPE_CH7 |
R |
0 |
This bit reflects which kind of input type channel 7 is. Since channel 7 is a fixed internal channel. |
6 |
BIT_ADC_IN_TYPE_CH6 |
R |
0 |
This bit reflects which kind of input type channel 6 is. Since channel 6 is a fixed internal channel. |
5 |
BIT_ADC_IN_TYPE_CH5 |
R/W |
0 |
This bit controls channel 5 input type. If it’s set to differential type(value of this bit is 1), channel 4 should also be set to differential type since they are hardware-fixed differential pair.
|
4 |
BIT_ADC_IN_TYPE_CH4 |
R/W |
0 |
This bit controls channel 4 input type. If it’s set to differential type(value of this bit is 1), channel 5 should also be set to differential type since they are hardware-fixed differential pair.
|
3 |
BIT_ADC_IN_TYPE_CH3 |
R/W |
0 |
This bit controls channel 3 input type. If it’s set to differential type(value of this bit is 1), channel 2 should also be set to differential type since they are hardware-fixed differential pair.
|
2 |
BIT_ADC_IN_TYPE_CH2 |
R/W |
0 |
This bit controls channel 2 input type. If it’s set to differential type(value of this bit is 1), channel 3 should also be set to differential type since they are hardware-fixed differential pair.
|
1 |
BIT_ADC_IN_TYPE_CH1 |
R/W |
0 |
This bit controls channel 1 input type. If it’s set to differential type(value of this bit is 1), channel 0 should also be set to differential type since they are hardware-fixed differential pair.
|
0 |
BIT_ADC_IN_TYPE_CH0 |
R/W |
0 |
This bit controls channel 0 input type. If it’s set to differential type(value of this bit is 1), channel 1 should also be set to differential type since they are hardware-fixed differential pair.
|
REG_ADC_COMP_TH_CHx
Name: ADC Channel x Comparison Threshold Register
Size: 32
Address offset: 008h + 04h * x (x=0, 1, 2, 3, 4, 5, 6, 7, 8, 9)
Read/write access: R/W
Channel comparison threshold
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:28 |
RSVD |
R |
- |
Reserved |
27:16 |
BIT_ADC_COMP_TH_H_CHx |
R/W |
0h |
This field defines the higher threshold of channel x for ADC automatic comparison. |
15:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_COMP_TH_L_CHx |
R/W |
0h |
This field defines the lower threshold of channel x for ADC automatic comparison. |
REG_ADC_COMP_CTRL
Name: ADC Comparison Control Register
Size: 32
Address offset: 030h
Read/write access: R/W
Channel comparison criterion control register, can be used to control every channel’s comparison
criterion. There are 3 kinds of criterions.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:20 |
RSVD |
R |
- |
Reserved |
19:18 |
BIT_ADC_COMP_CTRL_CH9 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
17:16 |
BIT_ADC_COMP_CTRL_CH8 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
15:14 |
BIT_ADC_COMP_CTRL_CH7 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
13:12 |
BIT_ADC_COMP_CTRL_CH6 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
11:10 |
BIT_ADC_COMP_CTRL_CH5 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
9:8 |
BIT_ADC_COMP_CTRL_CH4 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
7:6 |
BIT_ADC_COMP_CTRL_CH3 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
5:4 |
BIT_ADC_COMP_CTRL_CH2 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
3:2 |
BIT_ADC_COMP_CTRL_CH1 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
1:0 |
BIT_ADC_COMP_CTRL_CH0 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
REG_ADC_COMP_STS
Name: ADC Comparison Status Register
Size: 32
Address offset: 034h
Read/write access: R
The comparison status of every channel
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:20 |
RSVD |
R |
- |
Reserved |
19:18 |
BIT_ADC_COMP_STS_CH9 |
R |
0h |
This field reflects the comparison result of channel 9 immediately |
17:16 |
BIT_ADC_COMP_STS_CH8 |
R |
0h |
This field reflects the comparison result of channel 8 immediately |
15:14 |
BIT_ADC_COMP_STS_CH7 |
R |
0h |
This field reflects the comparison result of channel 7 immediately |
13:12 |
BIT_ADC_COMP_STS_CH6 |
R |
0h |
This field reflects the comparison result of channel 6 immediately |
11:10 |
BIT_ADC_COMP_STS_CH5 |
R |
0h |
This field reflects the comparison result of channel 5 immediately |
9:8 |
BIT_ADC_COMP_STS_CH4 |
R |
0h |
This field reflects the comparison result of channel 4 immediately |
7:6 |
BIT_ADC_COMP_STS_CH3 |
R |
0h |
This field reflects the comparison result of channel 3 immediately |
5:4 |
BIT_ADC_COMP_STS_CH2 |
R |
0h |
This field reflects the comparison result of channel 2 immediately |
3:2 |
BIT_ADC_COMP_STS_CH1 |
R |
0h |
This field reflects the comparison result of channel 1 immediately |
1:0 |
BIT_ADC_COMP_STS_CH0 |
R |
0h |
This field reflects the comparison result of channel 0 immediately |
REG_ADC_CHSW_LIST_0
Name: ADC Channel Switch List 0 Register
Size: 32
Address offset: 038h
Read/write access: R/W
Software channel list 0, to define the analog channels to own channel list
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:28 |
BIT_ADC_CHSW_7 |
R/W |
0h |
This field defines the number 7 channel to do a conversion when a conversion event takes place. |
27:24 |
BIT_ADC_CHSW_6 |
R/W |
0h |
This field defines the number 6 channel to do a conversion when a conversion event takes place. |
23:20 |
BIT_ADC_CHSW_5 |
R/W |
0h |
This field defines the number 5 channel to do a conversion when a conversion event takes place. |
19:16 |
BIT_ADC_CHSW_4 |
R/W |
0h |
This field defines the number 4 channel to do a conversion when a conversion event takes place. |
15:12 |
BIT_ADC_CHSW_3 |
R/W |
0h |
This field defines the number 3 channel to do a conversion when a conversion event takes place. |
11:8 |
BIT_ADC_CHSW_2 |
R/W |
0h |
This field defines the number 2 channel to do a conversion when a conversion event takes place. |
7:4 |
BIT_ADC_CHSW_1 |
R/W |
0h |
This field defines the number 1 channel to do a conversion when a conversion event takes place. |
3:0 |
BIT_ADC_CHSW_0 |
R/W |
0h |
This field defines the number 0 channel to do a conversion when a conversion event takes place. |
REG_ADC_CHSW_LIST_1
Name: ADC Channel Switch List 1 Register
Size: 32
Address offset: 03Ch
Read/write access: R/W
Software channel list 1, refer to REG_ADC_CHSW_LIST_0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:28 |
BIT_ADC_CHSW_15 |
R/W |
0h |
This field defines the number 15 channel to do a conversion when a conversion event takes place. |
27:24 |
BIT_ADC_CHSW_14 |
R/W |
0h |
This field defines the number 14 channel to do a conversion when a conversion event takes place. |
23:20 |
BIT_ADC_CHSW_13 |
R/W |
0h |
This field defines the number 13 channel to do a conversion when a conversion event takes place. |
19:16 |
BIT_ADC_CHSW_12 |
R/W |
0h |
This field defines the number 12 channel to do a conversion when a conversion event takes place. |
15:12 |
BIT_ADC_CHSW_11 |
R/W |
0h |
This field defines the number 11 channel to do a conversion when a conversion event takes place. |
11:8 |
BIT_ADC_CHSW_10 |
R/W |
0h |
This field defines the number 10 channel to do a conversion when a conversion event takes place. |
7:4 |
BIT_ADC_CHSW_9 |
R/W |
0h |
This field defines the number 9 channel to do a conversion when a conversion event takes place. |
3:0 |
BIT_ADC_CHSW_8 |
R/W |
0h |
This field defines the number 8 channel to do a conversion when a conversion event takes place. |
REG_ADC_RST_LIST
Name: ADC Reset Channel List Register
Size: 32
Address offset: 040h
Read/write access: R/W
Reset the channel list to default status
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_RST_LIST |
R/W |
0h |
This bit controls to reset the channel switch to default state or not. Once this bit is set, the auto/manual channel switch goes to the first channel as a default state.
|
REG_ADC_AUTO_CSW_CTRL
Name: ADC Automatic Channel Switch Control Register
Size: 32
Address offset: 044h
Read/write access: R/W
Automatic switch channel function
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_AUTO_CSW_EN |
R/W |
0h |
This bit controls the automatic channel switch enabled or disabled.
|
REG_ADC_SW_TRIG
Name: ADC Software Trigger Register
Size: 32
Address offset: 048h
Read/write access: R/W
Software controls to trigger the channel switch
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_SW_TRIG |
R/W |
0h |
This bit controls the ADC module to do a conversion. Every time this bit is set to 1, ADC module would switch to a new channel and do one conversion. Therefore, this bit could be used as a start-convert event which is controlled by software. Every time a conversion is done, software MUST clear this bit manually. The interval between clearing and restart this bit must exceed one sample clock period.
|
REG_ADC_LAST_CH
Name: ADC Last Channel Register
Size: 32
Address offset: 04Ch
Read/write access: R
The register records the last channel
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
- |
Reserved |
3:0 |
BIT_ADC_LAST_CH |
R |
0h |
This field reflects the last used channel |
REG_ADC_BUSY_STS
Name: ADC Busy Status Register
Size: 32
Address offset: 050h
Read/write access: R
The register reflects the ADC FSM and fifo status
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
- |
Reserved |
2 |
BIT_ADC_FIFO_EMPTY |
R |
1 |
|
1 |
BIT_ADC_FIFO_FULL_REAL |
R |
0 |
|
0 |
BIT_ADC_BUSY_STS |
R |
0 |
This bit reflects the ADC is busy or not. If the ADC is processing a conversion of a channel, this bit remains 1 which indicates it’s busy. Once a conversion is done, this bit becomes 0 which indicates it’s ready to do another conversion.
|
REG_ADC_INTR_CTRL
Name: ADC Interrupt Control Register
Size: 32
Address offset: 054h
Read/write access: R/W
The register to enable or disable the different kinds of interrupts
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:18 |
RSVD |
R |
- |
Reserved |
17 |
BIT_ADC_IT_COMP_CH9_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 9 comparison criterion matches.
|
16 |
BIT_ADC_IT_COMP_CH8_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 8 comparison criterion matches.
|
15 |
BIT_ADC_IT_COMP_CH7_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 7 comparison criterion matches.
|
14 |
BIT_ADC_IT_COMP_CH6_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 6 comparison criterion matches.
|
13 |
BIT_ADC_IT_COMP_CH5_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 5 comparison criterion matches.
|
12 |
BIT_ADC_IT_COMP_CH4_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 4 comparison criterion matches.
|
11 |
BIT_ADC_IT_COMP_CH3_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 3 comparison criterion matches.
|
10 |
BIT_ADC_IT_COMP_CH2_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 2 comparison criterion matches.
|
9 |
BIT_ADC_IT_COMP_CH1_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 1 comparison criterion matches.
|
8 |
BIT_ADC_IT_COMP_CH0_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 0 comparison criterion matches.
|
7 |
BIT_ADC_IT_ERR_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when an error state takes place.
|
6 |
BIT_ADC_IT_DAT_OVW_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a data overwritten situation takes place.
|
5 |
BIT_ADC_IT_FIFO_EMPTY_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO empty state takes place.
|
4 |
BIT_ADC_IT_FIFO_OVER_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO overflow state takes place.
|
3 |
BIT_ADC_IT_FIFO_FULL_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO full state takes place.
|
2 |
BIT_ADC_IT_CHCV_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a particular channel conversion is done. Please refer to reg_adc_it_chno_con
|
1 |
BIT_ADC_IT_CV_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not every time a conversion is done. No matter ADC module is in what kind of operation mode. Every time a conversion is executed, ADC module would notify system if This bit is set.
|
0 |
BIT_ADC_IT_CVLIST_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a conversion of the last channel in the list is done. For example, in automatic mode conversions would be executed continuously. Every time the last channel conversion is done, which means all channel conversions in the list is done, ADC could notify system if This bit is set.
|
REG_ADC_INTR_RAW_STS
Name: ADC Interrupt Raw Status Register
Size: 32
Address offset: 058h
Read/write access: R
The register to record the different kinds of interrupt raw status (bypass the enable register’s
control)
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:18 |
RSVD |
R |
- |
Reserved |
17 |
BIT_ADC_IT_COMP_CH9_RAW_STS |
R |
0h |
|
16 |
BIT_ADC_IT_COMP_CH8_RAW_STS |
R |
0h |
Merged |
15 |
BIT_ADC_IT_COMP_CH7_RAW_STS |
R |
0h |
Merged |
14 |
BIT_ADC_IT_COMP_CH6_RAW_STS |
R |
0h |
Merged |
13 |
BIT_ADC_IT_COMP_CH5_RAW_STS |
R |
0h |
Merged |
12 |
BIT_ADC_IT_COMP_CH4_RAW_STS |
R |
0h |
Merged |
11 |
BIT_ADC_IT_COMP_CH3_RAW_STS |
R |
0h |
Merged |
10 |
BIT_ADC_IT_COMP_CH2_RAW_STS |
R |
0h |
Merged |
9 |
BIT_ADC_IT_COMP_CH1_RAW_STS |
R |
0h |
Merged |
8 |
BIT_ADC_IT_COMP_CH0_RAW_STS |
R |
0h |
Merged |
7 |
BIT_ADC_IT_ERR_RAW_STS |
R |
0h |
Merged |
6 |
BIT_ADC_IT_DAT_OVW_RAW_STS |
R |
0h |
Merged |
5 |
BIT_ADC_IT_FIFO_EMPTY_RAW_STS |
R |
1h |
Merged |
4 |
BIT_ADC_IT_FIFO_OVER_RAW_STS |
R |
0h |
Merged |
3 |
BIT_ADC_IT_FIFO_FULL_RAW_STS |
R |
0h |
Merged |
2 |
BIT_ADC_IT_CHCV_END_RAW_STS |
R |
0h |
Merged |
1 |
BIT_ADC_IT_CV_END_RAW_STS |
R |
0h |
Merged |
0 |
BIT_ADC_IT_CVLIST_END_RAW_STS |
R |
0h |
Merged |
REG_ADC_INTR_STS
Name: ADC Interrupt Status Register
Size: 32
Address offset: 05Ch
Read/write access: R/W
The register to record the different kinds of interrupt status
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:18 |
RSVD |
R |
- |
Reserved |
17 |
BIT_ADC_IT_COMP_CH9_STS |
R/W |
0h |
|
16 |
BIT_ADC_IT_COMP_CH8_STS |
R/W |
0h |
Merged |
15 |
BIT_ADC_IT_COMP_CH7_STS |
R/W |
0h |
Merged |
14 |
BIT_ADC_IT_COMP_CH6_STS |
R/W |
0h |
Merged |
13 |
BIT_ADC_IT_COMP_CH5_STS |
R/W |
0h |
Merged |
12 |
BIT_ADC_IT_COMP_CH4_STS |
R/W |
0h |
Merged |
11 |
BIT_ADC_IT_COMP_CH3_STS |
R/W |
0h |
Merged |
10 |
BIT_ADC_IT_COMP_CH2_STS |
R/W |
0h |
Merged |
9 |
BIT_ADC_IT_COMP_CH1_STS |
R/W |
0h |
Merged |
8 |
BIT_ADC_IT_COMP_CH0_STS |
R/W |
0h |
Merged |
7 |
BIT_ADC_IT_ERR_STS |
R/W |
0h |
Merged |
6 |
BIT_ADC_IT_DAT_OVW_STS |
R/W |
0h |
Merged |
5 |
BIT_ADC_IT_FIFO_EMPTY_STS |
R/W |
0h |
Merged |
4 |
BIT_ADC_IT_FIFO_OVER_STS |
R/W |
0h |
Merged |
3 |
BIT_ADC_IT_FIFO_FULL_STS |
R/W |
0h |
Merged |
2 |
BIT_ADC_IT_CHCV_END_STS |
R/W |
0h |
Merged |
1 |
BIT_ADC_IT_CV_END_STS |
R/W |
0h |
Merged |
0 |
BIT_ADC_IT_CVLIST_END_STS |
R/W |
0h |
Merged |
REG_ADC_IT_CHNO_CON
Name: ADC Interrupt Channel Number Configuration Register
Size: 32
Address offset: 060h
Read/write access: R/W
The specific channel to trigger interrupt
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
- |
Reserved |
3:0 |
BIT_ADC_IT_CHNO_CON |
R/W |
0h |
This field defines that ADC module should send interrupt signal to system when a conversion which of channel number is the same as this field. This register is only valid when bit_adc_it_chcv_end_en is set. Bit_adc_it_chno_con: channel number |
REG_ADC_FULL_LVL
Name: ADC FIFO Full Threshold Register
Size: 32
Address offset: 064h
Read/write access: R/W
The fifo full threshold
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:6 |
RSVD |
R |
- |
Reserved |
5:0 |
BIT_ADC_FULL_LVL |
R/W |
0h |
This field defines the FIFO full entry thredshold level and it’s used for FIFO full interrupt. It should be set according to ADC FIFO depth. A value of 0 sets the threshold for 1 entry, and a value of 15 sets the threshold for 16 entries. |
REG_ADC_EXT_TRIG_TIMER_SEL
Name: ADC External Trigger Timer Select Register
Size: 32
Address offset: 068h
Read/write access: R/W
The register to select the specific external timer source
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
- |
Reserved |
2:0 |
BIT_ADC_EXT_TRIG_TIMER_SEL |
R/W |
0h |
These three bits defines which timer channel would be used to make ADC module do a conversion.
|
REG_ADC_DATA_CHx
Name: ADC Channel x Data Register
Size: 32
Address offset: 06Ch + 04h * x (x=0, 1, 2, 3, 4, 5, 6, 7, 8, 9)
Read/write access: R
The register to store the channel data, ready and overwritten information
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:18 |
RSVD |
R |
- |
Reserved |
17 |
BIT_ADC_DAT_RDY_CHx |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_chx. |
16 |
BIT_ADC_DAT_OVW_CHx |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_chx.
|
15:12 |
BIT_ADC_NUM_CHx |
R |
0 |
This field contains the newsest conversion data of channel x [15:12]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
11:0 |
BIT_ADC_DATA_CHx |
R |
0 |
This field contains the newsest conversion data of channel x [11:0]: newest data |
REG_ADC_DATA_GLOBAL
Name: ADC Global Data Register
Size: 32
Address offset: 094h
Read/write access: R
The register to store global data, ready, channel and overwritten information
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21:18 |
BIT_ADC_DAT_CH |
R |
0 |
This field indicates which channel data is procedd right now |
17 |
BIT_ADC_DAT_RDY_GLOBAL |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_global |
16 |
BIT_ADC_DAT_OVW_GLOBAL |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takes place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field.
|
15:12 |
BIT_ADC_CH_NUM_GLOBAL |
R |
0 |
This field contains the newsest conversion data of channel in the list. [15:12]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
11:0 |
BIT_ADC_DATA_GLOBAL |
R |
0 |
This field contains the newsest conversion data of channel in the list. [11:0]: newest data |
REG_ADC_FLR
Name: ADC FIFO Level Register
Size: 32
Address offset: 098h
Read/write access: R
The register to store fifo entry number
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:5 |
RSVD |
R |
- |
Reserved |
4:0 |
BIT_ADC_FLR |
R |
0 |
This field records the current ADC FIFO entry number. |
REG_ADC_CLR_FIFO
Name: ADC Clear FIFO Register
Size: 32
Address offset: 09Ch
Read/write access: R/W
The register to clear fifo
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_CLR_FIFO |
R/W |
0 |
This bit is used to clear FIFO contents and makes it to the default status. Every time this bit is set to 1. FIFO would be cleared to the default status. Software should set this bit to 0 after FIFO is cleared.
|
REG_ADC_CLK_DIV
Name: ADC Clock Divider Register
Size: 32
Address offset: 0A0h
Read/write access: R/W
The register to control clock dividend
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
- |
Reserved |
2:0 |
BIT_ADC_CLK_DIV |
R/W |
3h |
This field defines clock driver level of ADC module. A value of 0 is for clock divided by 2. A value of 1 is for clock divided by 4. A value of 2 is for clock divided by 8. A value of 3 is for clock divided by 12. A value of 4 is for clock divided by 16. A value of 5 is for clock divided by 32. A value of 6 is for clock divided by 64. |
REG_ADC_DELAY_CNT
Name: ADC Delay Count Register
Size: 32
Address offset: 0A4h
Read/write access: R/W
The register to configure ADC delay and channel unmask
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31 |
BIT_ADC_CH_UNMASK |
R/W |
0 |
Enable BIT_ADC_DAT_CHID |
30:10 |
RSVD |
R |
- |
Reserved |
9:8 |
BIT_ADC_CLK_SEL |
R/W |
0 |
Just config to 00 |
7:4 |
RSVD |
R |
- |
Reserved |
3:2 |
BIT_ADC_DELAY |
R/W |
0 |
This field defines channel switch data delay count. A value of 0 is for using default count of hardware. |
1:0 |
BIT_ADC_CTRL_DELAY |
R/W |
0 |
This field defines channel switch ctrl delay count. A value of 0 is for using default count of hardware. |
REG_ADC_PWR_CTRL
Name: ADC Power Control Register
Size: 32
Address offset: 0A8h
Read/write access: R/W
The register to control the ADC power and debug configuration
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
- |
Reserved |
3 |
BIT_ADC_DBG_EN |
R/W |
0 |
Debug port enable |
2:1 |
BIT_ADC_DBG_SEL |
R/W |
0 |
Debug port select |
0 |
BIT_ADC_PWR_CTRL |
R/W |
0 |
This field is used to power control |
REG_ADC_SW_TMODE
Name: ADC Software Test Mode
Size: 32
Address offset: 0ACh
Read/write access: R/W
The register to set the software test mode
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_SW_TMODE |
R/W |
0 |
This bit is used to change the high 4 bits in FIFO.
|
Base Address: 0x40812000
Name |
Address offset |
Access |
Description |
|---|---|---|---|
000h |
R/W |
Basic configuration of ADC including enable and operation mode |
|
004h |
R/W |
Analog ADC input type configuration |
|
008h |
R/W |
Channel comparison threshold |
|
00Ch |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
010h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
014h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
018h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
01Ch |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
020h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
024h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
028h |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
02Ch |
R/W |
Refer to REG_ADC_COMP_TH_CH0 |
|
030h |
R/W |
Refer to REG_ADC_COMP_TH_CH10 |
|
034h |
R/W |
Channel comparison criterion control register, can be used to control every channel’s comparison criterion. There are 3 kinds of criterions. |
|
038h |
R |
The comparison status of every channel |
|
03Ch |
R/W |
Software channel list 0, to define the analog channels to own channel list |
|
040h |
R/W |
Software channel list 1, refer to REG_ADC_CHSW_LIST_0 |
|
048h |
R/W |
Automatic switch channel function |
|
04Ch |
R/W |
Software controls to trigger the channel switch |
|
050h |
R |
The register records the last channel |
|
054h |
R |
The register reflects the ADC FSM and fifo status |
|
058h |
R/W |
The register to enable or disable the different kinds of interrupts |
|
05Ch |
R |
The register to record the different kinds of interrupt raw status(bypass the enable register’s control) |
|
060h |
R/W |
The register to record the different kinds of interrupt status |
|
064h |
R/W |
The specific channel to trigger interrupt |
|
068h |
R/W |
The fifo full threshold |
|
06Ch |
R/W |
The register to select the specific external timer source |
|
070h |
R |
The register to store the channel data , ready and overwritten information |
|
074h |
R |
Refer to REG_ADC_DATA_CH0 |
|
078h |
R |
Refer to REG_ADC_DATA_CH0 |
|
07Ch |
R |
Refer to REG_ADC_DATA_CH0 |
|
080h |
R |
Refer to REG_ADC_DATA_CH0 |
|
084h |
R |
Refer to REG_ADC_DATA_CH0 |
|
088h |
R |
Refer to REG_ADC_DATA_CH0 |
|
08Ch |
R |
Refer to REG_ADC_DATA_CH0 |
|
090h |
R |
Refer to REG_ADC_DATA_CH0 |
|
094h |
R |
Refer to REG_ADC_DATA_CH0 |
|
098h |
R |
Refer to REG_ADC_DATA_CH0 |
|
09Ch |
R |
Register to store global data, ready , channel and overwritten information |
|
0A0h |
R |
Register to store fifo entry number |
|
0A4h |
R/W |
Register to clear fifo |
|
0A8h |
R/W |
Register to control clock dividend and channel unmask |
|
0ACh |
R/W |
Register to configure ADC over sample |
|
0B0h |
R/W |
Register to control the ADC power and debug configuration |
|
0B4h |
R/W |
Register to set the software test mode |
|
0B8h |
R/W |
||
0BCh |
R/W |
||
0C0h |
R/W |
||
0C4h |
R/W |
||
0C8h |
R/W |
||
0CCh |
R/W |
||
0D0h |
R/W |
||
0D4h |
R/W |
||
0D8h |
R/W |
||
0DCh |
R/W |
||
0E0h |
R/W |
||
0E4h |
R/W |
||
0E8h |
R/W |
||
0ECh |
R/W |
||
0F0h |
R/W |
||
0F4h |
R/W |
||
0F8h |
R/W |
||
0FCh |
R/W |
||
100h |
R/W |
Dummy register |
REG_ADC_CONF
Name: ADC Configuration Register
Size: 32
Address offset: 000h
Read/write access: R/W
Basic configuration of ADC including enable and operation mode
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:10 |
RSVD |
R |
- |
Reserved |
9 |
BIT_ADC_ENABLE |
R/W |
0h |
This bit is for ADC enable control |
8 |
RSVD |
R |
- |
Reserved |
7:4 |
BIT_ADC_CVLIST_LEN |
R/W |
0h |
This field defines the number of items in the ADC conversion channel list. |
3:1 |
BIT_ADC_OP_MOD |
R/W |
0h |
These bits selects ADC operation mode. 0: software trigger mode.
|
0 |
RSVD |
R |
- |
Reserved |
REG_ADC_IN_TYPE
Name: ADC Input Type Register
Size: 32
Address offset: 004h
Read/write access: R/W
Analog ADC input type configuration
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:11 |
RSVD |
R |
- |
Reserved |
10 |
BIT_ADC_IN_TYPE_CH10 |
R |
0 |
This bit reflects which kind of input type channel 10 is. Since channel 10 is a fixed internal channel. |
9 |
BIT_ADC_IN_TYPE_CH9 |
R |
0 |
This bit reflects which kind of input type channel 9 is. Since channel 9 is a fixed internal channel. |
8 |
BIT_ADC_IN_TYPE_CH8 |
R |
0 |
This bit reflects which kind of input type channel 8 is. Since channel 8 is a fixed internal channel. |
7 |
BIT_ADC_IN_TYPE_CH7 |
R/W |
0 |
This bit controls channel 7 input type. If it’s set to differential type(value of this bit is 1), channel 6 should also be set to differential type since they are hardware-fixed differential pair.
|
6 |
BIT_ADC_IN_TYPE_CH6 |
R/W |
0 |
This bit controls channel 6 input type. If it’s set to differential type(value of this bit is 1), channel 5 should also be set to differential type since they are hardware-fixed differential pair.
|
5 |
BIT_ADC_IN_TYPE_CH5 |
R/W |
0 |
This bit controls channel 5 input type. If it’s set to differential type(value of this bit is 1), channel 4 should also be set to differential type since they are hardware-fixed differential pair.
|
4 |
BIT_ADC_IN_TYPE_CH4 |
R/W |
0 |
This bit controls channel 4 input type. If it’s set to differential type(value of this bit is 1), channel 5 should also be set to differential type since they are hardware-fixed differential pair.
|
3 |
BIT_ADC_IN_TYPE_CH3 |
R/W |
0 |
This bit controls channel 3 input type. If it’s set to differential type(value of this bit is 1), channel 2 should also be set to differential type since they are hardware-fixed differential pair.
|
2 |
BIT_ADC_IN_TYPE_CH2 |
R/W |
0 |
This bit controls channel 2 input type. If it’s set to differential type(value of this bit is 1), channel 3 should also be set to differential type since they are hardware-fixed differential pair.
|
1 |
BIT_ADC_IN_TYPE_CH1 |
R/W |
0 |
This bit controls channel 1 input type. If it’s set to differential type(value of this bit is 1), channel 0 should also be set to differential type since they are hardware-fixed differential pair.
|
0 |
BIT_ADC_IN_TYPE_CH0 |
R/W |
0 |
This bit controls channel 0 input type. If it’s set to differential type(value of this bit is 1), channel 1 should also be set to differential type since they are hardware-fixed differential pair.
|
REG_ADC_COMP_TH_CH0
Name: ADC Channel 0 Comparison Threshold Register
Size: 32
Address offset: 008h
Read/write access: R/W
Channel comparison threshold
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CH0 |
R/W |
0h |
This field defines the higher threshold of channel 0 for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CH0 |
R/W |
0h |
This field defines the lower threshold of channel 0 for ADC automatic comparison. |
REG_ADC_COMP_TH_CH1
Name: ADC Channel 1 Comparison Threshold Register
Size: 32
Address offset: 00Ch
Read/write access: R/W
Refer to REG_ADC_COMP_TH_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CH1 |
R/W |
0h |
This field defines the higher threshold of channel 1 for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CH1 |
R/W |
0h |
This field defines the lower threshold of channel 1 for ADC automatic comparison. |
REG_ADC_COMP_TH_CH2
Name: ADC Channel 2 Comparison Threshold Register
Size: 32
Address offset: 010h
Read/write access: R/W
Refer to REG_ADC_COMP_TH_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CH2 |
R/W |
0h |
This field defines the higher threshold of channel 2 for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CH2 |
R/W |
0h |
This field defines the lower threshold of channel 2 for ADC automatic comparison. |
REG_ADC_COMP_TH_CH3
Name: ADC Channel 3 Comparison Threshold Register
Size: 32
Address offset: 014h
Read/write access: R/W
Refer to REG_ADC_COMP_TH_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CH3 |
R/W |
0h |
This field defines the higher threshold of channel 3 for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CH3 |
R/W |
0h |
This field defines the lower threshold of channel 3 for ADC automatic comparison. |
REG_ADC_COMP_TH_CH4
Name: ADC Channel 4 Comparison Threshold Register
Size: 32
Address offset: 018h
Read/write access: R/W
Refer to REG_ADC_COMP_TH_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CH4 |
R/W |
0h |
This field defines the higher threshold of channel 4 for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CH4 |
R/W |
0h |
This field defines the lower threshold of channel 4 for ADC automatic comparison. |
REG_ADC_COMP_TH_CH5
Name: ADC Channel 5 Comparison Threshold Register
Size: 32
Address offset: 01Ch
Read/write access: R/W
Refer to REG_ADC_COMP_TH_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CH5 |
R/W |
0h |
This field defines the higher threshold of channel 5 for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CH5 |
R/W |
0h |
This field defines the lower threshold of channel 5 for ADC automatic comparison. |
REG_ADC_COMP_TH_CH6
Name: ADC Channel 6 Comparison Threshold Register
Size: 32
Address offset: 020h
Read/write access: R/W
Refer to REG_ADC_COMP_TH_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CH6 |
R/W |
0h |
This field defines the higher threshold of channel 6 for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CH6 |
R/W |
0h |
This field defines the lower threshold of channel 6 for ADC automatic comparison. |
REG_ADC_COMP_TH_CH7
Name: ADC Channel 7 Comparison Threshold Register
Size: 32
Address offset: 024h
Read/write access: R/W
Refer to REG_ADC_COMP_TH_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CH7 |
R/W |
0h |
This field defines the higher threshold of channel 7 for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CH7 |
R/W |
0h |
This field defines the lower threshold of channel 7 for ADC automatic comparison. |
REG_ADC_COMP_TH_CH8
Name: ADC Channel 8 Comparison Threshold Register
Size: 32
Address offset: 028h
Read/write access: R/W
Refer to REG_ADC_COMP_TH_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CH8 |
R/W |
0h |
This field defines the higher threshold of channel 8 for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CH8 |
R/W |
0h |
This field defines the lower threshold of channel 8 for ADC automatic comparison. |
REG_ADC_COMP_TH_CH9
Name: ADC Channel 9 Comparison Threshold Register
Size: 32
Address offset: 02Ch
Read/write access: R/W
Refer to REG_ADC_COMP_TH_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CH9 |
R/W |
0h |
This field defines the higher threshold of channel 9 for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CH9 |
R/W |
0h |
This field defines the lower threshold of channel 9 for ADC automatic comparison. |
REG_ADC_COMP_TH_CH10
Name: ADC Channel 10 Comparison Threshold Register
Size: 32
Address offset: 030h
Read/write access: R/W
Refer to REG_ADC_COMP_TH_CH10
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
BIT_ADC_COMP_TH_H_CH10 |
R/W |
0h |
This field defines the higher threshold of channel 10 for ADC automatic comparison. |
15:0 |
BIT_ADC_COMP_TH_L_CH10 |
R/W |
0h |
This field defines the lower threshold of channel 10 for ADC automatic comparison. |
REG_ADC_COMP_CTRL
Name: ADC Comparison Control Register
Size: 32
Address offset: 034h
Read/write access: R/W
Channel comparison criterion control register, can be used to control every channel’s comparison
criterion. There are 3 kinds of criterions.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21:20 |
BIT_ADC_COMP_CTRL_CH10 |
R/W |
0h |
This field defines ADC channel comparison criteria which would notify system by interrupt when the criterion matches. Once a criterion matches, ADC should send an interrupt signal to system if the related interrupt mask is unmask. ADC also updates comparison results in reg_adc_comp_sts.
|
19:18 |
BIT_ADC_COMP_CTRL_CH9 |
R/W |
0h |
The function is same as bit_adc_comp_ctrl_ch10 |
17:16 |
BIT_ADC_COMP_CTRL_CH8 |
R/W |
0h |
The function is same as bit_adc_comp_ctrl_ch10 |
15:14 |
BIT_ADC_COMP_CTRL_CH7 |
R/W |
0h |
The function is same as bit_adc_comp_ctrl_ch10 |
13:12 |
BIT_ADC_COMP_CTRL_CH6 |
R/W |
0h |
The function is same as bit_adc_comp_ctrl_ch10 |
11:10 |
BIT_ADC_COMP_CTRL_CH5 |
R/W |
0h |
The function is same as bit_adc_comp_ctrl_ch10 |
9:8 |
BIT_ADC_COMP_CTRL_CH4 |
R/W |
0h |
The function is same as bit_adc_comp_ctrl_ch10 |
7:6 |
BIT_ADC_COMP_CTRL_CH3 |
R/W |
0h |
The function is same as bit_adc_comp_ctrl_ch10 |
5:4 |
BIT_ADC_COMP_CTRL_CH2 |
R/W |
0h |
The function is same as bit_adc_comp_ctrl_ch10 |
3:2 |
BIT_ADC_COMP_CTRL_CH1 |
R/W |
0h |
The function is same as bit_adc_comp_ctrl_ch10 |
1:0 |
BIT_ADC_COMP_CTRL_CH0 |
R/W |
0h |
The function is same as bit_adc_comp_ctrl_ch10 |
REG_ADC_COMP_STS
Name: ADC Comparison Status Register
Size: 32
Address offset: 038h
Read/write access: R
The comparison status of every channel
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21:20 |
BIT_ADC_COMP_STS_CH10 |
R |
0h |
This field reflects the comparison result of channel 10 immediately |
19:18 |
BIT_ADC_COMP_STS_CH9 |
R |
0h |
This field reflects the comparison result of channel 9 immediately |
17:16 |
BIT_ADC_COMP_STS_CH8 |
R |
0h |
This field reflects the comparison result of channel 8 immediately |
15:14 |
BIT_ADC_COMP_STS_CH7 |
R |
0h |
This field reflects the comparison result of channel 7 immediately |
13:12 |
BIT_ADC_COMP_STS_CH6 |
R |
0h |
This field reflects the comparison result of channel 6 immediately |
11:10 |
BIT_ADC_COMP_STS_CH5 |
R |
0h |
This field reflects the comparison result of channel 5 immediately |
9:8 |
BIT_ADC_COMP_STS_CH4 |
R |
0h |
This field reflects the comparison result of channel 4 immediately |
7:6 |
BIT_ADC_COMP_STS_CH3 |
R |
0h |
This field reflects the comparison result of channel 3 immediately |
5:4 |
BIT_ADC_COMP_STS_CH2 |
R |
0h |
This field reflects the comparison result of channel 2 immediately |
3:2 |
BIT_ADC_COMP_STS_CH1 |
R |
0h |
This field reflects the comparison result of channel 1 immediately |
1:0 |
BIT_ADC_COMP_STS_CH0 |
R |
0h |
This field reflects the comparison result of channel 0 immediately |
REG_ADC_CHSW_LIST_0
Name: ADC Channel Switch List 0 Register
Size: 32
Address offset: 03Ch
Read/write access: R/W
Software channel list 0, to define the analog channels to own channel list
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:28 |
BIT_ADC_CHSW_7 |
R/W |
0h |
This field defines the number 7 channel to do a conversion when a conversion event takes place. |
27:24 |
BIT_ADC_CHSW_6 |
R/W |
0h |
This field defines the number 6 channel to do a conversion when a conversion event takes place. |
23:20 |
BIT_ADC_CHSW_5 |
R/W |
0h |
This field defines the number 5 channel to do a conversion when a conversion event takes place. |
19:16 |
BIT_ADC_CHSW_4 |
R/W |
0h |
This field defines the number 4 channel to do a conversion when a conversion event takes place. |
15:12 |
BIT_ADC_CHSW_3 |
R/W |
0h |
This field defines the number 3 channel to do a conversion when a conversion event takes place. |
11:8 |
BIT_ADC_CHSW_2 |
R/W |
0h |
This field defines the number 2 channel to do a conversion when a conversion event takes place. |
7:4 |
BIT_ADC_CHSW_1 |
R/W |
0h |
This field defines the number 1 channel to do a conversion when a conversion event takes place. |
3:0 |
BIT_ADC_CHSW_0 |
R/W |
0h |
This field defines the number 0 channel to do a conversion when a conversion event takes place. |
REG_ADC_CHSW_LIST_1
Name: ADC Channel Switch List 1 Register
Size: 32
Address offset: 040h
Read/write access: R/W
Software channel list 1, refer to REG_ADC_CHSW_LIST_0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:28 |
BIT_ADC_CHSW_15 |
R/W |
0h |
This field defines the number 15 channel to do a conversion when a conversion event takes place. |
27:24 |
BIT_ADC_CHSW_14 |
R/W |
0h |
This field defines the number 14 channel to do a conversion when a conversion event takes place. |
23:20 |
BIT_ADC_CHSW_13 |
R/W |
0h |
This field defines the number 13 channel to do a conversion when a conversion event takes place. |
19:16 |
BIT_ADC_CHSW_12 |
R/W |
0h |
This field defines the number 12 channel to do a conversion when a conversion event takes place. |
15:12 |
BIT_ADC_CHSW_11 |
R/W |
0h |
This field defines the number 11 channel to do a conversion when a conversion event takes place. |
11:8 |
BIT_ADC_CHSW_10 |
R/W |
0h |
This field defines the number 10 channel to do a conversion when a conversion event takes place. |
7:4 |
BIT_ADC_CHSW_9 |
R/W |
0h |
This field defines the number 9 channel to do a conversion when a conversion event takes place. |
3:0 |
BIT_ADC_CHSW_8 |
R/W |
0h |
This field defines the number 8 channel to do a conversion when a conversion event takes place. |
REG_ADC_AUTO_CSW_CTRL
Name: ADC Automatic Channel Switch Control Register
Size: 32
Address offset: 048h
Read/write access: R/W
Automatic switch channel function
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_AUTOSW_EN |
R/W |
0h |
This bit controls the automatic channel switch enabled or disabled.
|
REG_ADC_SW_TRIG
Name: ADC Software Trigger Register
Size: 32
Address offset: 04Ch
Read/write access: R/W
Software controls to trigger the channel switch
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_SW_TRIG |
R/W |
0h |
This bit controls the ADC module to do a conversion. Every time this bit is set to 1, ADC module would switch to a new channel and do one conversion. Therefore, this bit could be used as a start-convert event which is controlled by software. Every time a conversion is done, software MUST clear this bit manually. The interval between clearing and restart this bit must exceed one sample clock period.
|
REG_ADC_LAST_CH
Name: ADC Last Channel Register
Size: 32
Address offset: 050h
Read/write access: R
The register records the last channel
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
- |
Reserved |
3:0 |
BIT_ADC_LAST_CH |
R |
0h |
This field reflects the last used channel |
REG_ADC_BUSY_STS
Name: ADC Busy Status Register
Size: 32
Address offset: 054h
Read/write access: R
The register reflects the ADC FSM and fifo status
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
- |
Reserved |
2 |
BIT_ADC_FIFO_EMPTY |
R |
1 |
|
1 |
BIT_ADC_FIFO_FULL_REAL |
R |
0 |
|
0 |
BIT_ADC_BUSY_STS |
R |
0 |
This bit reflects the ADC is busy or not. If the ADC is processing a conversion of a channel, this bit remains 1 which indicates it’s busy. Once a conversion is done, this bit becomes 0 which indicates it’s ready to do another conversion.
|
REG_ADC_INTR_CTRL
Name: ADC Interrupt Control Register
Size: 32
Address offset: 058h
Read/write access: R/W
The register to enable or disable the different kinds of interrupts
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31 |
BIT_ADC_IT_COMP_DET_MOD |
R/W |
0h |
This bit controls the interrupt bit_adc_it_comp_chx operation. comparison criterion matching is rising edge.
|
30:19 |
RSVD |
R |
- |
Reserved |
18 |
BIT_ADC_IT_COMP_CH10_EN |
R/W |
0h |
The function is same as bit_adc_it_comp_ch0_en |
17 |
BIT_ADC_IT_COMP_CH9_EN |
R/W |
0h |
The function is same as bit_adc_it_comp_ch0_en |
16 |
BIT_ADC_IT_COMP_CH8_EN |
R/W |
0h |
The function is same as bit_adc_it_comp_ch0_en |
15 |
BIT_ADC_IT_COMP_CH7_EN |
R/W |
0h |
The function is same as bit_adc_it_comp_ch0_en |
14 |
BIT_ADC_IT_COMP_CH6_EN |
R/W |
0h |
The function is same as bit_adc_it_comp_ch0_en |
13 |
BIT_ADC_IT_COMP_CH5_EN |
R/W |
0h |
The function is same as bit_adc_it_comp_ch0_en |
12 |
BIT_ADC_IT_COMP_CH4_EN |
R/W |
0h |
The function is same as bit_adc_it_comp_ch0_en |
11 |
BIT_ADC_IT_COMP_CH3_EN |
R/W |
0h |
The function is same as bit_adc_it_comp_ch0_en |
10 |
BIT_ADC_IT_COMP_CH2_EN |
R/W |
0h |
The function is same as bit_adc_it_comp_ch0_en |
9 |
BIT_ADC_IT_COMP_CH1_EN |
R/W |
0h |
The function is same as bit_adc_it_comp_ch0_en |
8 |
BIT_ADC_IT_COMP_CH0_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when channel 0 comparison criterion matches.
|
7 |
BIT_ADC_IT_ERR_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when an error state takes place.
|
6 |
BIT_ADC_IT_DAT_OVW_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a data overwritten situation takes place.
|
5 |
BIT_ADC_IT_FIFO_EMPTY_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO empty state takes place.
|
4 |
BIT_ADC_IT_FIFO_OVER_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO overflow state takes place.
|
3 |
BIT_ADC_IT_FIFO_FULL_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a FIFO full state takes place.
|
2 |
BIT_ADC_IT_CHCV_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a particular channel conversion is done. Please refer to reg_adc_it_chno_con
|
1 |
BIT_ADC_IT_CV_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not every time a conversion is done. No matter ADC module is in what kind of operation mode. Every time a conversion is executed, ADC module would notify system if This bit is set.
|
0 |
BIT_ADC_IT_CVLIST_END_EN |
R/W |
0h |
This bit controls the interrupt is enabled or not when a conversion of the last channel in the list is done. For example, in automatic mode conversions would be executed continuously. Every time the last channel conversion is done, which means all channel conversions in the list is done, ADC could notify system if This bit is set.
|
REG_ADC_INTR_RAW_STS
Name: ADC Interrupt Raw Status Register
Size: 32
Address offset: 05Ch
Read/write access: R
The register to record the different kinds of interrupt raw status(bypass the enable register’s
control)
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:19 |
RSVD |
R |
- |
Reserved |
18 |
BIT_ADC_IT_COMP_CH10_RAW_STS |
R |
0h |
|
17 |
BIT_ADC_IT_COMP_CH9_RAW_STS |
R |
0h |
Merged |
16 |
BIT_ADC_IT_COMP_CH8_RAW_STS |
R |
0h |
Merged |
15 |
BIT_ADC_IT_COMP_CH7_RAW_STS |
R |
0h |
Merged |
14 |
BIT_ADC_IT_COMP_CH6_RAW_STS |
R |
0h |
Merged |
13 |
BIT_ADC_IT_COMP_CH5_RAW_STS |
R |
0h |
Merged |
12 |
BIT_ADC_IT_COMP_CH4_RAW_STS |
R |
0h |
Merged |
11 |
BIT_ADC_IT_COMP_CH3_RAW_STS |
R |
0h |
Merged |
10 |
BIT_ADC_IT_COMP_CH2_RAW_STS |
R |
0h |
Merged |
9 |
BIT_ADC_IT_COMP_CH1_RAW_STS |
R |
0h |
Merged |
8 |
BIT_ADC_IT_COMP_CH0_RAW_STS |
R |
0h |
Merged |
7 |
BIT_ADC_IT_ERR_RAW_STS |
R |
0h |
Merged |
6 |
BIT_ADC_IT_DAT_OVW_RAW_STS |
R |
0h |
Merged |
5 |
BIT_ADC_IT_FIFO_EMPTY_RAW_STS |
R |
1h |
Merged |
4 |
BIT_ADC_IT_FIFO_OVER_RAW_STS |
R |
0h |
Merged |
3 |
BIT_ADC_IT_FIFO_FULL_RAW_STS |
R |
0h |
Merged |
2 |
BIT_ADC_IT_CHCV_END_RAW_STS |
R |
0h |
Merged |
1 |
BIT_ADC_IT_CV_END_RAW_STS |
R |
0h |
Merged |
0 |
BIT_ADC_IT_CVLIST_END_RAW_STS |
R |
0h |
Merged |
REG_ADC_INTR_STS
Name: ADC Interrupt Status Register
Size: 32
Address offset: 060h
Read/write access: R/W
The register to record the different kinds of interrupt status
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:19 |
RSVD |
R |
- |
Reserved |
18 |
BIT_ADC_IT_COMP_CH10_STS |
R/W |
0h |
|
17 |
BIT_ADC_IT_COMP_CH9_STS |
R/W |
0h |
Merged |
16 |
BIT_ADC_IT_COMP_CH8_STS |
R/W |
0h |
Merged |
15 |
BIT_ADC_IT_COMP_CH7_STS |
R/W |
0h |
Merged |
14 |
BIT_ADC_IT_COMP_CH6_STS |
R/W |
0h |
Merged |
13 |
BIT_ADC_IT_COMP_CH5_STS |
R/W |
0h |
Merged |
12 |
BIT_ADC_IT_COMP_CH4_STS |
R/W |
0h |
Merged |
11 |
BIT_ADC_IT_COMP_CH3_STS |
R/W |
0h |
Merged |
10 |
BIT_ADC_IT_COMP_CH2_STS |
R/W |
0h |
Merged |
9 |
BIT_ADC_IT_COMP_CH1_STS |
R/W |
0h |
Merged |
8 |
BIT_ADC_IT_COMP_CH0_STS |
R/W |
0h |
Merged |
7 |
BIT_ADC_IT_ERR_STS |
R/W |
0h |
Merged |
6 |
BIT_ADC_IT_DAT_OVW_STS |
R/W |
0h |
Merged |
5 |
BIT_ADC_IT_FIFO_EMPTY_STS |
R/W |
0h |
Merged |
4 |
BIT_ADC_IT_FIFO_OVER_STS |
R/W |
0h |
Merged |
3 |
BIT_ADC_IT_FIFO_FULL_STS |
R/W |
0h |
Merged |
2 |
BIT_ADC_IT_CHCV_END_STS |
R/W |
0h |
Merged |
1 |
BIT_ADC_IT_CV_END_STS |
R/W |
0h |
Merged |
0 |
BIT_ADC_IT_CVLIST_END_STS |
R/W |
0h |
Merged |
REG_ADC_IT_CHNO_CON
Name: ADC Interrupt Channel Number Configuration Register
Size: 32
Address offset: 064h
Read/write access: R/W
The specific channel to trigger interrupt
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
- |
Reserved |
3:0 |
BIT_ADC_IT_CHNO_CON |
R/W |
0h |
This field defines that ADC module should send interrupt signal to system when a conversion which of channel number is the same as this field. This register is only valid when bit_adc_it_chcv_end_en is set. Bit_adc_it_chno_con: channel number |
REG_ADC_FULL_LVL
Name: ADC FIFO Full Threshold Register
Size: 32
Address offset: 068h
Read/write access: R/W
The fifo full threshold
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:6 |
RSVD |
R |
- |
Reserved |
5:0 |
BIT_ADC_FULL_LVL |
R/W |
0h |
This field defines the FIFO full entry thredshold level and it’s used for FIFO full interrupt. It should be set according to ADC FIFO depth. A value of 0 sets the threshold for 1 entry, and a value of 15 sets the threshold for 16 entries. |
REG_ADC_EXT_TRIG_TIMER_SEL
Name: ADC External Trigger Timer Select Register
Size: 32
Address offset: 06Ch
Read/write access: R/W
The register to select the specific external timer source
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
- |
Reserved |
2:0 |
BIT_ADC_EXT_TRIG_TIMER_SEL |
R/W |
0h |
These three bits defines which timer channel would be used to make ADC module do a conversion.
|
REG_ADC_DATA_CH0
Name: ADC Channel 0 Data Register
Size: 32
Address offset: 070h
Read/write access: R
The register to store the channel data , ready and overwritten information
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CH0 |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_ch0. |
20 |
BIT_ADC_DAT_OVW_CH0 |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_ch0.
|
19:16 |
BIT_ADC_NUM_CH0 |
R |
0 |
This field contains the newsest conversion data of channel 0 [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CH0 |
R |
0 |
This field contains the newsest conversion data of channel 0 [15:0]: newest data |
REG_ADC_DATA_CH1
Name: ADC Channel 1 Data Register
Size: 32
Address offset: 074h
Read/write access: R
Refer to REG_ADC_DATA_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CH1 |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_ch1. |
20 |
BIT_ADC_DAT_OVW_CH1 |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_ch1.
|
19:16 |
BIT_ADC_NUM_CH1 |
R |
0 |
This field contains the newsest conversion data of channel 1 [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CH1 |
R |
0 |
This field contains the newsest conversion data of channel 1 [15:0]: newest data |
REG_ADC_DATA_CH2
Name: ADC Channel 2 Data Register
Size: 32
Address offset: 078h
Read/write access: R
Refer to REG_ADC_DATA_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CH2 |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_ch2. |
20 |
BIT_ADC_DAT_OVW_CH2 |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_ch2.
|
19:16 |
BIT_ADC_NUM_CH2 |
R |
0 |
This field contains the newsest conversion data of channel 2 [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CH2 |
R |
0 |
This field contains the newsest conversion data of channel 2 [15:0]: newest data |
REG_ADC_DATA_CH3
Name: ADC Channel 3 Data Register
Size: 32
Address offset: 07Ch
Read/write access: R
Refer to REG_ADC_DATA_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CH3 |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_ch3. |
20 |
BIT_ADC_DAT_OVW_CH3 |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_ch3.
|
19:16 |
BIT_ADC_NUM_CH3 |
R |
0 |
This field contains the newsest conversion data of channel 3 [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CH3 |
R |
0 |
This field contains the newsest conversion data of channel 3 [15:0]: newest data |
REG_ADC_DATA_CH4
Name: ADC Channel 4 Data Register
Size: 32
Address offset: 080h
Read/write access: R
Refer to REG_ADC_DATA_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CH4 |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_ch4. |
20 |
BIT_ADC_DAT_OVW_CH4 |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_ch4.
|
19:16 |
BIT_ADC_NUM_CH4 |
R |
0 |
This field contains the newsest conversion data of channel 4 [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CH4 |
R |
0 |
This field contains the newsest conversion data of channel 4 [15:0]: newest data |
REG_ADC_DATA_CH5
Name: ADC Channel 5 Data Register
Size: 32
Address offset: 084h
Read/write access: R
Refer to REG_ADC_DATA_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CH5 |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_ch5. |
20 |
BIT_ADC_DAT_OVW_CH5 |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_ch5.
|
19:16 |
BIT_ADC_NUM_CH5 |
R |
0 |
This field contains the newsest conversion data of channel 5 [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CH5 |
R |
0 |
This field contains the newsest conversion data of channel 5 [15:0]: newest data |
REG_ADC_DATA_CH6
Name: ADC Channel 6 Data Register
Size: 32
Address offset: 088h
Read/write access: R
Refer to REG_ADC_DATA_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CH6 |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_ch6. |
20 |
BIT_ADC_DAT_OVW_CH6 |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_ch6.
|
19:16 |
BIT_ADC_NUM_CH6 |
R |
0 |
This field contains the newsest conversion data of channel 6 [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CH6 |
R |
0 |
This field contains the newsest conversion data of channel 6 [15:0]: newest data |
REG_ADC_DATA_CH7
Name: ADC Channel 7 Data Register
Size: 32
Address offset: 08Ch
Read/write access: R
Refer to REG_ADC_DATA_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CH7 |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_ch7. |
20 |
BIT_ADC_DAT_OVW_CH7 |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_ch7.
|
19:16 |
BIT_ADC_NUM_CH7 |
R |
0 |
This field contains the newsest conversion data of channel 7 [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CH7 |
R |
0 |
This field contains the newsest conversion data of channel 7 [15:0]: newest data |
REG_ADC_DATA_CH8
Name: ADC Channel 8 Data Register
Size: 32
Address offset: 090h
Read/write access: R
Refer to REG_ADC_DATA_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CH8 |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_ch8. |
20 |
BIT_ADC_DAT_OVW_CH8 |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_ch8.
|
19:16 |
BIT_ADC_NUM_CH8 |
R |
0 |
This field contains the newsest conversion data of channel 8 [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CH8 |
R |
0 |
This field contains the newsest conversion data of channel 8 [15:0]: newest data |
REG_ADC_DATA_CH9
Name: ADC Channel 9 Data Register
Size: 32
Address offset: 094h
Read/write access: R
Refer to REG_ADC_DATA_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CH9 |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_ch9. |
20 |
BIT_ADC_DAT_OVW_CH9 |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_ch9.
|
19:16 |
BIT_ADC_NUM_CH9 |
R |
0 |
This field contains the newsest conversion data of channel 9 [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CH9 |
R |
0 |
This field contains the newsest conversion data of channel 9 [15:0]: newest data |
REG_ADC_DATA_CH10
Name: ADC Channel 9 Data Register
Size: 32
Address offset: 098h
Read/write access: R
Refer to REG_ADC_DATA_CH0
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_CH10 |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_ch10. |
20 |
BIT_ADC_DAT_OVW_CH10 |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takeing place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field. It would be cleared to 0 when a read operation of reg_adc_data_ch10.
|
19:16 |
BIT_ADC_NUM_CH10 |
R |
0 |
This field contains the newsest conversion data of channel 10 [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_CH10 |
R |
0 |
This field contains the newsest conversion data of channel 10 [15:0]: newest data |
REG_ADC_DATA_GLOBAL
Name: ADC Global Data Register
Size: 32
Address offset: 09Ch
Read/write access: R
Register to store global data, ready , channel and overwritten information
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
- |
Reserved |
21 |
BIT_ADC_DAT_RDY_GLOBAL |
R |
0 |
This bit indicates that a conversion is done. Every time a conversion is done, this bit should be set to 1 and it would be cleared to 0 when a read operation of reg_adc_data_global |
20 |
BIT_ADC_DAT_OVW_GLOBAL |
R |
0 |
This bit indicates that there is a data overwritten situation in bit_adc_data_global takes place. A data overwritten situation is that a former conversion data is NOT read before a new conversion is written to data field.
|
19:16 |
BIT_ADC_CH_NUM_GLOBAL |
R |
0 |
This field contains the newsest conversion data of channel in the list. [19:16]: which channel in channel list the data belongs to, only valid when bit_adc_ch_unmask=1 |
15:0 |
BIT_ADC_DATA_GLOBAL |
R |
0 |
This field contains the newsest conversion data of channel in the list. [15:0]: newest data |
REG_ADC_FLR
Name: ADC FIFO Level Register
Size: 32
Address offset: 0A0h
Read/write access: R
Register to store fifo entry number
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:6 |
RSVD |
R |
- |
Reserved |
5:0 |
BIT_ADC_FLR |
R |
0 |
This field records the current ADC FIFO entry number. |
REG_ADC_CLR_FIFO
Name: ADC Clear FIFO Register
Size: 32
Address offset: 0A4h
Read/write access: R/W
Register to clear fifo
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_CLR_FIFO |
R/W |
0 |
This bit is used to clear FIFO contents and makes it to the default status. Every time this bit is set to 1. FIFO would be cleared to the default status. Software should set this bit to 0 after FIFO is cleared.
|
REG_ADC_SETTLE
Name: ADC Settle Register
Size: 32
Address offset: 0A8h
Read/write access: R/W
Register to control clock dividend and channel unmask
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:8 |
RSVD |
R |
- |
Reserved |
7:4 |
BIT_SETTLE_POW_ON |
R/W |
0h |
Settle count for sample data from power on , the unit is adc sample clock. 0 means no need to settle |
3:0 |
BIT_SETTLE_CTC_TO_ADC |
R/W |
0h |
Settle count for sample data from captouch to ADC, the unit is adc sample clock. 0 means no need to settle |
REG_ADC_OVERSAMPLE
Name: ADC Over Sample Register
Size: 32
Address offset: 0ACh
Read/write access: R/W
Register to configure ADC over sample
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:9 |
RSVD |
R |
- |
Reserved |
8:6 |
BIT_ADC_OSF |
R/W |
0 |
Oversampling right shift
|
5:3 |
BIT_ADC_OSR |
R/W |
0 |
Over sample ratio
|
2 |
RSVD |
R |
- |
Reserved |
1 |
BIT_OV_MODE |
R/W |
0 |
Oversample mode 1-All oversampling conversions done in regular sequence 0-All oversampling conversions done in staggered sequence |
0 |
BIT_ADC_OS_EN |
R/W |
0 |
Over sample enable 1-enable; 0-disable |
REG_ADC_PWR_CTRL
Name: ADC Power Control Register
Size: 32
Address offset: 0B0h
Read/write access: R/W
Register to control the ADC power and debug configuration
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:5 |
RSVD |
R |
- |
Reserved |
4 |
BIT_ADC_PWR_KEEP |
R/W |
0 |
Keep adc power on at all times. automatic adjustment resumes after shutdown.
|
3 |
BIT_ADC_DBG_EN |
R/W |
0 |
Debug port enable |
2:1 |
BIT_ADC_DBG_SEL |
R/W |
0 |
Debug port select |
0 |
BIT_ADC_PWR_CTRL |
R/W |
0 |
This field is used to power control |
REG_ADC_SW_TMODE
Name: ADC Software Test Mode
Size: 32
Address offset: 0B4h
Read/write access: R/W
Register to set the software test mode
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
BIT_ADC_SW_TMODE |
R/W |
0 |
This bit is used to change the high 4 bits in FIFO.
|
REG_ADC_CLK_HCNT0_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0B8h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT0 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt0+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT1_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0BCh
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT1 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt1+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT2_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0C0h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT2 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt2+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT3_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0C4h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT3 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt3+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT4_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0C8h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT4 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt4+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT5_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0CCh
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT5 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt5+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT6_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0D0h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT6 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt6+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT7_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0D4h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT7 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt7+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT8_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0D8h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT8 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt8+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT9_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0DCh
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT9 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt9+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT10_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0E0h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT10 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt10+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT11_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0E4h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT11 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt11+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT12_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0E8h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT12 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt12+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT13_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0ECh
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT13 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt13+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT14_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0F0h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT14 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt14+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_HCNT15_DIV
Name: ADC Channel Clock Divider Register
Size: 32
Address offset: 0F4h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
- |
Reserved |
11:0 |
BIT_ADC_CLK_HCNT15 |
R/W |
12’d21 |
This field defines clock driver high level of chn in ADC module. High level =( bit_adc_clk_hcnt15+1) * ip_clk period . hcnt11-13 is rsvd. |
REG_ADC_CLK_LCNT0_DIV
Name: ADC Clock Divider Register
Size: 32
Address offset: 0F8h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:6 |
RSVD |
R |
- |
Reserved |
5:0 |
BIT_ADC_CLK_LCNT |
R/W |
6’d2 |
This field defines clock driver lower level of chn in ADC module.when source clock is 4M, the duration of low level need >=2 for timing req.(>=0.5us) Lower level =bit_adc_clk_lcnt* ip_clk period |
REG_ADC_DUMMY_CNT
Name: ADC Dummy Cnt Register
Size: 32
Address offset: 0FCh
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:25 |
RSVD |
R |
- |
Reserved |
24:0 |
BIT_ADC_DUMMY_CHN_SCNT |
R/W |
0h |
Dummy channel time counter. in auto mode, adc share the dummy channel for captouch. this reg controls the time of dummy channel. |
REG_ADC_DUMMY
Name: ADC Dummy Register
Size: 32
Address offset: 100h
Read/write access: R/W
Dummy register
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DUMMY |
R/W |
ffffh |
Dummy register |
