Debug Timer

Overview

The debug timer is a high-precision wrap-around timer that automatically starts after the chip is powered up and begins continuous timing. It provides a unified high-precision time reference for all on-chip processors, ensuring time synchronization in multi-core scenarios. In addition, the debug timer is equipped with a software-triggered counter specifically designed to solve competition issues between cores, assisting in debugging timing conflicts and resource preemption during multi-core operation. It is a key component for chip multi-core debugging and timing calibration.

Features

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730ERTL8721F

• High-precision {{IC_PARAM_DEBUG_TIMER_WIDTH}} wrap-around timer

• 1μs timing precision, with each counter increment corresponding to a timing duration of 1 microsecond

• Automatically starts after power-up, no software configuration required for enablement

• A software-triggered counter

Functional Description

The high-precision wrap-around timer supports two types of clock input sources: external crystal (XTAL) or internal 32K clock. The two clock sources can be intelligently switched according to the system operating state. When the system is running normally, the high-precision crystal can be used to ensure timing accuracy; when the system enters sleep mode, the timer will automatically switch the clock source. Regardless of which clock source is used, the counter will automatically add 1 every 1us.

When the count value of the high-precision wrap-around timer reaches the maximum bit limit it supports, it will automatically wrap to 0 and start a new round of counting, achieving a cyclic counting effect without the need for manual zero reset. It should be noted that during the process of entering and exiting sleep mode, the clock source switching operation will cause a certain timing error to the timing operation. Therefore, in actual use of the timer, if it involves switching of sleep mode scenarios, the impact of this error must be considered in advance.

The high-precision wrap-around timer also supports configuration functions. Software can configure the counter start value as needed. After configuration, the counter

The software-triggered counter is mainly used to debug various timing issues in multi-core SoC chips, accurately locating timing deviations and resource arbitration exceptions during multi-core operation. Through software triggering, efficient arbitration control is implemented at the bus level, optimizing multi-core competition scheduling logic.

The counter has two independent read windows. Different read addresses correspond to different counting rules: if a read operation is performed from the DBGT_ATOM_INC address, the software-triggered counter value will automatically increase by one; if a read operation is performed from the DBGT_ATOM address, the counter value remains unchanged and will not increment. By distinguishing read addresses, the count trigger logic can be flexibly controlled to adapt to different multi-core debugging scenarios.

Registers

The following table lists the memory map of the debug timer registers.

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730ERTL8721F

Base Address: 0x41015000

Name	Address offset	Access	Description
REG_DBGT_CTRL	000h	R/W	This register contains the configuration of debug timer’s clock and enable signal.
REG_DBGT_CRV	004h	R/W
REG_DBGT_ATOM_INC	008h	R	Atom count adds 1.
REG_DBGT_ATOM	00Ch	R/W
REG_DBGT_SCRATCH	010h	R/W	This register is user-defined.
REG_DBGTIM_DUMMY	014h	R/W

REG_DBGT_CTRL

• Name: Debug Timer control register

• Size: 32

• Address offset: 000h

• Read/write access: R/W

This register contains the configuration of debug timer’s clock and enable signal.

Bit	Symbol	Access	INI	Description
31:1	RSVD	R	-	Reserved
0	ENABLE	R/W	1h	Debug timer enable. 1: The counter is enabled. 0: The counter is disabled.

REG_DBGT_CRV

• Name: Debug Timer count register

• Size: 32

• Address offset: 004h

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31:0	DBGT_CRV	R/W	0h	Continue to count from 0 once it’s reached 32’hFFFFFFFF.

REG_DBGT_ATOM_INC

• Name: Debug Timer atom read increase register

• Size: 32

• Address offset: 008h

• Read/write access: R

Atom count adds 1.

Bit	Symbol	Access	INI	Description
31:0	DBGT_ATOM_INC	R	0h	Each read will increase 1 and return to the increased value to bus.

REG_DBGT_ATOM

• Name: Debug Timer atom register

• Size: 32

• Address offset: 00Ch

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31:0	DBGT_ATOM	R/W	0h	Return the last increased value of atom counter.

REG_DBGT_SCRATCH

• Name: Debug Timer scratch register

• Size: 32

• Address offset: 010h

• Read/write access: R/W

This register is user-defined.

Bit	Symbol	Access	INI	Description
31:0	DBGT_SCRATCH	R/W	0h	Reserved

REG_DBGTIM_DUMMY

• Name: Debug Timer Dummy Register

• Size: 32

• Address offset: 014h

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31:0	DUMMY	R/W	ffffh	Dummy register