Debug Timer

Debug timer is a common timestamp for all debug messages originating from all on-die processors and processor execution domains (application, kernel, and firmware). It also includes a lock-free increment counter.

Features

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• Simple {{IC_PARAM_DEBUG_TIMER_WIDTH}} wrap timer

• A lock-free counter

Functional Description

The debug timer has two types of clock input: XTAL and internal 32K.

• When selecting XTAL with an internal divider, XTAL can generate a fixed 1us time interval between each time increments.

• When selecting 32K clock, the counter increases 31us every 30.5us.

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The counter can be enabled and disabled, by default it is enabled. The counter wraps around to zero and continues to count once it reaches {{IC_PARAM_DEBUG_TIMER_MAX_VALUE}}. A write to timestamp will set the current value of the timestamp, however, it must continue to increment at the base of the new setting value if the writing happens when the counter is active.

The XTAL clock may be gated in sleep mode. If you select XTAL as the clock source in sleep mode, the debug timer will stop counting, and all the registers will be maintained. The counter will resume the increment immediately after XTAL resumes. You can select 32K as the clock source in sleep mode; however, the counter itself needs 220us to do switch clock before continuing counting. In this period, writing to this IP is not allowed. All the registers will be reset to the initial values after wakeup from deepsleep mode.

The lock-free counter is a read trigger increase counter, can be used to debug timing issues in multicore SoC. Arbitration is implemented at the bus level. The counter has two read windows: read will trigger the counter increases one if reading from DBGT_ATOM_INC, and will not increase if reading from DBGT_ATOM.

The timestamp and atom should be reset to zero on the rising edge of the ENABLE bit (DBGT_CTRL [0]).

Registers

The following table lists the memory map of the debug timer registers.

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Base Address: 0x41015000

Name	Address offset	Access	Description
REG_DBGT_CTRL	000h	R/W	This register contains the configuration of debug timer’s clock and enable signal.
REG_DBGT_CRV	004h	R/W
REG_DBGT_ATOM_INC	008h	R	Atom count adds 1.
REG_DBGT_ATOM	00Ch	R/W
REG_DBGT_SCRATCH	010h	R/W	This register is user-defined.
REG_DBGTIM_DUMMY	014h	R/W

REG_DBGT_CTRL

• Name : Debug Timer control register

• Size : 32

• Address offset : 000h

• Read/write access : R/W

This register contains the configuration of debug timer’s clock and enable signal.

Bit	Symbol	Access	Reset	Description
31:1	RSVD	R	-	Reserved
0	ENABLE	R/W	1h	Debug timer enable. 1: The counter is enabled. 0: The counter is disabled.

REG_DBGT_CRV

• Name : Debug Timer count register

• Size : 32

• Address offset : 004h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:0	DBGT_CRV	R/W	0h	Continue to count from 0 once it’s reached 32’hFFFFFFFF.

REG_DBGT_ATOM_INC

• Name : Debug Timer atom read increase register

• Size : 32

• Address offset : 008h

• Read/write access : R

Atom count adds 1.

Bit	Symbol	Access	Reset	Description
31:0	DBGT_ATOM_INC	R	0h	Each read will increase 1 and return to the increased value to bus.

REG_DBGT_ATOM

• Name : Debug Timer atom register

• Size : 32

• Address offset : 00Ch

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:0	DBGT_ATOM	R/W	0h	Return the last increased value of atom counter.

REG_DBGT_SCRATCH

• Name : Debug Timer scratch register

• Size : 32

• Address offset : 010h

• Read/write access : R/W

This register is user-defined.

Bit	Symbol	Access	Reset	Description
31:0	DBGT_SCRATCH	R/W	0h	Reserved

REG_DBGTIM_DUMMY

• Name : Debug Timer Dummy Register

• Size : 32

• Address offset : 014h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:0	DUMMY	R/W	ffffh	Dummy register