Audio

Audio IC Feature Support Table

Function	RTL8721Dx	RTL8720E	RTL8726E	RTL8713E	RTL8730E	RTL8721F
I2S	Y	Y	Y	Y	Y	Y
AMIC	N	N	Y	Y	Y	N
DMIC	Y	Y	Y	Y	Y	Y
VAD	N	N	N	N	Y	N
PDM	N	Y	Y	Y	Y	N
LINEOUT	N	N	Y	Y	Y	N
HPO	N	N	N	N	Y	N

Introduction

The audio whole block diagram is illustrated below.

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Audio block consists of two parts:

• SPORT: 2x

  • SPORT0 is for internal digital microphone interface and external I2S interface

  • SPORT1 is only for external I2S interface.

• DMIC

SPORT

SPORT Data Path

The data paths of SPORT 0/1/2/3 are shown below respectively.

SPORT0 data path

SPORT1 data path

SPORT2 data path

SPORT3 data path

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Support SPORT0 and SPORT1.

SPORT Function

SPORT Feature

• General features

  • Supports up to 8-channel I2S transmitter

  • Supports 16/20/24/32 bits data length

  • Supports 16/20/24/32 bits channel length

  • Works in master and slave mode.

  • Supports sampling rate up to 192kHz

  • Support Multi-IO mode, fs up to 192kHz

• General functions

  • SPORT fs counter and phase counter

    • SPORT fs counter and phase counter under BCLK

      • When using phase counter, rx_bclk_div_ratio/ tx_bclk_div_ratio should be configured to 63.

      • Fs counter is used to count the number of LRCLK.

      • On every falling edge of LRCLK, phase counter would accumulate once in two BCLK cycles by default. On the next falling edge of LRCLK, phase counter will be reset to 0 and then start counting again. At this time, the maximum accumulated value of phase counter is 31.

      • Phase counter also can accumulate once in one BCLK cycle, the maximum accumulated value of phase counter is 63.

      • SPORT fs and phase counter is shown below:

      

    • SPORT fs counter and phase counter under SPORT CLK

      • SPORT CLK=98.304MHz/45.1584MHz. When the SPORT CLK is 98.304M, and on every rising edge or falling edge of LRCLK, the phase counter will accumulate once in one SPORT clock cycle, the accuracy of phase counter can reach 10ns.

      • Phase counter can start on the falling edge of LRCLK, and it increments by one at each SPORT CLK. On the next falling edge of LRCLK, phase counter will be reset to 0 and then start to count again.

      • Phase counter also can start on the rising edge of LRCLK, the rest is similar to the description above.

      • In master mode LRCLK is divided by SPORT CLK. In slave mode SPORT LRCLK is supported by master.

      • SPORT fs counter and phase counter under SPORT CLK is shown below:

      

      Note

      N = SPORT CLK/LRCLK

  • LRCLK start and stop detect: in slave mode, SPORT can use SPORT clock to monitor the start and stop of LRCLK.

    • Start condition: detect the rising edge or falling edge(default) of LRCLK. The implementation steps are as follows:

    

    • Stop condition: the phase counter is accumulated to a settable threshold. The implementation steps are as follows:

    

  • SPORT direct mode feature:

    • Used for data transmission between different sports without CPU and DMA involved in data transfer.

    • When two sports work in direct mode, clock needs to be at the same frequency.

  • SPORT FIFO:

    • TX_FIFO_0 and TX_FIFO_1 are two asynchronous ping-pong FIFO. Each FIFO is depth=32 and width=32, so 2*32*4 bytes=64 words.

    • RX_FIFO_0 and RX_FIFO_1 are two asynchronous ping-pong FIFO. Each FIFO is depth=32 and width=32, so 2*32*4 bytes=64 words.

    • 6/8 channels for data transmission, FIFO0 and FIFO1 would be used. Two FIFOs will request at the same time, and four SPORTs will produce 16 requests at the same time.

  • WIFI TSF

    • WIFI TSF start SPORT

      

      • MAC sends interrupt to audio, and hardware will automatically start playing in audio side. The hardware delay is tens of nanoseconds. There is no need to wait for software to set MAC to send interrupt to open the following two bit functions.

      ((u32)SP0_CTRL0) &= ~ SP_BIT_TX_DISABLE;
      ((u32)SP0_CTRL0) |= SP_BIT_START_TX;
      

    • WIFI TSF latch SPORT counter

      

      Hardware latch SPORT counter when it detects a change in the TSFT specified bit, software specifies the bits. The latch period is optional: 1.024/ 2.048/ 4.096 ……/ 131.072.

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

• SPORT0 is for internal digital microphone interface and external I2S interface

• SPORT1 is only for external I2S interface.

• Not support LRCLK start and stop detect

• Not support SPORT fs counter and phase counter under SPORT CLK

• Support WIFI TSF，but not support WIFI TSF start SPORT

I2S Signal Introduction

The I2S bus has three lines:

• Continuous serial clock (SCK/BCLK)

  • One SCK pulse generates a data bit

  • Master generates SCK

• Word select (WS/LRCLK)

  The word select line indicates the channel being transmitted:

  • WS = 0: channel 1 (left)

  • WS = 1: channel 2 (right)

  Changes one clock period before the MSB is transmitted

• Serial data (SD)

  SD is transmitted in two complements with the MSB first. The MSB has a fixed position, whereas the position of the LSB depends on the word length.

  When the system word length is greater than the transmitter word length, the word is truncated (the least significant data bits are set to 0).

  • If the receiver is sent more bits than its word length, the bits after the LSB are ignored.

  • If the receiver is sent fewer bits than its word length, the missing bits are set to zero internally.

I2S Data Format

The I2S interface supports I2S (Philips) format, Left-justified (MSB) format, Right-justified (LSB) format, PCM, and TDM mode. Software can select any mode by setting the I2S control register. The following figures show the I2S data format.

• I2S format

Note

• Typically, fs = 8/16/32/44.1/48/88.2/96/192/192kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK = Arbitrarily cycles within 1/fs, but >= 2*(N+1) * fs, <= 256 * fs

• Left-justified format

Note

• Typically, fs = 8/16/32/44.1/48/88.2/96/192/192kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 2*(N+1)*fs, <= 256 *fs

• PCM mode A

Note

• Typically, fs = 8/16/32/44.148/88.2/96/192kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 2*(N+1)*fs, <= 256 * fs

• PCM mode B

Note

• Typically, fs = 8/16/32/44.148/88.2/96/192kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 2*(N+1)*fs, <= 256 * fs

• I2S TDM 8 mode

Note

• Typically, fs = 8/16/32/44.1/48kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 8*(N+1)*fs, <= 256 * fs

• Left-justified TDM 8 mode

Note

• Typically, fs = 8/16/32/44.1/48kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 8*(N+1)*fs, <= 256 * fs

• PCM mode A in TDM 8 mode

Note

• Typically, fs = 8/16/32/44.1/48kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 8*(N+1)*fs, <= 256 * fs

• PCM mode B in TDM 8 mode

Note

• Typically, fs = 8/16/32/44.1/48kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 8*(N+1)*fs, <= 256 *fs

• I2S TDM 6 mode

Note

• Typically, fs = 8/16/32/44.1/48kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 6*(N+1)*fs, <= 256 * fs

• Left-justified TDM 6 mode

Note

• Typically, fs = 8/16/32/44.1/48kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 6*(N+1)*fs, <= 256 * fs

• PCM mode A in TDM 6 mode

Note

• Typically, fs = 8/16/32/44.1/48kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 6*(N+1)*fs, <= 256 * fs

• PCM mode B in TDM 6 mode

Note

• Typically, fs = 8/16/32/44.1/48kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 6*(N+1)*fs, <= 256 * fs

• I2S TDM 4 mode

Note

• Typically, fs = 8/16/32/44.1/48/88.2/96kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 4*(N+1)*fs, <= 256 * fs

• Left-justified TDM 4 mode

Note

• Typically, fs = 8/16/32/44.1/48/88.2/96kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 4*(N+1)*fs, <= 256 * fs

• PCM mode A in TDM 4 mode

Note

• Typically, fs = 8/16/32/44.1/48/88.2/96kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 4*(N+1)*fs, <= 256 * fs

• PCM mode B in TDM 4 mode

Note

• Typically, fs = 8/16/32/44.1/48/88.2/96kHz

• Channel length: 16/20/24/32 bits (N+1)

• SCK >= 4*(N+1)*fs, <= 256 * fs

I2S supports 16/20/24/32 bits channel length, the relationship between audio data length and channel length is illustrated below.

SPORT Parameters

SPORT parameters

Interface/Format	Sampling rate	Audio bits	Channel	Channel length	BCLK polarity	Serial data	Mode
I2S	192kHz	16 bits	Stereo	16 bits	BCLK	MSB first	Master
Left-justified	96kHz	20 bits	Mono	20 bits	BCLK inverse	LSB first	Slave
PCM Mode A (Short Frame Sync)	88.2kHz	24 bits		24 bits
PCM Mode A (Short Frame Sync)	48kHz	32 bits		32 bits
PCM Mode B (Short Frame Sync)	44.1kHz
PCM Mode B (Short Frame Sync)	32kHz
	16kHz
	8kHz

I2S PINMUX

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

The data PIN DIO[3:0] of I2S can be used as output or input. It can be set as input or output in the corresponding part of I2S in the PAD register. I2S data pinmux is shown below.

Audio Codec

General Description

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Audio codec provides 2-channel digital microphone for recording.

Features

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

DMIC interface features:

• 8kHz/11.025kHz/12kHz/16kHz/22.5kHz/24kHz/32kHz/44.1kHz/48kHz/88.2kHz/96kHz for digital microphone interface

• Asynchronous sample rate converter (ASRC) for each interface

• Configurable 0-5 band EQ

• Adjustable digital volume control

• For digital volume control, supports zero-crossing detection to minimize audible artifacts

• DC remove function

Audio Codec Data Path

Recording Data Path

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

The following figure shows the recording data path of digital microphone interface. In the recording path, the input source is 2-channel DMIC.

Playback Data Path

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Not support.

Audio Codec Functional Description

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Audio codec provides 2-channel digital microphone for recording.

Audio Recording

Audio Recording Block

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

The digital microphone (DMIC) interface is for digital microphone, and supports 2-channel digital microphone recording. The following figure shows the details block of digital microphone interface.

Digital Feature of Audio Recording

• Recording path for sampling rate 8k/11.025k/12k/16k/32k/22.05k/44.1k/48k/88.2k/96kHz

• ASRC (asynchronous sample rate converter)

• The ADC digital part supports digital volume control, and the gain is between 48dB and -17.625dB in 0.375dB per step.

• There is a high pass filter for DC offset

• Zero-crossing function

  • If the volume is adjusted while the signal is a non-zero value, an audible click can occur, as shown below.

  

  Click noise without zero crossing

  • In order to prevent this click noise, a zero-crossing function is provided. When enabled, this will cause the volume to update only when a zero crossing occurs, minimizing click noise, as shown below.

  

  Minimizing click noise with zero crossing

  • When the signal is very quiet and consists of mainly of noise, zero crossing cannot be met, now the gain will change with steps, as shown below.

  

  Gain update with steps as zero crossing

• Equalizer block

  The equalizer block cascades 0-5 bands of equalizer to tailor the frequency characteristics of the recording system according to user preferences and to emulate environment sound.

• DC remove function block

  A high pass filter is implemented for dc offset. The high pass filter is mainly for ADC recording used. The cut-off frequency of filter is programmable and is varied according to different sample rates. The filter is used to remove DC offset at normal conditions.

• Silence detector block

  The Silence detector is used to reduce the noise floor for DAC path or ADC path. When the input signal is below silence level, the input signal will be reduced to suppress the background noise. The reducing level can be set by registers.

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Audio Playback

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Not support.

Audio Playback Block

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Not support.

Digital Feature of Audio Playback

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Not support.

VAD_PITCH

VAD_PITCH Features

VAD (Voice Activity Detection) is a low-energy voice detect IP. It supports voice trigger. Once the VAD function is enabled, it will automatically sample the voice and detect the voice energy above the threshold value or not, even the processor is in sleep mode.

The overall design of VAD mainly includes two aspects, one is the generation of wake-up interrupt, to wake up the processor; the other is the transmission of voice data after wake-up, to let the processor timely access to audio data for keyword recognition.

VAD data source may be up to four analog microphones, and up to eight digital microphones. The VAD can configure software to choose which audio source to use as input. An APB configuration interface is also supported. When the VAD successfully recognizes a human voice in CPU low power mode, an interrupt is generated and reported to the CPU.

SRAM is used to store audio data buffer during power consumption. It is 128KB in size and supports 64 bits read/write. The data source is parallel to the VAD’s audio data source and is also audio data after the MUX.

At the same time, SRAM can also be read and written by KM0, KM4 and CA32 at workflow.

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

• Not support VAD_PITCH

Register

SPORT Register

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Base Address:

• SPORT0_REG : 0x4012A000

• SPORT1_REG : 0x4012B000

Name	Address offset	Access	Description
REG_SP_REG_MUX	000h	R/W
REG_SP_CTRL0	004h	R/W
REG_SP_CTRL1	008h	R/W
REG_SP_INT_CTRL	00Ch	R/W
REG_SP_TRX_COUNTER_STATUS	014h	R
REG_SP_ERR	018h	R
REG_SR_TX_BCLK	01Ch	R/W
REG_SP_TX_LRCLK	020h	R/W
REG_SP_FIFO_CTRL	024h	R
REG_SP_FORMAT	028h	R/W
REG_SP_RX_BCLK	02Ch	R/W
REG_SP_RX_LRCLK	030h	R/W
REG_SP_DSP_COUNTER	034h	R
REG_SP_DIRECT_CTRL0	03Ch	R/W
REG_SP_FIFO_IRQ	044h	R/W
REG_SP_DIRECT_CTRL1	048h	R/W
REG_SP_DIRECT_CTRL2	04Ch	R/W
REG_SP_DIRECT_CTRL3	054h	R/W
REG_SP_DIRECT_CTRL4	058h	R/W
REG_SP_RX_COUNTER1	05Ch	R/W
REG_SP_RX_COUNTER2	060h	R
REG_SP_MCLK	064h	R/W
REG_TX_FIFO_0_WR_ADDR	800h	R/W
REG_RX_FIFO_0_RD_ADDR	880h	R
REG_TX_FIFO_1_WR_ADDR	900h	R/W
REG_RX_FIFO_1_RD_ADDR	980h	R

REG_SP_REG_MUX

• Name : SPORT MUX Register

• Size : 32

• Address offset : 000h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:0	SP_REG_MUX	R/W	0xFFFFFFFF	Mux of register write with different base address of the sam e SPORT. This field can be set as different value with four different base address in one SPORT, but other registers share the sam e value with four different base address in one SPORT.

REG_SP_CTRL0

• Name : SPORT Control Register 0

• Size : 32

• Address offset : 004h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:30	MCLK_SEL	R/W	0x0	Not used, refer to 0x64 2’b00: MCLK output=dsp_src_clk/4 2’b01: MCLK output=dsp_src_clk/2 2’b10/2’b11: MCLK output=dsp_src_clk
29:28	SP_SEL_I2S_RX_CH	R/W	0x0	2’b00: L/R 2’b01: R/L 2’b10: L/L 2’b11: R/R x ADC path
27:26	SP_SEL_I2S_TX_CH	R/W	0x0	2’b00: L/R 2’b01: R/L 2’b10: L/L 2’b11: R/R x DAC path
25	SP_START_RX	R/W	0	1’b0: Rx is disabled 1’b1: Rx is started
24	SP_RX_DISABLE	R/W	1	1’b1: SPORT Rx is disabled. 1’b0: SPORT Rx is enabled.
23	RX_LSB_FIRST_0	R/W	0	1’b0: MSB first when Rx 1’b1: LSB first
22	TX_LSB_FIRST_0	R/W	0	1’b0: MSB first when Tx 1’b1: LSB first
21:20	SP_TDM_MODE_SEL_RX	R/W	0x0	2’b00: Without TDM 2’b01: TDM4 2’b10: TDM6 2’b11: TDM8
19:18	SP_TDM_MODE_SEL_TX	R/W	0x0	2’b00: Without TDM 2’b01: TDM4 2’b10: TDM6 2’b11: TDM8
17	SP_START_TX	R/W	0	1’b0: Tx is disabled. 1’b1: Tx is started.
16	SP_TX_DISABLE	R/W	1	1’b1: SPORT Tx is disabled. 1’b0: SPORT Tx is enabled.
15	SP_I2S_SELF_LPBK_EN	R/W	0	1’b1: internal loopback mode is enabled
14:12	SP_DATA_LEN_SEL_TX_0	R/W	0x0	3’b000: 16 bits 3’b001: 20 bits 3’b010: 24 bits 3’b100: 32 bits
11	SP_EN_I2S_MONO_TX_0	R/W	0	1’b1: mono 1’b0: stereo
10	SP_INV_I2S_SCLK	R/W	0	1’b1: I2S/PCM bit clock is inverted
9:8	SP_DATA_FORMAT_SEL_TX	R/W	0x0	2’b00: I2S 2’b01: Left-justified 2’b10: PCM mode A 2’b11: PCM mode B
7	DSP_CTL_MODE	R/W	0	1’b1: DSP and SPORT1 handshaking is enabled. 1’b0: GDMA and SPORT1 handshaking is enabled.
6	SP_LOOPBACK	R/W	0	1’b1: self-loopback mode
5	SP_WCLK_TX_INVERSE	R/W	0	1’b1: I2S/PCM word clock is inverted for Tx (SPK path)
4	SLAVE_DATA_SEL	R/W	0	1’b1: To be an I2S or PCM slave (data path)
3	SLAVE_CLK_SEL	R/W	0	1’b1: To be an I2S or PCM slave (CLK path)
2	RX_INV_I2S_SCLK	R/W	0	1’b1: sclk to Rx path (ADC path) is inverted
1	TX_INV_I2S_SCLK	R/W	0	1’b1: sclk to Tx path (DAC path) is inverted
0	SP_RESET	R/W	0	1’b1: reset SPORT1 module, and remember to write “1” to rese t and then write “0” to release from reset.

REG_SP_CTRL1

• Name : SPORT Control Register 1

• Size : 32

• Address offset : 008h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31	RX_FIFO_1_REG_1_EN	R/W	0	1’b1: Enable last two channels of RX_FIFO_1. Only enable whe n RX_FIFO_1_REG_1_EN = 1.
30	RX_FIFO_1_REG_0_EN	R/W	0	1’b1: Enable first two channels of RX_FIFO_1. Only enable wh en RX_FIFO_0_REG_0_EN = 1.
29	RX_FIFO_0_REG_1_EN	R/W	0	1’b1: Enable last two channels of RX_FIFO_0. Only enable whe n RX_FIFO_0_REG_0_EN = 1.
28	RX_FIFO_0_REG_0_EN	R/W	1	1’b1: Enable first two channels of RX_FIFO_0. Disable 0x0008 [28] ~ Disable 0x0008[31] at the same time to reset Rx FIFO.
27	TX_FIFO_1_REG_1_EN	R/W	0	1’b1: Enable last two channels of TX_FIFO_1. Only enable whe n TX_FIFO_1_REG_0_EN = 1.
26	TX_FIFO_1_REG_0_EN	R/W	0	1’b1: Enable first two channels of TX_FIFO_1. Only enable wh en TX_FIFO_0_REG_0_EN = 1.
25	TX_FIFO_0_REG_1_EN	R/W	0	1’b1: Enable last two channels of TX_FIFO_0. Only enable whe n TX_FIFO_0_REG_0_EN = 1.
24	TX_FIFO_0_REG_0_EN	R/W	1	1’b1: Enable first two channels of TX_FIFO_0. Disable 0x0008 [24] ~ Disable 0x0008[27] at the same time to reset Tx FIFO.
23	RX_SNK_LR_SWAP_0	R/W	0	1’b1: swap L/R audio samples written to the sink memory of R X_FIFO_0
22	RX_SNK_BYTE_SWAP_0	R/W	0	1’b1: swap H/L bytes written to the sink memory of RX_FIFO_0
21	TX_SRC_LR_SWAP_0	R/W	0	1’b1: swap L/R audio samples read from the source memory of TX_FIFO_0
20	TX_SRC_BYTE_SWAP_0	R/W	0	1’b1: swap H/L bytes read from the source memory of TX_FIFO_ 0
19	DIRECT_MODE_EN	R/W	0	1’b1: WS (LRCK) and SCK (BCLK) are from other SPORT
18:17	SP_DIRECT_SRC_SEL	R/W	0x0	2’b00: WS and SCK are from SPORT0. 2’b01: WS and SCK are from SPORT1. 2’b10: WS and SCK are from SPORT2. 2’b11: WS and SCK are from SPORT3.
16	ERR_CNT_SAT_SET	R/W	0	1’b1: saturation count (65534 -> 65535 -> 65535 …) 1’b0: wrap count (65534 -> 65535 -> 0 -> 1 -> 2 …)
15:14	SPORT_CLK_SEL	R/W	0x0	2’b0x00: dsp_src_clk (BCLK*2) 2’b10: dsp_src_clk (BCLK*4)/2 2’b11: dsp_src_clk (BCLK*8)/4
13	CLEAR_RX_ERR_CNT	R/W	0	Write 1’b1 and then write 0 to clear Rx error counter
12	CLEAR_TX_ERR_CNT	R/W	0	Write 1’b1 and then write 0 to clear Tx error counter
11	ENABLE_MCLK	R/W	0	Enable mclk.
10:8	DEBUG_BUS_SEL	R/W	0x0	3’b000: debug_bus_a 3’b001: debug_bus_b … 3’b111: debug_bus_h
7	WS_FORCE_VAL	R/W	1	When WS_FORCE = 1, ws_out_tx and ws_out_rx = “ws_force_val”
6	WS_FORCE	R/W	0	1’b1: Make ws_out_tx and ws_out_rx = “ws_force_val”
5	BCLK_RESET	R/W	0	1’b0: Enable bclk 1’b1: Disable and reset bclk
4	BCLK_PULL_ZERO	R/W	0	Write 1’b1 to pull bclk to 0 smoothly Write 1’b0 to reopen bclk
3	MULTI_IO_EN_RX	R/W	1	1’b1: Enable multi-IO of Rx 1’b0: Disable multi-IO of Rx
2	MULTI_IO_EN_TX	R/W	1	1’b1: Enable multi-IO of Tx 1’b0: Disable multi-IO of Tx
1	TX_FIFO_FILL_ZERO	R/W	0	X is the burst size of TX_FIFO_0. Y is the burst size of TX_ FIFO_1. Fill TX_FIFO_0 with X zero data and fill TX_FIFO_1 with Y ze ro data. This control bit is “write 1 clear” type
0	SP_RESET_SMOOTH	R/W	0	1’b1: reset SPORT1 module with complete LRCK cycle.

REG_SP_INT_CTRL

• Name : SPORT Interrupt Control Register

• Size : 32

• Address offset : 00Ch

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:24	INT_ENABLE_DSP_1	R/W	0x0	Bit[24]: for the interrupt of “sp_ready_to_tx_1” Bit[25]: for the interrupt of “sp_ready_to_rx_1” Bit[26]: for the interrupt of “tx_fifo_full_intr_1” Bit[27]: for the interrupt of “rx_fifo_full_intr_1” Bit[28]: for the interrupt of “tx_fifo_empty_intr_1” Bit[29]: for the interrupt of “rx_fifo_empty_intr_1” Bit[30]: for the interrupt of “tx_i2s_idle_1” Bit[31]: Reserved
23:16	INT_ENABLE_DSP_0	R/W	0x0	Bit[16]: for the interrupt of “sp_ready_to_tx” Bit[17]: for the interrupt of “sp_ready_to_rx” Bit[18]: for the interrupt of “tx_fifo_full_intr” Bit[19]: for the interrupt of “rx_fifo_full_intr” Bit[20]: for the interrupt of “tx_fifo_empty_intr” Bit[21]: for the interrupt of “rx_fifo_empty_intr” Bit[22]: for the interrupt of “tx_i2s_idle” Bit[23]: Reserved
15:14	DUMMY	R/W	0x0	-
13:9	INTR_CLR_1	R/W	0x0	Bit[9]: for the interrupt of “tx_fifo_full_intr_1” Bit[10]: for the interrupt of “rx_fifo_full_intr_1” Bit[11]: for the interrupt of “tx_fifo_empty_intr_1” Bit[12]: for the interrupt of “rx_fifo_empty_intr_1” Bit[13]: Reserved
8	RX_DSP_CLEAR_INT_1	R/W	0	For DSP mode (bypass GDMA), F/W writes 1’b1 and then 1’b0 to clear Rx interrupt. Note Rx interrupt is to indicate that DSP can get audio data f rom RX_FIFO_1.
7	TX_DSP_CLEAR_INT_1	R/W	0	For DSP mode (bypass GDMA), F/W writes 1’b1 and then 1’b0 to clear TX interrupt. Note Tx interrupt is to indicate that DSP can write audio data to TX_FIFO_1.
6:2	INTR_CLR_0	R/W	0x0	Bit[2]: for the interrupt of “tx_fifo_full_intr” Bit[3]: for the interrupt of “rx_fifo_full_intr” Bit[4]: for the interrupt of “tx_fifo_empty_intr” Bit[5]: for the interrupt of “rx_fifo_empty_intr” Bit[6]: Reserved
1	RX_DSP_CLEAR_INT_0	R/W	0	For DSP mode (bypass GDMA), F/W writes 1’b1 and then 1’b0 to clear Rx interrupt. Note Rx interrupt is to indicate that DSP can get audio data f rom RX_FIFO_0.
0	TX_DSP_CLEAR_INT_0	R/W	0	For DSP mode (bypass GDMA), F/W writes 1’b1 and then 1’b0 to clear Tx interrupt. Note Tx interrupt is to indicate that DSP can write audio data to TX_FIFO_0.

REG_SP_TRX_COUNTER_STATUS

• Name : SPORT TRX Counter Status Register

• Size : 32

• Address offset : 014h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31	SP_RESET_STATE	R	0	1’b1: sp_reset is enabled. 1’b0: sp_reset is disabled.
30	RSVD	R	-	Reserved
29:24	RX_DEPTH_CNT_1	R	0x0	RX_FIFO_1 depth counter status (MIC path)
23:22	RSVD	R	-	Reserved
21:16	TX_DEPTH_CNT_1	R	0x0	TX_FIFO_1 depth counter status (SPK path)
15:14	RSVD	R	-	Reserved
13:8	RX_DEPTH_CNT_0	R	0x0	RX_FIFO_0 depth counter status (MIC path)
7:6	RSVD	R	-	Reserved
5:0	TX_DEPTH_CNT_0	R	0x0	TX_FIFO_0 depth counter status (SPK path)

REG_SP_ERR

• Name : SPORT Error Register

• Size : 32

• Address offset : 018h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:16	RX_ERR_CNT	R	0x0	Rx error counter (MIC path) Note This counter should always be zero if everything works we ll.
15:0	TX_ERR_CNT	R	0x0	Tx error counter (SPK path) Note This counter should always be zero if everything works we ll.

REG_SR_TX_BCLK

• Name : SPORT Tx BCLK Register

• Size : 32

• Address offset : 01Ch

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31	TX_MI_NI_UPDATE	R/W	0	1’b1: to update “mi” and “ni” to get the new clock rate. This bit will be reset automatically when the update is done
30:16	TX_NI	R/W	0x30	BCLK = 40MHz*(ni/mi) For example: BCLK=3.072MHz=40MHz*(48/625)
15:0	TX_MI	R/W	0x271

REG_SP_TX_LRCLK

• Name : SPORT Tx LRCLK Register

• Size : 32

• Address offset : 020h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:24	RX_BCLK_DIV_RATIO	R/W	0x3F	Rx bclk even-bit integer divider. Used in “mode_40mhz” set as 1’b1. (rx_bclk_div_ratio + 1) is the number of “sck_out” cycles wi thin a “ws_out_rx” cycle (1/fs). Default of (rx_bclk_div_ratio + 1) is 64. Set as 64 – 1 = 63 . Only odd number supported. Maximum is 255.
23:16	TX_BCLK_DIV_RATIO	R/W	0x3F	Tx bclk even-bit integer divider. Used in “mode_40mhz” set as 1’b1. (tx_bclk_div_ratio + 1) is the number of “sck_out” cycles wi thin a “ws_out_tx” cycle (1/fs). Default of (tx_bclk_div_ratio + 1) is 64. Set as 64 – 1 = 63 . Only odd number supported. Maximum is 255.
15:14	DUMMY1	R/W	0x0	-
13:8	RXDMA_BUSRTSIZE	R/W	0x10	Rx DMA burst size
7:6	DUMMY2	R/W	0x0	-
5:0	TXDMA_BURSTSIZE	R/W	0x10	Tx DMA burst size

REG_SP_FIFO_CTRL

• Name : SPORT FIFO Control Register

• Size : 32

• Address offset : 024h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31	RX_FIFO_EMPTY_0	R	1	1: RX_FIFO_0 is empty
30	TX_FIFO_EMPTY_0	R	1	1: TX_FIFO_0 is empty
29	RX_FIFO_FULL_0	R	0	1: RX_FIFO_0 is full
28	TX_FIFO_FULL_0	R	0	1: TX_FIFO_0 is full
27	RX_FIFO_EMPTY_1	R	1	1: RX_FIFO_1 is empty
26	TX_FIFO_EMPTY_1	R	1	1: TX_FIFO_1 is empty
25	RX_FIFO_FULL_1	R	0	1: RX_FIFO_1 is full
24	TX_FIFO_FULL_1	R	0	1: TX_FIFO_1 is full
23:14	RSVD	R	-	Reserved
13	TX_I2S_IDLE_1	R	0	1: Tx is working but FIFO_1 is empty.
12	RX_FIFO_EMPTY_INTR_1	R	0	1: RX_FIFO_1 is empty (MIC path)
11	TX_FIFO_EMPTY_INTR_1	R	0	1: TX_FIFO_1 is empty (SPK path)
10	RX_FIFO_FULL_INTR_1	R	0	1: RX_FIFO_1 is full (MIC path)
9	TX_FIFO_FULL_INTR_1	R	0	1: TX_FIFO_1 is full (SPK path)
8	SP_READY_TO_RX_1	R	0	1: It is ready to receive data (MIC path)
7	SP_READY_TO_TX_1	R	0	1: It is ready to send data out (SPK path)
6	TX_I2S_IDLE_0	R	0	1: Tx is working but FIFO_0 is empty.
5	RX_FIFO_EMPTY_INTR_0	R	0	1: RX_FIFO_0 is empty (MIC path)
4	TX_FIFO_EMPTY_INTR_0	R	0	1: TX_FIFO_0 is empty (SPK path)
3	RX_FIFO_FULL_INTR_0	R	0	1: RX_FIFO_0 is full (MIC path)
2	TX_FIFO_FULL_INTR_0	R	0	1: TX_FIFO_0 is full (SPK path)
1	SP_READY_TO_RX_0	R	0	1: It is ready to receive data (MIC path)
0	SP_READY_TO_TX_0	R	0	1: It is ready to send data out (SPK path)

REG_SP_FORMAT

• Name : SPORT Format Register

• Size : 32

• Address offset : 028h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31	TRX_SAME_CH_LEN	R/W	0	1: Tx (SPK path) and Rx (MIC path) have the same channel l ength.
30:28	SP_CH_LEN_SEL_RX	R/W	0x4	3’b000: 16 bits 3’b001: 20 bits 3’b010: 24 bits 3’b100: 32 bits
27	DUMMY3	R/W	0	-
26:24	SP_CH_LEN_SEL_TX	R/W	0x4	3’b000: 16 bits 3’b001: 20 bits 3’b010: 24 bits 3’b100: 32 bits
23	RX_IDEAL_LEN_EN	R/W	0	Function enable of rx_ideal_len.
22:20	RX_IDEAL_LEN	R/W	0x0	Sd_in can be received 1 ~ 8 ( = rx_ideal_len + 1 ) BCLK cycl e latter.
19	TX_IDEAL_LEN_EN	R/W	0	Function enable of tx_ideal_len. PCMA SDO will be delayed 1 LRCK.
18:16	TX_IDEAL_LEN	R/W	0x0	Sd_out can be sent 1 ~ 8 ( = tx_ideal_len + 1 ) BCLK cycle e arlier.
15	DUMMY4	R/W	0	-
14:12	SP_DATA_LEN_SEL_RX_0	R/W	0x0	Data length of MIC path and it is valid if “trx_same_length” == 1’b0. 3’b000: 16 bits 3’b001: 20 bits 3’b010: 24 bits 3’b100: 32 bits
11	SP_EN_I2S_MONO_RX_0	R/W	0	Channel format of MIC path and it is valid if “trx_same_ch” == 1’b0. 1: mono 0: stereo
10	TRX_SAME_LRC	R/W	0	1: “ws_out_rx” is as same as “ws_out_tx”
9:8	SP_DATA_FORMAT_SEL_RX	R/W	0x0	Data format of MIC path and it is valid if “trx_same_fs” == 1’b0. 2’b00: I2S 2’b01: Left-justified 2’b10: PCM mode A 2’b11: PCM mode B
7	FIXED_BCLK	R/W	0	1: Refer to the description of “fixed_bclk_sel” 0: BCLK = dsp_clk/2 when “mode_40mhz = 0”
6	FIXED_BCLK_SEL	R/W	0	0: BCLK is fixed at dsp_src_clk/4 1: BCLK is fixed at dsp_src_clk/2
5	SP_WCLK_RX_INVERSE	R/W	0	1: invert the phase of “ws_out_rx” which is also called as “ADCLRC”
4	DUMMY5	R/W	0	-
3	SCK_OUT_INVERSE	R/W	0	1: invert the phase of “sck_out”
2	TRX_SAME_LENGTH	R/W	1	1: Tx (SPK path) and Rx (MIC path) have the same data leng th. Both are either 16 or 24 bits
1	TRX_SAME_CH	R/W	1	1: Tx (SPK path) and Rx (MIC path) have the same channel s etting. Both are either stereo or mono
0	TRX_SAME_FS	R/W	1	1: Tx (SPK path) and Rx (MIC path) have the same sampling rate

REG_SP_RX_BCLK

• Name : SPORT Rx BCLK Register

• Size : 32

• Address offset : 02Ch

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31	RX_MI_NI_UPDATE	R/W	0	1’b1: to update “mi” and “ni” to get the new clock rate. This bit will be reset automatically when the update is done
30:16	RX_NI	R/W	0x30	BCLK = 40MHz*(ni/mi) For example: BCLK=3.072MHz=40MHz*(48/625)
15:0	RX_MI	R/W	0x271

REG_SP_RX_LRCLK

• Name : SPORT Rx LRCLK Register

• Size : 32

• Address offset : 030h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31	CLR_TX_SPORT_RDY	R/W	0	0x001: clear tx_sport_interrupt signal This control bit is “write 1 clear” type For read, the read data is from clr_tx_sport_rdy
30	EN_TX_SPORT_INTERRUPT	R/W	0	Enable tx_sport_interrupt
29	EN_FS_PHASE_LATCH	R/W	0	0x001: Latch the value of tx_fs_phase_rpt, rx_fs_phase_rpt , tx_sport_sounter, rx_sport_sounter at the same time. This control bit is “write 1 clear” type
28:27	DUMMY6	R/W	0x0
26:0	TX_SPORT_COMPARE_VAL	R/W	0x40	X = (tx_sport_compare_val). When counter equal X. SPORT will send tx_sport_interrupt to DSP. FW should take care X={32~134217727}

REG_SP_DSP_COUNTER

• Name : SPORT DSP Counter Register

• Size : 32

• Address offset : 034h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:5	TX_SPORT_COUNTER	R	0x0	For DSP read instant Tx SPORT counter value, counter down
4:0	TX_FS_PHASE_RPT	R	0x0	Report Tx phase

REG_SP_DIRECT_CTRL0

• Name : SPORT Direct Control Register 0

• Size : 32

• Address offset : 03Ch

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:28	TX_CH7_DATA_SEL	R/W	0x7	4’h0: tx_fifo_0_reg_0_l 4’h1: tx_fifo_0_reg_0_r 4’h2: tx_fifo_0_reg_1_l 4’h3: tx_fifo_0_reg_1_r 4’h4: tx_fifo_1_reg_0_l 4’h5: tx_fifo_1_reg_0_r 4’h6: tx_fifo_1_reg_1_l 4’h7: tx_fifo_1_reg_1_r 4’h8: direct_reg_7
27:24	TX_CH6_DATA_SEL	R/W	0x6	4’h8: direct_reg_6
23:20	TX_CH5_DATA_SEL	R/W	0x5	4’h8: direct_reg_5
19:16	TX_CH4_DATA_SEL	R/W	0x4	4’h8: direct_reg_4
15:12	TX_CH3_DATA_SEL	R/W	0x3	4’h8: direct_reg_3
11:8	TX_CH2_DATA_SEL	R/W	0x2	4’h8: direct_reg_2
7:4	TX_CH1_DATA_SEL	R/W	0x1	4’h8: direct_reg_1
3:0	TX_CH0_DATA_SEL	R/W	0x0	4’h8: direct_reg_0

REG_SP_FIFO_IRQ

• Name : SPORT FIFO IRQ Register

• Size : 32

• Address offset : 044h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31	RX_LSB_FIRST_1	R/W	0	1’b0: MSB first when Tx 1’b1: LSB first
30	TX_LSB_FIRST_1	R/W	0	1’b0: MSB first when Tx 1’b1: LSB first
29	RX_SNK_LR_SWAP_1	R/W	0	1’b1: swap L/R audio samples written to the sink memory of R X_FIFO_1
28	RX_SNK_BYTE_SWAP_1	R/W	0	1’b1: swap H/L bytes written to the sink memory of RX_FIFO_1
27	TX_SRC_LR_SWAP_1	R/W	0	1’b1: swap L/R audio samples read from the source memory of TX_FIFO_1
26	TX_SRC_BYTE_SWAP_1	R/W	0	1’b1: swap H/L bytes read from the source memory of TX_FIFO_ 1
25:16	DUMMY7	R/W	0x0	-
15:8	INT_ENABLE_MCU_1	R/W	0x0	Bit8]: for the interrupt of “sp_ready_to_tx” Bit9]: for the interrupt of “sp_ready_to_rx” Bit10]: for the interrupt of “tx_fifo_full_intr” Bit11]: for the interrupt of “rx_fifo_full_intr” Bit12]: for the interrupt of “tx_fifo_empty_intr” Bit13]: for the interrupt of “rx_fifo_empty_intr” Bit14]: for the interrupt of “tx_i2s_idle” Bit15]: reserved
7:0	INT_ENABLE_MCU_0	R/W	0x0	Bit0]: for the interrupt of “sp_ready_to_tx” Bit1]: for the interrupt of “sp_ready_to_rx” Bit2]: for the interrupt of “tx_fifo_full_intr” Bit3]: for the interrupt of “rx_fifo_full_intr” Bit4]: for the interrupt of “tx_fifo_empty_intr” Bit5]: for the interrupt of “rx_fifo_empty_intr” Bit6]: for the interrupt of “tx_i2s_idle” Bit7]: reserved

REG_SP_DIRECT_CTRL1

• Name : SPORT Direct Control Register 1

• Size : 32

• Address offset : 048h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31	SP_EN_I2S_MONO_RX_1	R/W	0	Channel format of MIC path and it is valid if “trx_same_ch” == 1’b0. 1’b1: mono 1’b0: stereo
30:28	SP_DATA_LEN_SEL_RX_1	R/W	0x0	Data length of MIC path and it is valid if “trx_same_length” == 1’b0. 3’b000: 16 bits 3’b001: 20 bits 3’b010: 24 bits 3’b100: 32 bits
27	SP_EN_I2S_MONO_TX_1	R/W	0	1’b1: mono 1’b0: stereo
26:24	SP_DATA_LEN_SEL_TX_1	R/W	0x0	3’b000: 16 bits 3’b001: 20 bits 3’b010: 24 bits 3’b100: 32 bits
23	DIRECT_REG_3_EN	R/W	0	1’b1: Enable direct_reg_3.
22:18	DIRECT_REG_3_SEL	R/W	0x0	5’h0: spa_direct_in_0 5’h1: spa_direct_in_1 5’h2: spa_direct_in_2 5’h3: spa_direct_in_3 5’h4: spa_direct_in_4 5’h5: spa_direct_in_5 5’h6: spa_direct_in_6 5’h7: spa_direct_in_7 5’h8: spb_direct_in_0 5’h9: spb_direct_in_1 5’ha: spb_direct_in_2 5’hb: spb_direct_in_3 5’hc: spb_direct_in_4 5’hd: spb_direct_in_5 5’he: spb_direct_in_6 5’hf: spb_direct_in_7 5’h10: spc_direct_in_0 5’h11: spc_direct_in_1 5’h12: spc_direct_in_2 5’h13: spc_direct_in_3 5’h14: spc_direct_in_4 5’h15: spc_direct_in_5 5’h16: spc_direct_in_6 5’h17: spc_direct_in_7 5’h18: sp0_direct_in_tx_fifo_0_reg_0_l 5’h19: sp0_direct_in_tx_fifo_0_reg_0_r 5’h1a: sp0_direct_in_tx_fifo_0_reg_1_l 5’h1b: sp0_direct_in_tx_fifo_0_reg_1_r 5’h1c: TDM_RX_CH3 SPORT0: a = 1, b = 2, c = 3 SPORT1: a = 0, b = 2, c = 3 SPORT2: a = 0, b = 1, c = 3 SPORT3: a = 0, b = 1, c = 2
17	DIRECT_REG_2_EN	R/W	0	1’b1: Enable direct_reg_2.
16:12	DIRECT_REG_2_SEL	R/W	0x0	5’h1c: TDM_RX_CH2
11	DIRECT_REG_1_EN	R/W	0	1’b1: Enable direct_reg_1.
10:6	DIRECT_REG_1_SEL	R/W	0x0	5’h1c: TDM_RX_CH1
5	DIRECT_REG_0_EN	R/W	0	1’b1: Enable direct_reg_0.
4:0	DIRECT_REG_0_SEL	R/W	0x0	5’h1c: TDM_RX_CH0

REG_SP_DIRECT_CTRL2

• Name : SPORT Direct Control Register 2

• Size : 32

• Address offset : 04Ch

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31	SP_DIRECT_OUT_7_EN	R/W	0	Enable sp_direct_out_7.
30	SP_DIRECT_OUT_6_EN	R/W	0	Enable sp_direct_out_6.
29	SP_DIRECT_OUT_5_EN	R/W	0	Enable sp_direct_out_5.
28	SP_DIRECT_OUT_4_EN	R/W	0	Enable sp_direct_out_4.
27	SP_DIRECT_OUT_3_EN	R/W	0	Enable sp_direct_out_3.
26	SP_DIRECT_OUT_2_EN	R/W	0	Enable sp_direct_out_2.
25	SP_DIRECT_OUT_1_EN	R/W	0	Enable sp_direct_out_1.
24	SP_DIRECT_OUT_0_EN	R/W	0	Enable sp_direct_out_0.
23	DIRECT_REG_7_EN	R/W	0	1’b1: Enable direct_reg_7.
22:18	DIRECT_REG_7_SEL	R/W	0x0	5’h0: spa_direct_in_0 5’h1: spa_direct_in_1 5’h2: spa_direct_in_2 5’h3: spa_direct_in_3 5’h4: spa_direct_in_4 5’h5: spa_direct_in_5 5’h6: spa_direct_in_6 5’h7: spa_direct_in_7 5’h8: spb_direct_in_0 5’h9: spb_direct_in_1 5’ha: spb_direct_in_2 5’hb: spb_direct_in_3 5’hc: spb_direct_in_4 5’hd: spb_direct_in_5 5’he: spb_direct_in_6 5’hf: spb_direct_in_7 5’h10: spc_direct_in_0 5’h11: spc_direct_in_1 5’h12: spc_direct_in_2 5’h13: spc_direct_in_3 5’h14: spc_direct_in_4 5’h15: spc_direct_in_5 5’h16: spc_direct_in_6 5’h17: spc_direct_in_7 5’h18: sp0_direct_in_tx_fifo_0_reg_0_l 5’h19: sp0_direct_in_tx_fifo_0_reg_0_r 5’h1a: sp0_direct_in_tx_fifo_0_reg_1_l 5’h1b: sp0_direct_in_tx_fifo_0_reg_1_r 5’h1c: TDM_RX_CH7 SPORT0: a = 1, b = 2, c = 3 SPORT1: a = 0, b = 2, c = 3 SPORT2: a = 0, b = 1, c = 3 SPORT3: a = 0, b = 1, c = 2
17	DIRECT_REG_6_EN	R/W	0	1’b1: Enable direct_reg_6.
16:12	DIRECT_REG_6_SEL	R/W	0x0	5’h1c: TDM_RX_CH6
11	DIRECT_REG_5_EN	R/W	0	1’b1: Enable direct_reg_5.
10:6	DIRECT_REG_5_SEL	R/W	0x0	5’h1c: TDM_RX_CH5
5	DIRECT_REG_4_EN	R/W	0	1’b1: Enable direct_reg_4.
4:0	DIRECT_REG_4_SEL	R/W	0x0	5’h1c: TDM_RX_CH4

REG_SP_DIRECT_CTRL3

• Name : SPORT Direct Control Register 3

• Size : 32

• Address offset : 054h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	DUMMY8	R/W	0x0	-
28:24	RX_FIFO_0_REG_1_R_SEL	R/W	0x3	5’d0: RX_CH0_data_out (MIC path) 5’d1: RX_CH1_data_out (MIC path) 5’d2: RX_CH2_data_out (MIC path) 5’d3: RX_CH3_data_out (MIC path) 5’d4: RX_CH4_data_out (MIC path) 5’d5: RX_CH5_data_out (MIC path) 5’d6: RX_CH6_data_out (MIC path) 5’d7: RX_CH7_data_out (MIC path) 5’d8: spa_direct_in_0 5’d9: spa_direct_in_1 5’d10: spa_direct_in_2 5’d11: spa_direct_in_3 5’d12: spa_direct_in_4 5’d13: spa_direct_in_5 5’d14: spa_direct_in_6 5’d15: spa_direct_in_7 5’d16: spb_direct_in_0 5’d17: spb_direct_in_1 5’d18: spb_direct_in_2 5’d19: spb_direct_in_3 5’d20: spb_direct_in_4 5’d21: spb_direct_in_5 5’d22: spb_direct_in_6 5’d23: spb_direct_in_7 5’d24: spc_direct_in_0 5’d25: spc_direct_in_1 5’d26: spc_direct_in_2 5’d27: spc_direct_in_3 5’d28: spc_direct_in_4 5’d29: spc_direct_in_5 5’d30: spc_direct_in_6 5’d31: spc_direct_in_7 SPORT0: a = 1, b = 2, c = 3 SPORT1: a = 0, b = 2, c = 3 SPORT2: a = 0, b = 1, c = 3 SPORT3: a = 0, b = 1, c = 2
23:21	DUMMY9	R/W	0x0
20:16	RX_FIFO_0_REG_1_L_SEL	R/W	0x2
15:13	DUMMY10	R/W	0x0
12:8	RX_FIFO_0_REG_0_R_SEL	R/W	0x1
7:5	DUMMY11	R/W	0x0
4:0	RX_FIFO_0_REG_0_L_SEL	R/W	0x0

REG_SP_DIRECT_CTRL4

• Name : SPORT Direct Control Register 4

• Size : 32

• Address offset : 058h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	DUMMY12	R/W	0x0
28:24	RX_FIFO_1_REG_1_R_SEL	R/W	0x7	5’d0: RX_CH0_data_out (MIC path) 5’d1: RX_CH1_data_out (MIC path) 5’d2: RX_CH2_data_out (MIC path) 5’d3: RX_CH3_data_out (MIC path) 5’d4: RX_CH4_data_out (MIC path) 5’d5: RX_CH5_data_out (MIC path) 5’d6: RX_CH6_data_out (MIC path) 5’d7: RX_CH7_data_out (MIC path) 5’d8: spa_direct_in_0 5’d9: spa_direct_in_1 5’d10: spa_direct_in_2 5’d11: spa_direct_in_3 5’d12: spa_direct_in_4 5’d13: spa_direct_in_5 5’d14: spa_direct_in_6 5’d15: spa_direct_in_7 5’d16: spb_direct_in_0 5’d17: spb_direct_in_1 5’d18: spb_direct_in_2 5’d19: spb_direct_in_3 5’d20: spb_direct_in_4 5’d21: spb_direct_in_5 5’d22: spb_direct_in_6 5’d23: spb_direct_in_7 5’d24: spc_direct_in_0 5’d25: spc_direct_in_1 5’d26: spc_direct_in_2 5’d27: spc_direct_in_3 5’d28: spc_direct_in_4 5’d29: spc_direct_in_5 5’d30: spc_direct_in_6 5’d31: spc_direct_in_7 SPORT0: a = 1, b = 2, c = 3 SPORT1: a = 0, b = 2, c = 3 SPORT2: a = 0, b = 1, c = 3 SPORT3: a = 0, b = 1, c = 2
23:21	DUMMY13	R/W	0x0
20:16	RX_FIFO_1_REG_1_L_SEL	R/W	0x6
15:13	DUMMY14	R/W	0x0
12:8	RX_FIFO_1_REG_0_R_SEL	R/W	0x5
7:5	DUMMY15	R/W	0x0
4:0	RX_FIFO_1_REG_0_L_SEL	R/W	0x4

REG_SP_RX_COUNTER1

• Name : SPORT Rx Counter Register 1

• Size : 32

• Address offset : 05Ch

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31	CLR_RX_SPORT_RDY	R/W	0	X = (tx_sport_compare_val). When counter equal X. SPORT will send tx_sport_interrupt to DSP. FW should take care X={32~8191}
30	EN_RX_SPORT_INTERRUPT	R/W	0	Enable rx sport interrupt.
29:27	DUMMY16	R/W	0x0
26:0	RX_SPORT_COMPARE_VAL	R/W	0x40	X = (rx_sport_compare_val). When counter equal X. SPORT will send rx_sport_interrupt to DSP. FW should take care X={32~134217727}

REG_SP_RX_COUNTER2

• Name : SPORT Rx Counter Register 2

• Size : 32

• Address offset : 060h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:5	RX_SPORT_COUNTER	R	0x0	For DSP read instant Rx SPORT counter value, counter down
4:0	RX_FS_PHASE_RPT	R	0x0	Report Rx phase

REG_SP_MCLK

• Name : SPORT MCLK Register

• Size : 32

• Address offset : 064h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31	MCLK_MI_NI_UPDATE	R/W	0	1’b1: to update “mi” and “ni” to get the new clock rate. This bit will be reset automatically when the update is done
30:16	MCLK_NI	R/W	0xc0	Mclk_out = 40MHz*(ni/mi) For example: mclk_out=3.072MHz=40MHz*(48/625)
15:0	MCLK_MI	R/W	0x271

REG_TX_FIFO_0_WR_ADDR

• Name : TX FIFO 0 Write Address Register

• Size : 32

• Address offset : 800h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:0	TX_FIFO_0_WR_ADDR	R/W	0x0	TX_FIFO_0 write address

REG_RX_FIFO_0_RD_ADDR

• Name : RX FIFO 0 Read Address Register

• Size : 32

• Address offset : 880h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:0	RX_FIFO_0_RD_ADDR	R	0x0	RX_FIFO_0 read address

REG_TX_FIFO_1_WR_ADDR

• Name : TX FIFO 1 Write Address Register

• Size : 32

• Address offset : 900h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:0	TX_FIFO_1_WR_ADDR	R/W	0x0	TX_FIFO_1 write address

REG_RX_FIFO_1_RD_ADDR

• Name : RX FIFO 1 Read Address Register

• Size : 32

• Address offset : 980h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:0	RX_FIFO_1_RD_ADDR	R	0x0	RX_FIFO_1 read address

Audio Codec Digital Register

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Base Address: 0x41106000

Name	Address offset	Access	Description
REG_AUDIO_CONTROL_0	000h	R/W
REG_AUDIO_CONTROL_1	004h	R/W
REG_CLOCK_CONTROL_1	008h	R/W
REG_CLOCK_CONTROL_2	00Ch	R/W
REG_CLOCK_CONTROL_3	010h	R/W
REG_CLOCK_CONTROL_4	014h	R/W
REG_CLOCK_CONTROL_5	018h	R/W
REG_CLOCK_CONTROL_6	01Ch	R/W
REG_CLOCK_CONTROL_7	020h	R/W
REG_ASRC_CONTROL_0	024h	R
REG_ASRC_CONTROL_1	028h	R
REG_ASRC_CONTROL_2	02Ch	R/W
REG_ASRC_CONTROL_3	030h	R/W
REG_I2S_0_CONTROL	03Ch	R/W
REG_I2S_0_CONTROL_1	040h	R/W
REG_ADC_0_CONTROL_0	050h	R/W
REG_ADC_0_CONTROL_1	054h	R/W
REG_ADC_1_CONTROL_0	058h	R/W
REG_ADC_1_CONTROL_1	05Ch	R/W
REG_ADC_ALIGN_CONTROL_REG_0	0ACh	R/W
REG_ADC_ALIGN_CONTROL_REG	0B0h	R/W
REG_ADC_0_SILENCE_CONTROL	100h	R/W
REG_ADC_1_SILENCE_CONTROL	104h	R/W
REG_ADC_0_EQ_CTRL	400h	R/W
REG_ADC_0_BIQUAD_H0_0	404h	R/W
REG_ADC_0_BIQUAD_B1_0	408h	R/W
REG_ADC_0_BIQUAD_B2_0	40Ch	R/W
REG_ADC_0_BIQUAD_A1_0	410h	R/W
REG_ADC_0_BIQUAD_A2_0	414h	R/W
REG_ADC_0_BIQUAD_H0_1	418h	R/W
REG_ADC_0_BIQUAD_B1_1	41Ch	R/W
REG_ADC_0_BIQUAD_B2_1	420h	R/W
REG_ADC_0_BIQUAD_A1_1	424h	R/W
REG_ADC_0_BIQUAD_A2_1	428h	R/W
REG_ADC_0_BIQUAD_H0_2	42Ch	R/W
REG_ADC_0_BIQUAD_B1_2	430h	R/W
REG_ADC_0_BIQUAD_B2_2	434h	R/W
REG_ADC_0_BIQUAD_A1_2	438h	R/W
REG_ADC_0_BIQUAD_A2_2	43Ch	R/W
REG_ADC_0_BIQUAD_H0_3	440h	R/W
REG_ADC_0_BIQUAD_B1_3	444h	R/W
REG_ADC_0_BIQUAD_B2_3	448h	R/W
REG_ADC_0_BIQUAD_A1_3	44Ch	R/W
REG_ADC_0_BIQUAD_A2_3	450h	R/W
REG_ADC_0_BIQUAD_H0_4	454h	R/W
REG_ADC_0_BIQUAD_B1_4	458h	R/W
REG_ADC_0_BIQUAD_B2_4	45Ch	R/W
REG_ADC_0_BIQUAD_A1_4	460h	R/W
REG_ADC_0_BIQUAD_A2_4	464h	R/W
REG_ADC_1_EQ_CTRL	468h	R/W
REG_ADC_1_BIQUAD_H0_0	46Ch	R/W
REG_ADC_1_BIQUAD_B1_0	470h	R/W
REG_ADC_1_BIQUAD_B2_0	474h	R/W
REG_ADC_1_BIQUAD_A1_0	478h	R/W
REG_ADC_1_BIQUAD_A2_0	47Ch	R/W
REG_ADC_1_BIQUAD_H0_1	480h	R/W
REG_ADC_1_BIQUAD_B1_1	484h	R/W
REG_ADC_1_BIQUAD_B2_1	488h	R/W
REG_ADC_1_BIQUAD_A1_1	48Ch	R/W
REG_ADC_1_BIQUAD_A2_1	490h	R/W
REG_ADC_1_BIQUAD_H0_2	494h	R/W
REG_ADC_1_BIQUAD_B1_2	498h	R/W
REG_ADC_1_BIQUAD_B2_2	49Ch	R/W
REG_ADC_1_BIQUAD_A1_2	4A0h	R/W
REG_ADC_1_BIQUAD_A2_2	4A4h	R/W
REG_ADC_1_BIQUAD_H0_3	4A8h	R/W
REG_ADC_1_BIQUAD_B1_3	4ACh	R/W
REG_ADC_1_BIQUAD_B2_3	4B0h	R/W
REG_ADC_1_BIQUAD_A1_3	4B4h	R/W
REG_ADC_1_BIQUAD_A2_3	4B8h	R/W
REG_ADC_1_BIQUAD_H0_4	4BCh	R/W
REG_ADC_1_BIQUAD_B1_4	4C0h	R/W
REG_ADC_1_BIQUAD_B2_4	4C4h	R/W
REG_ADC_1_BIQUAD_A1_4	4C8h	R/W
REG_ADC_1_BIQUAD_A2_4	4CCh	R/W
REG_ANA_READ	800h	R
REG_ADC_0_LPF_RD	804h	R
REG_ADC_1_LPF_RD	808h	R
REG_SILENCE_INFORM	824h	R
REG_AUDIO_RO_DUMMY1	828h	R

REG_AUDIO_CONTROL_0

• Name : Audio Control Register 0

• Size : 32

• Address offset : 000h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:18	RSVD	R	-	Reserved
17:13	AUDIO_DBG_SEL	R/W	0	Debug probe selection
12:6	RSVD	R	-	Reserved
5:4	SYS_CLK_RATE_SEL	R/W	0x2	Audio sys_clk selection
3	AUDIO_CONTROL_0_DUMMY	R/W	0	DUMMY
2:1	RSVD	R	-	Reserved
0	AUDIO_IP_EN	R/W	0

REG_AUDIO_CONTROL_1

• Name : Audio Control Register 1

• Size : 32

• Address offset : 004h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:17	RSVD	R	-	Reserved
16:13	AUDIO_CONTROL_1_DUMMY	R/W	0	Dummy
12	I2S_DATA_RND_EN	R/W	1	I2s_data_rnd_en
11:0	RSVD	R	-	Reserved

REG_CLOCK_CONTROL_1

• Name : Clock Control Register 1

• Size : 32

• Address offset : 008h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15	AD_1_FIFO_EN	R/W	0	ADC channel 1 FIFO clock enable
14	AD_0_FIFO_EN	R/W	0	ADC channel 0 FIFO clock enable
13:8	RSVD	R	-	Reserved
7	AD_1_EN	R/W	0	ADC channel 1 clock enable
6	AD_0_EN	R/W	0	ADC channel 0 clock enable
5:0	RSVD	R	-	Reserved

REG_CLOCK_CONTROL_2

• Name : Clock Control Register 2

• Size : 32

• Address offset : 00Ch

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:18	RSVD	R	-	Reserved
17	AD_1_EQ_EN	R/W	0	ADC channel 1 EQ clock enable
16	AD_0_EQ_EN	R/W	0	ADC channel 0 EQ clock enable
15:10	RSVD	R	-	Reserved
9	DMIC_1_EN	R/W	0	ADC filter channel 1 clock enable: DMIC path
8	DMIC_0_EN	R/W	0	ADC filter channel 0 clock enable: DMIC path
7:0	RSVD	R	-	Reserved

REG_CLOCK_CONTROL_3

• Name : Clock Control Register 3

• Size : 32

• Address offset : 010h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:4	RSVD	R	-	Reserved
3	DMIC1_CLK_EN	R/W	0	Digital microphone clock enable
2:0	DMIC1_CLK_SEL	R/W	1	Set clock of digital microphone 3’b000: 5MHz 3’b001: 2.5MHz 3’b010: 1.25MHz 3’b011: 625kHz 3’b100: 312.5kHz 3’b101: Reserved 3’b110: Reserved 3’b111: 769.2kHz

REG_CLOCK_CONTROL_4

• Name : Clock Control Register 4

• Size : 32

• Address offset : 014h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7:4	SAMPLE_RATE_1	R/W	0	Set sample rate source 1 4’h0: 48K 4’h1: 96K 4’h2: 192K 4’h3: 32K 4’h4: 176.4K 4’h5: 16K 4’h6: Reserved 4’h7: 8K 4’h8: 44.1K 4’h9: 88.2K 4’ha:24K 4’hb: 12K 4’hc: 22.05K 4’hd: 11.025K 4’he~4’hf: Reserved
3:0	SAMPLE_RATE_0	R/W	0	Set sample rate source 0 4’h0: 48K 4’h1: 96K 4’h2: 192K 4’h3: 32K 4’h4: 176.4K 4’h5: 16K 4’h6: Reserved 4’h7: 8K 4’h8: 44.1K 4’h9: 88.2K 4’ha:24K 4’hb: 12K 4’hc: 22.05K 4’hd: 11.025K 4’he~4’hf: Reserved

REG_CLOCK_CONTROL_5

• Name : Clock Control Register 5

• Size : 32

• Address offset : 018h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:4	RSVD	R	-	Reserved
3:2	ADC_1_FS_SRC_SEL	R/W	0	Channel 1 ADC path sample rate source selection 2’b00: Source 0 2’b01: Source 1 2’b10: Source 2
1:0	ADC_0_FS_SRC_SEL	R/W	0	Channel 0 ADC path sample rate source selection 2’b00: Source 0 2’b01: Source 1 2’b10: Source 2

REG_CLOCK_CONTROL_6

• Name : Clock Control Register 6

• Size : 32

• Address offset : 01Ch

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:2	RSVD	R	-	Reserved
1	ADC_1_ASRC_EN	R/W	0	Channel 1 ADC path ASRC enable 0: Disable 1: Enable If ASRC is enabled, sample_rate becomes useless.
0	ADC_0_ASRC_EN	R/W	0	Channel 0 ADC path ASRC enable 0: Disable 1: Enable If ASRC is enabled, sample_rate becomes useless.

REG_CLOCK_CONTROL_7

• Name : Clock Control Register 7

• Size : 32

• Address offset : 020h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:11	RSVD	R	-	Reserved
10:9	ADC_1_DMIC_LPF_CLK_SEL	R/W	0	Channel 1 ADC path DMIC LPF clock 2’b00: 10M 2’b01: 5M 2’b10: 2.5M 2’b11: 769.2*2K
8:7	ADC_0_DMIC_LPF_CLK_SEL	R/W	0	Channel 0 ADC path DMIC LPF clock 2’b00: 10M 2’b01: 5M 2’b10: 2.5M 2’b11: 769.2*2K
6:0	RSVD	R	-	Reserved

REG_ASRC_CONTROL_0

• Name : ASRC Control Register 0

• Size : 32

• Address offset : 024h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:0	RSVD	R	-	Reserved

REG_ASRC_CONTROL_1

• Name : ASRC Control Register 1

• Size : 32

• Address offset : 028h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:0	RSVD	R	-	Reserved

REG_ASRC_CONTROL_2

• Name : ASRC Control Register 2

• Size : 32

• Address offset : 02Ch

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:5	RSVD	R	-	Reserved
4	ASRC_AUTO_ADJUST_RX_0	R/W	1	HW auto adjust convergence rate 0: Disable 1: Enable
3:2	ASRC_GAIN_SEL_RX_0	R/W	0x3	ASRC convergence rate: larger is faster but more noisy
1:0	ASRC_RATE_SEL_RX_0	R/W	0	0: fs supports 4kHz ~ 60kHz 1: fs supports 60kHz ~ 120kHz 2/3: Reserved

REG_ASRC_CONTROL_3

• Name : ASRC Control Register 3

• Size : 32

• Address offset : 030h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:24	RSVD	R	-	Reserved
23:0	ASRC_SDM_INTI_RX_0	R/W	0	Set initial value of tracked frequency

REG_I2S_0_CONTROL

• Name : I2S 0 Control Register

• Size : 32

• Address offset : 03Ch

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:21	RSVD	R	-	Reserved
20	I2S_0_MASTER_SEL	R/W	0	I2S 0 master source selection 1’b0: internal SPORT 1’b1: external I2S
19:18	I2S_0_DATA_CH_SEL_TX	R/W	0	I2S 0 Tx channel data 2’b00: L/R 2’b01: R/L 2’b10: L/L 2’b11: R/R
17:16	I2S_0_CH_LEN_SEL_RX	R/W	0	I2S 0 Rx channel length 2’b00: 16 bits 2’b01: 32 bits 2’b10: 24 bits 2’b11: 8 bits
15:14	I2S_0_CH_LEN_SEL_TX	R/W	0	I2S 0 Tx channel length 2’b00: 16 bits 2’b01: 32 bits 2’b10: 24 bits 2’b11: 8 bits
13:12	I2S_0_DATA_LEN_SEL_RX	R/W	0	I2S 0 Rx channel data length 2’b00: 16 bits 2’b10: 24 bits 2’b11: 8 bits
11:10	I2S_0_DATA_LEN_SEL_TX	R/W	0	I2S 0 Tx channel data length 2’b00: 16 bits 2’b10: 24 bits 2’b11: 8 bits
9:8	I2S_0_DATA_FORMAT_SEL_RX	R/W	0	I2S 0 Rx channel data format 2’b00: I2S 2’b01: Left-justified 2’b10: PCM mode A 2’b11: PCM mode B
7:6	I2S_0_DATA_FORMAT_SEL_TX	R/W	0	I2S 0 Tx channel data format 2’b00: I2S 2’b01: Left-justified 2’b10: PCM mode A 2’b11: PCM mode B
5:4	I2S_0_TDM_MODE_RX	R/W	0	I2S 0 Rx channel TDM mode 0: 2 channels 1: 4 channels 2/3: Reserved
3	I2S_0_SAME_LRC_EN	R/W	0	1’b1: LRC_TX share to LRC_RX
2	I2S_0_SELF_LPBK_EN	R/W	0	1’b1: internal loopback mode is enabled
1	I2S_0_INV_SCLK	R/W	0	1’b1: I2S/PCM bit clock is inverted
0	I2S_0_RST_N_REG	R/W	0	1’b1: rst_n to audio digital IP is de-asserted 1’b0: rst_n to audio digital IP is asserted

REG_I2S_0_CONTROL_1

• Name : I2S 0 Control Register 1

• Size : 32

• Address offset : 040h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31	I2S_0_DATA_CH7_RX_DISABLE	R/W	0	I2S 0 Rx channel data channel 7 1: disable 0: enable
30	I2S_0_DATA_CH6_RX_DISABLE	R/W	0	I2S 0 Rx channel data channel 6 1: disable 0: enable
29	I2S_0_DATA_CH5_RX_DISABLE	R/W	0	I2S 0 Rx channel data channel 5 1: disable 0: enable
28	I2S_0_DATA_CH4_RX_DISABLE	R/W	0	I2S 0 Rx channel data channel 4 1: disable 0: enable
27	I2S_0_DATA_CH3_RX_DISABLE	R/W	0	I2S 0 Rx channel data channel 3 1: disable 0: enable
26	I2S_0_DATA_CH2_RX_DISABLE	R/W	0	I2S 0 Rx channel data channel 2 1: disable 0: enable
25	I2S_0_DATA_CH1_RX_DISABLE	R/W	0	I2S 0 Rx channel data channel 1 1: disable 0: enable
24	I2S_0_DATA_CH0_RX_DISABLE	R/W	0	I2S 0 Rx channel data channel 0 1: disable 0: enable
23:21	I2S_0_DATA_CH7_SEL_RX	R/W	0	I2S 0 Rx channel data channel 7 0: CH0 1: CH1 2/3/4/5/6/7: reserved
20:18	I2S_0_DATA_CH6_SEL_RX	R/W	0	I2S 0 Rx channel data channel 6 0: CH0 1: CH1 2/3/4/5/6/7: reserved
17:15	I2S_0_DATA_CH5_SEL_RX	R/W	5	I2S 0 Rx channel data channel 5 0: CH0 1: CH1 2/3/4/5/6/7: reserved
14:12	I2S_0_DATA_CH4_SEL_RX	R/W	4	I2S 0 Rx channel data channel 4 0: CH0 1: CH1 2/3/4/5/6/7: reserved
11:9	I2S_0_DATA_CH3_SEL_RX	R/W	3	I2S 0 Rx channel data channel 3 0: CH0 1: CH1 2/3/4/5/6/7: reserved
8:6	I2S_0_DATA_CH2_SEL_RX	R/W	2	I2S 0 Rx channel data channel 2 0: CH0 1: CH1 2/3/4/5/6/7: reserved
5:3	I2S_0_DATA_CH1_SEL_RX	R/W	1	I2S 0 Rx channel data channel 1 0: CH0 1: CH1 2/3/4/5/6/7: reserved
2:0	I2S_0_DATA_CH0_SEL_RX	R/W	0	I2S 0 Rx channel data channel 0 0: CH0 1: CH1 2/3/4/5/6/7: reserved

REG_ADC_x_CONTROL_0

• Name : ADC Channel x Control Register 0

• Size : 32

• Address offset : 050h + 04h * x (x=0, 1)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:30	ADC_x_DMIC_LPF2ND_FC_SEL	R/W	0	Uplink Channel x DMIC path SRC 2nd LPF FC
29:27	ADC_x_DCHPF_FC_SEL	R/W	0x4	Channel x ADC path high pass filter Fc
26	ADC_x_DCHPF_EN	R/W	0	Channel x ADC path high pass filter enable control (filter D C) 0: Disable 1: Enable
25:24	RSVD	R	-	Reserved
23	ADC_x_HPF_RSVD	R/W	0	Channel x ADC path reserved
22	ADC_x_AD_MUTE	R/W	0	Channel x ADC path mute 0: Un-Mute 1: Mute
21:20	ADC_x_AD_ZDET_TOUT	R/W	0	Channel x ADC path zero detection time out selection 2’b00: 1024*16 samples 2’b01: 1024*32 samples 2’b10: 1024*64 samples 2’b11: 64 samples
19:18	ADC_x_AD_ZDET_FUNC	R/W	0x2	Channel x ADC path zero detection function selection 2’b00: immediate change 2’b01: zero detection & immediate change 2’b10: zero detection & step 2’b11: zero detection & timeout step
17:8	RSVD	R	-	Reserved
7	ADC_x_DMIC_MIX_MUTE	R/W	1	Channel x DMIC input path mute 0: Un-Mute 1: Mute
6:5	ADC_x_DMIC_LPF1ST_FC_SEL	R/W	0	Channel x DMIC path SRC 1st LPF FC
4	ADC_x_DMIC_LPF1ST_EN	R/W	1	Channel x DMIC path SRC 1st LPF control 0: Disable 1: Enable
3	ADC_x_DMIC_LPF2ND_EN	R/W	1	Channel x DMIC path SRC 2nd LPF control 0: Disable 1: Enable
2:0	ADC_x_DMIC_SRC_SEL	R/W	0	Channel x DMIC source selection 3’b000: MIC 1 rising 3’b001: MIC 1 falling 3’b010: MIC 2 rising 3’b011: MIC 2 falling other: reserved

REG_ADC_x_CONTROL_1

• Name : ADC Channel x Control Register 1

• Size : 32

• Address offset : 054h + 04h * x (x=0, 1)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:17	RSVD	R	-	Reserved
16	ADC_x_FIFO_KEEP_ONE	R/W	0	Channel x I2S sample buffering 0: 4 samples 1: 1 sample
15:12	ADC_x_RPTR_HOLD	R/W	0	Channel x I2S read point hold number Rptr_hold = (I2S_fs/ad_fs) - 1
11:10	DUMMY	R/W	0	Dummy
9:8	ADC_x_BOOST_GAIN	R/W	0	Channel x ADC path boost gain control 00: 0dB 01: 12dB 10: 24dB 11: 36dB
7:0	ADC_x_AD_GAIN	R/W	0x2f	Channel x ADC digital volume -17.625dB ~ 48dB in 0.375dB st ep 8’h00: -17.625dB ... 8’h2f: 0dB 8’h30: 0.375dB ... 8’haf: 48dB

REG_ADC_ALIGN_CONTROL_REG_0

• Name : ADC Align Control Register 0

• Size : 32

• Address offset : 0ACh

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:3	RSVD	R	-	Reserved
2	SP_AD_ALIGN_EN	R/W	0	1: Uplink channel will align with I2S 0: Disable
1	RSVD	R	-	Reserved
0	SP_AD_FIFO_ALIGN_EN	R/W	0	1: Uplink FIFO will align with I2S 0: Disable

REG_ADC_ALIGN_CONTROL_REG

• Name : ADC Align Control Register

• Size : 32

• Address offset : 0B0h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7	ADC_1_ALIGN_EN	R/W	0	Uplink CH1 align enable
6:4	ADC_1_ALIGN_CH_SEL	R/W	0	Uplink CH1 align channel selection 0: CH0 1: CH1 Others: reserved
3	ADC_0_ALIGN_EN	R/W	0	Uplink CH0 align enable
2:0	ADC_0_ALIGN_CH_SEL	R/W	0	Uplink CH0 align channel selection 0: CH0 1: CH1 Others: reserved

REG_ADC_x_SILENCE_CONTROL

• Name : ADC Channel x Silence Control Register

• Size : 32

• Address offset : 100h + 04h * x (x=0, 1)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:7	RSVD	R	-	Reserved
6:4	ADC_x_SILENCE_DEBOUNCE_SEL	R/W	0x3	Channel x ADC path silence detection debounce (48K) 3’b000: 80ms 3’b001: 160ms 3’b010: 320ms 3’b011: 640ms 3’b100: 1.28s 3’b101: 2.56s 3’b110: 5.12s 3’b111: 0.16ms
3:1	ADC_x_SILENCE_LEVEL_SEL	R/W	1	Channel x ADC path silence detection threshold 3’b000: -54db 3’b001: -60db 3’b010: -66db 3’b011: -72db 3’b100: -78db 3’b101: -84db 3’b110: -90db 3’b111: -96db
0	ADC_x_SILENCE_DET_EN	R/W	0	Channel x ADC path silence detection enable 0: Disable 1: Enable

REG_ADC_0_EQ_CTRL

• Name : ADC Channel 0 EQ Control Register

• Size : 32

• Address offset : 400h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:5	RSVD	R	-	Reserved
4	ADC_0_BIQUAD_EN_4	R/W	0	ADC channel 0 EQ 4-band biquad enable 0: disable 1: enable
3	ADC_0_BIQUAD_EN_3	R/W	0	ADC channel 0 EQ 3-band biquad enable 0: disable 1: enable
2	ADC_0_BIQUAD_EN_2	R/W	0	ADC channel 0 EQ 2-band biquad enable 0: disable 1: enable
1	ADC_0_BIQUAD_EN_1	R/W	0	ADC channel 0 EQ 1-band biquad enable 0: disable 1: enable
0	ADC_0_BIQUAD_EN_0	R/W	0	ADC channel 0 EQ 0-band biquad enable 0: disable 1: enable

REG_ADC_0_BIQUAD_H0_x

• Name : ADC Channel 0 EQ x Band Biquad H0 Register

• Size : 32

• Address offset : 404h + 04h * x (x=0, 1, 2, 3, 4)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:0	ADC_0_BIQUAD_H0_x	R/W	0x2000000	ADC channel 0 EQ x-band coef. H0 2’s complement in 4.25 for mat, i.e. the range is from -8~7.99.

REG_ADC_0_BIQUAD_B1_x

• Name : ADC Channel 0 EQ x Band Biquad B1 Register

• Size : 32

• Address offset : 408h + 04h * x (x=0, 1, 2, 3, 4)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:0	ADC_0_BIQUAD_B1_x	R/W	0	ADC channel 0 EQ x-band coef. B1 2’s complement in 4.25 for mat, i.e. the range is from -8~7.99.

REG_ADC_0_BIQUAD_B2_x

• Name : ADC Channel 0 EQ x Band Biquad B2 Register

• Size : 32

• Address offset : 40Ch + 04h * x (x=0, 1, 2, 3, 4)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:0	ADC_0_BIQUAD_B2_x	R/W	0	ADC channel 0 EQ x-band coef. B2 2’s complement in 4.25 for mat, i.e. the range is from -8~7.99.

REG_ADC_0_BIQUAD_A1_x

• Name : ADC Channel 0 EQ x Band Biquad A1 Register

• Size : 32

• Address offset : 410h + 04h * x (x=0, 1, 2, 3, 4)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:0	ADC_0_BIQUAD_A1_x	R/W	0	ADC channel 0 EQ x-band coef. A1 2’s complement in 4.25 for mat, i.e. the range is from -8~7.99.

REG_ADC_0_BIQUAD_A2_x

• Name : ADC Channel 0 EQ x Band Biquad A2 Register

• Size : 32

• Address offset : 414h + 04h * x (x=0, 1, 2, 3, 4)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:0	ADC_0_BIQUAD_A2_x	R/W	0	ADC channel 0 EQ x-band coef. A2 2’s complement in 4.25 for mat, i.e. the range is from -8~7.99.

REG_ADC_1_EQ_CTRL

• Name : ADC Channel 1 EQ Control Register

• Size : 32

• Address offset : 468h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:5	RSVD	R	-	Reserved
4	ADC_1_BIQUAD_EN_4	R/W	0	ADC channel 1 EQ 4-band biquad enable 0: disable 1: enable
3	ADC_1_BIQUAD_EN_3	R/W	0	ADC channel 1 EQ 3-band biquad enable 0: disable 1: enable
2	ADC_1_BIQUAD_EN_2	R/W	0	ADC channel 1 EQ 2-band biquad enable 0: disable 1: enable
1	ADC_1_BIQUAD_EN_1	R/W	0	ADC channel 1 EQ 1-band biquad enable 0: disable 1: enable
0	ADC_1_BIQUAD_EN_0	R/W	0	ADC channel 1 EQ 0-band biquad enable 0: disable 1: enable

REG_ADC_1_BIQUAD_H0_x

• Name : ADC Channel 1 EQ x Band Biquad H0 Register

• Size : 32

• Address offset : 46Ch + 04h * x (x=0, 1, 2, 3, 4)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:0	ADC_1_BIQUAD_H0_x	R/W	0x2000000	ADC channel 1 EQ x-band coef. h0 2’s complement in 4.25 for mat, i.e. the range is from -8~7.99.

REG_ADC_1_BIQUAD_B1_x

• Name : ADC Channel 1 EQ x Band Biquad B1 Register

• Size : 32

• Address offset : 470h + 04h * x (x=0, 1, 2, 3, 4)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:0	ADC_1_BIQUAD_B1_x	R/W	0	ADC channel 1 EQ x-band coef. b1 2’s complement in 4.25 for mat, i.e. the range is from -8~7.99.

REG_ADC_1_BIQUAD_B2_x

• Name : ADC Channel 1 EQ x Band Biquad B2 Register

• Size : 32

• Address offset : 474h + 04h * x (x=0, 1, 2, 3, 4)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:0	ADC_1_BIQUAD_B2_x	R/W	0	ADC channel 1 EQ x-band coef. b2 2’s complement in 4.25 for mat, i.e. the range is from -8~7.99.

REG_ADC_1_BIQUAD_A1_x

• Name : ADC Channel 1 EQ x Band Biquad A1 Register

• Size : 32

• Address offset : 478h + 04h * x (x=0, 1, 2, 3, 4)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:0	ADC_1_BIQUAD_A1_x	R/W	0	ADC channel 1 EQ x-band coef. a1 2’s complement in 4.25 for mat, i.e. the range is from -8~7.99.

REG_ADC_1_BIQUAD_A2_x

• Name : ADC Channel 1 EQ x Band Biquad A2 Register

• Size : 32

• Address offset : 47Ch + 04h * x (x=0, 1, 2, 3, 4)

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:0	ADC_1_BIQUAD_A2_x	R/W	0	ADC channel 1 EQ x-band coef. a2 2’s complement in 4.25 for mat, i.e. the range is from -8~7.99.

REG_ANA_READ

• Name : ANA Read Register

• Size : 32

• Address offset : 800h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:1	RSVD	R	-	Reserved
0	MICBIAS_OC	R		The status flag of MICBIAS over-current protection

REG_ADC_0_LPF_RD

• Name : ADC Channel 0 LPF RD Register

• Size : 32

• Address offset : 804h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:19	RSVD	R	-	Reserved
18:0	ADC_0_LPF_RD	R		CH 0 ADC LPF out values

REG_ADC_1_LPF_RD

• Name : ADC Channel 1 LPF RD Register

• Size : 32

• Address offset : 808h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:19	RSVD	R	-	Reserved
18:0	ADC_1_LPF_RD	R		CH 1 ADC LPF out values

REG_SILENCE_INFORM

• Name : Silence Inform Register

• Size : 32

• Address offset : 824h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:12	RSVD	R	-	Reserved
11	ADC_1_SILENCE_DET_STATUS	R		Ongoing status of adc_1_silencedetection 1’b0: adc_1_silencedetection is resting (clock is gating) 1’b1: adc_1_silencedetection is working
10	ADC_1_SILENCE_DET_O	R		Adc_1_silencedata status (result of silence detection) 1’b0: not adc_1_silencedata 1’b1: adc_1_silenceis detected
9	ADC_0_SILENCE_DET_STATUS	R		Ongoing status of adc_0_silencedetection 1’b0: adc_0_silencedetection is resting (clock is gating) 1’b1: adc_0_silencedetection is working
8	ADC_0_SILENCE_DET_O	R		Adc_0_silencedata status (result of silence detection) 1’b0: not adc_0_silencedata 1’b1: adc_0_silenceis detected
7:0	RSVD	R	-	Reserved

REG_AUDIO_RO_DUMMY1

• Name : Audio RO Dummy1 Register

• Size : 32

• Address offset : 828h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:0	AUDIO_RO_DUMMY1	R		Dummy register

Audio Codec Analog Register

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

None

VAD_PITCH Register

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

None