Advanced Control Timer

The advanced control timer consists of a 16-bit auto-reload counter driven by a programmable prescaler. It is suitable for various applications, including measuring the pulse length of input signals (input capture) or generating output waveforms (output compare and PWM). Pulse length and waveform period can be adjusted between 25ns and 107s. Each timer is fully independent and does not share any resources with each other; different channels of the same timer share the same counter.

Capture Timer

Introduction

The capture timer is driven by a 16-bit auto-reload counter and a 16-bit programmable prescaler. It can be used for various purposes, including measuring the pulse length or count of input signals.

Features

The features of the capture timer are listed below.

• Clock source is XTAL40MHz

• Resolution is 16-bit

• Quantity: 1

• Prescaler bit width is 16-bit

• Counter counting mode is up-counting

• Supports pulse width measurement

• Supports pulse count measurement

• Supports interrupts

Block Diagram

The capture timer is mainly composed of a counter, a pre-load register, a prescaler, and capture registers. The block diagram is shown below.

Functional Description

Up-Counting Mode

The timer is a 16-bit counter with an associated auto-reload register. Both the counter and the auto-reload register can be read and written by software. Read and write operations can be performed even when the counter is running.

The timebase unit includes:

• Counter register ( TIMx_CNT )

• Auto-reload register ( TIMx_ARR )

• Prescaler ( TIMx_PSC )

The timer operates in upcounting mode, where the counter counts from 0 to the auto-reload value (the content of the TIMx_ARR register). When the counter reaches the auto-reload value, a counter overflow event occurs.

Pulse Width Measurement

When the CC0PM bit of the TIMx_CCR0 register is set to 0, the capture timer operates in capture mode 0. In this mode, the width of the TRGI active level can be measured. When TRGI transitions from inactive level to active level, the counter is automatically enabled. When TRGI transitions from active level to inactive level, the counter is automatically disabled, CC0IF is set, and the current count value is copied to the CCR0 field of the TIMx_CCR0 register.

The figure below shows an example of the pulse width measurement mode, where the prescaler division factor is 1 and the rising edge of TRGI is used for capture.

Pulse Count Measurement

When the CC0PM bit of the TIMx_CCR0 register is set to 1, the capture timer operates in capture mode 1. In this mode, the number of valid edges of TRGI within a given period can be counted. When the counter overflows, CC0IF is set, and the count is copied to the CCR0 field of the TIMx_CCR0 register.

The diagram below shows an example of the pulse counting mode, where the prescaler divides by 1, the rising edge of TRGI is used for capture, and the ARR field is equal to E6.

Interrupt Events

There are two types of interrupt events for the capture timer:

• Interrupt events in up-counting mode can be enabled by configuring the UIE bit of the TIMx_DIER register. When the UIE bit is 1, if an interrupt event occurs, it triggers a system interrupt. Both hardware overflow and software-triggered updates generate interrupts. The corresponding interrupt status can be checked through UIF in TIMx_SR , and the corresponding interrupt can be cleared by writing to UIF.

• Interrupt events in capture mode can be enabled by configuring the CC0IE bit of the TIMx_DIER register. Capture mode 0: When TRGI transitions from active level to inactive level, an interrupt event is triggered, and the current count value is copied to the CCR0 field of the TIMx_CCR0 register ; Capture mode 1: When the counter overflows, an interrupt event is triggered, and the value of the counted pulse number is copied to the CCR0 field of the TIMx_CCR0 register

PWM Timer

Introduction

The PWM timer is driven by a 16-bit auto-reload counter and a 16-bit programmable prescaler. It can be used for various purposes, including measuring the pulse frequency of input signals (input capture), single pulse mode, and output waveform generation (PWM).

Features

• Clock source: XTAL40M

• Resolution: 16-bit

• Prescaler: 16-bit

• Count mode: Up-counting

• Supports one-pulse mode

• Supports PWM mode with polarity selection

• Interrupt generation

• Sleep mode

• Duty cycle range: 0 to 100%

• Supports phase shift function

RTL8721DxRTL8720ERTL8710ERTL8726ERTL8713ERTL8730ERTL8721F

• 数量: {{IC_PARAM_PWMTIMER_QUANTITY}}

• 通道数: {{IC_PARAM_PWMTIMER_CHANNEL_NUM}}

Block Diagram

The PWM timer is mainly composed of a counter, a preload register, a prescaler, and capture/compare registers. Different channels of the same PWM timer share the same counter, and different channels can output waveforms with different duty cycles and phases. The block diagram is shown below.

Functional Description

Upcounting Mode

The Timer is a 16-bit counter with an associated auto-reload register. Both the counter and the auto-reload register can be read and written by software. Read and write operations can be performed even while the counter is running.

The time base unit includes:

• Counter register ( TIMx_CNT )

• Auto-reload register ( TIMx_ARR )

• Prescaler register ( TIMx_PSC )

The Timer operates in up-counting mode, where the counter counts from 0 to the auto-reload value (the content of the TIMx_ARR register). When the counter reaches the auto-reload value, a counter overflow event is generated.

Input Capture Mode

Input capture mode allows the timer to automatically latch the current counter value when a specific edge of an external trigger signal arrives. This function can be applied to application scenarios such as pulse width measurement, frequency calculation, and signal period detection.

The input capture mode is enabled by writing 1 to the CCxM bits in the TIMx_CCRx register. Once enabled, the CCRx field of the capture/compare register TIMx_CCRx will be used as a capture register to latch the counter value, and each channel has its own capture register.

When a valid transition edge of the TRGI signal is detected, the timer automatically latches the current counter value into the TIMx_CCRx register. Different channels can be configured with different polarities to capture different edges of the TRGI signal. At the same time, the CCxIF flag bit of the corresponding channel is set in the TIMx_SR status register. If the corresponding interrupt is enabled, the system will generate an interrupt request.

Software can clear this interrupt flag bit by writing 1 to the CCxIF bit.

One Pulse Mode

One-Pulse Mode (OPM) is a special case of PWM mode. It allows the counter to start in response to a stimulus and generate a pulse of programmable length after a programmable delay.

Starting the counter can be controlled by an active edge on TRGI, which can be a rising edge, falling edge, or both edges. The default output level in the idle state can be configured as high or low. The generated waveform can be completed in PWM mode. You can select One-Pulse Mode by setting the OPM bit in the TIMx_CR register. This will cause the counter to stop automatically at the next update.

The timing of One-Pulse Mode is shown in the following diagram.

Note

Since the channels are independent of each other, when TRGI is used to trigger one or more channels to output PWM signals, it can also be used as a capture source in the input capture mode of other channels.

PWM Mode

Pulse Width Modulation mode allows you to generate a signal whose frequency is determined by the value of the register and whose duty cycle is determined by the value of the CCRx field in the TIMx_CCRx register.

• Period: T_PWM = (ARR + 1) × T_CNT

• Duty cycle: D_PWM = (CCRx × T_CNT) / T_PWM

• Where: T_CNT = T_XTAL × (PSC + 1)

PWM mode can be selected independently on each channel (each OCx outputs a PWM) by setting the OCxM bits in the TIMx_CCRx register to 0. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCRx register, and finally enable the auto-reload preload register by setting the ARPE bit in the TIMx_CR register.

Since the preload register is only transferred to the shadow register when an update event occurs, you must initialize all registers by setting the UG bit in the TIMx_EGR register before starting the counter.

The OCx polarity can be programmed in software by the CCxP bit in the TIMx_CCRx register. It can be programmed as active high or active low.

In PWM mode, TIMx_CNT and CCRx (in TIMx_CCRx) are always compared to determine if TIMx_CNT < CCRx. As long as TIMx_CNT < CCRx, the PWM signal OCx remains active, otherwise it becomes inactive. If the comparison value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, the PWM signal OCx output is active throughout the entire period. If the comparison value is 0, the PWM signal OCx output is inactive throughout the entire period.

This timer can only generate PWM in edge-aligned mode. The following diagram shows some examples of edge-aligned PWM waveforms, where TIMx_ARR = 8.

Edge-aligned PWM waveforms (ARR = 8, CCxP = 0)

Phase Synchronization Function

This function is used for users to configure specific phase shifts between channels. It only applies to PWM mode and One-Pulse mode, and input capture mode is not affected.

There are 7 Counters in the PWM timer, including one CNT in the TIM_CNT register and six channel Counters for the six channels respectively. Each channel has a channel Counter, and its value can be obtained by reading the TIM_PHASECNTx (x=0, 1, 2, 3, 4, 5) register. The value of each channel Counter is calculated based on the CNT value in the TIM_CNT register. When the Counter value in TIM_CNT changes, the channel values are updated immediately. Each channel’s waveform uses its own channel Counter as the reference.

The phase shift between channels is achieved by setting the phase shift of the channel Counter relative to the CNT value in the TIM_CNT register. The phase shift function can be configured through the TIM_PSYNCx (x=0, 1, 2, 3, 4, 5) register. When the phase shift function is enabled by setting the SYNCENx bit in the TIM_PSYNCx register, the user can configure the phase shift between that channel’s Counter and the CNT value in TIM_CNT, and the phase shift value is set by SYNCDIR and SYNCPHASE in TIM_PSYNCx. When the phase shift function is disabled, that channel’s channel Counter value is exactly the same as CNT. The channel Counter value is:

channel Counter value = CNT - (-1)^SYNCDIR* (SYNCPHASE)

The hardware always ensures that the channel values are in the 0-ARR range. When the channel Counter value is higher than ARR, it immediately becomes old value - ARR to stay in the 0-ARR range; when the channel Counter value is lower than zero, it immediately becomes old value + ARR.

Phase shift function shows the curve of the channel Counter value relative to the Counter, and the corresponding waveforms generated from the channel Counters of channels 0, 1, and 2. In the following configuration, the phase shift between every two channels is 1/3.

In the above example, for channel 0, the SYNCEN0 of channel 0 is 0, so channel counter0 is always equal to CNT. When channel counter0 is lower than CCR0 (i.e., 30), channel 0 outputs high level; when channel counter0 is higher than CCR0, channel 0 outputs low level. For channel 1, SYNCEN1 is set to 1, so channel counter1 has a phase shift with TIM_CNT. The value of channel Counter 1 is CNT + 66, where CNT is the value of TIM_CNT. When channel counter1 is lower than CCR1, channel 1 outputs high level, and vice versa. For channel 2, channel counter2 is CNT + 33. Under the above settings, there is a 1/3 phase shift between every two channels.

The software ensures that SYNCPHASEx is always less than the ARR value. Otherwise, a low level will be generated and output.

After the PWM timer is enabled and generates waveforms, users may need to update some parameters, such as period, duty cycle, and phase shift values. Since the ARR, PSC, CCRx, and PSYNCx registers can be configured as preloaded or non-preloaded, users have three ways to change the configuration at runtime.

1. Set the register as non-preloaded, then set the new value, and the new value will take effect immediately after the register value changes.

2. Set the register as preloaded, then set the new value, and the new value will be updated after the next UEV of CNT.

3. Set the register as preloaded, set the new value, and then write the UG bit, after which CNT will be cleared and start counting from 0, and the new value will take effect immediately. This is useful when multiple parameters need to be updated immediately.

Phase shift function

The following subsections explain some scenarios.

Immediate update

1. Change the period

   1. Increase ARR value

      waveform when ARR changes from 100 to 150 illustrates when ARR value is changed from 100 to 150. Because ARR is increased, the waveforms in red cycle shows that all three channels are in low level states.

   2. Decrease ARR value

      waveform when ARR changes from 100 to 80 shows when ARR value is changed from 100 to 80. Before ARR is decreased, there is only one channel in high level state at the same time, After ARR is set to 80, the waveforms in red cycle shows that channel 0 and 2 are both in high level states in this case.

      

      waveform when ARR changes from 100 to 150

      

      waveform when ARR changes from 100 to 80

2. Change the duty cycle

   The duty cycle of each channel depends on its CCRx value which is configured individually in its own TIM_CCRx registers. They can’t be updated exactly at the same time due to the time gap that CPU executes instructions. The length of this time gap is unpredictable. The following examples ignore this time gap.

   1. Increase CCRx value

      The following figure displays when CCRx changes from 30 to 40. For channel 2, CCR2 is changed when channel counter2 value is 35 and also 30 < 35 < 40, so that waveform of channel 2 falls into high level simultaneously when CCRs is updated. This causes a glitch. Also, channel 0 and 1 both in high level state because of increasing its CCRx in this case.

      

   2. Decrease CCRx value

      The following figure shows when CCRx changes from 30 to 20. For channel 2, CCR2 is changed when channel counter2 value is 25 and also 20 < 25 < 30, so that waveform of channel 2 falls into low level simultaneously when CCRs is updated. The duty cycle of channel 2 in this period is neither 20% nor 30%, but 25% instead.

      

3. Change phase shift value

   Phase shift of each channel is configured individually in TIM_PSYNCx registers. They can’t be updated exactly at the same time and the following example ignore this time gap. Also, the change of phase shift always results in discrete channel counters and waveforms. The following figure is an example that phase shift of channel 1 changes from 66 to 36 and channel 2 from 33 to 63. For channel 1, channel counter1 is above and below CCR1 before and after changing. For channel 2, channel counter2 is below and above CCR2 before and after changing.

   

   Waveforms when phase shifts change

Update after the next UEV of CNT

1. Change the period

   1. Increase ARR value

      Waveform when ARR changes from 100 to 150 illustrates when ARR value is changed from 100 to 150. Because ARR is increased, the waveforms in red cycle shows that all three channels are in low level states in this case.

   2. Decrease ARR value

      Waveform when ARR changes from 100 to 80 shows when ARR value is changed from 100 to 80. Before ARR is decreased, there is only one channel in high level state at the same time, After ARR is set to 80, the waveforms in red cycle shows that channel 0 and 2 are both in high level states in this case.

      

      Waveform when ARR changes from 100 to 150

      

      Waveform when ARR changes from 100 to 80

2. Change the duty cycle

   The following examples ignore the time gap of configuration. The waveform is similar with cases that CCRx updates immediately.

   1. Increase CCRx value

      The following figure displays when CCRx changes from 30 to 40.

      

   2. Decrease CCRx value

      The following figure shows when CCRx changes from 30 to 20.

      

3. Change phase shift value

   The following example ignores the time gap of configuration; the waveform is similar with cases that phase shifts update immediately.

   

   waveform when phase shift change

Update after writing the UG bit

Before writing the UG bit, the waveform was generated according to the old configuration. The new configuration comes into effect after writing the UG bit, and also CNT and channel counter are cleared to 0. In the following example, ARR changes from 100 to 150, CCRx not changed, phase shift function of channel 0 is disabled, phase shift of channel 1 changes from 66 to 33, and phase shift of channel 2 changes from 33 to 66.

Waveform when writing UG bit

Registers

Capture Timer Registers

RTL8721DxRTL8720ERTL8710ERTL8726ERTL8713ERTL8730ERTL8721F

Base Address: 0x41100200

Name	Address offset	Access	Description
REG_TIM_EN	000h	R/W	Users can configure and observe the counter operation.
REG_TIM_CR	004h	R/W	This register is about the update operation.
REG_TIM_DIER	008h	R/W
REG_TIM_SR	00Ch	R/W
REG_TIM_EGR	010h	R/W	This register is about the update operation, and is user-defined.
REG_TIM_CNT	014h	R	This is timer count register.
REG_TIM_PSC	018h	R/W	This is prescaler value register.
REG_TIM_ARR	01Ch	R/W	This is auto-reload value register.
REG_TIM_CCR0	024h	R/W	This is the register about input capture configuration and the data of capture.
REG_TIM_PULSE_DBC	028h	R/W
REG_TIM_PULSE_DUMMY	02Ch	R/W

REG_TIM_EN

• Name: TIM enable register

• Size: 32

• Address offset: 000h

• Read/write access: R/W

Users can configure and observe the counter operation.

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	CNT_EN	R	0x0	Counter working status 0: Counter is stopped 1: Counter is working
15:9	RSVD	R	-	Reserved
8	CEN	R	0x0	Counter run status 0: Counter is disabled 1: Counter is enabled
7:2	RSVD	R	-	Reserved
1	CNT_STOP	R/W	0x0	Disable the counter Poll CNT_RUN to see the counter status. If CNT_RUN is 0, it means that the counter has been disabled internally.
0	CNT_START	R/W	0x0	Enable the counter Poll CNT_RUN to see the counter status. If CNT_RUN is 1, it means that the counter has been enabled internally.

REG_TIM_CR

• Name: TIM control register

• Size: 32

• Address offset: 004h

• Read/write access: R/W

This register is about the update operation.

Bit	Symbol	Access	INI	Description
31:5	RSVD	R	-	Reserved
4	ARPE	R/W	0x0	Enable auto-reload preloading 0: TIM_ARR register is not buffered 1: TIM_ARR register is buffered
3	RSVD	R	-	Reserved
2	URS	R/W	0x0	Update request source 0: Counter overflow and setting the UG bit 1: Counter overflow
1	UDIS	R/W	0x0	Disable UEV Shadow registers keep their values. Otherwise, buffered registers are then loaded with their preload values when UEV happens.
0	RSVD	R	-	Reserved

REG_TIM_DIER

• Name: TIM interrupt enable register

• Size: 32

• Address offset: 008h

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31:2	RSVD	R	-	Reserved
1	CC0IE	R/W	0x0	Enable Capture/Compare 0 interrupt
0	UIE	R/W	0x0	Enable update interrupt

REG_TIM_SR

• Name: TIM status register

• Size: 32

• Address offset: 00Ch

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31	UG_DONE	R	0x1	UG operation status This bit is cleared by hardware when the UG bit in the TIMx_EGR register is set. When the UG operation is done, hardware set this bit to ‘1’. So, software can poll this bit to see the UG operation status.
30:2	RSVD	R	-	Reserved
1	CC0IF	R/W	0x0	Capture/Compare 0 interrupt flag CC0 channel configured as pulse mode 0: This bit is set when TRGI is transferred to inactive level from active level. CC0 channel configured as pulse mode 1: This bit is set by hardware when the counter overflows. It is cleared by software.
0	UIF	R/W	0x0	Update interrupt flag

REG_TIM_EGR

• Name: TIM event generation register

• Size: 32

• Address offset: 010h

• Read/write access: R/W

This register is about the update operation, and is user-defined.

Bit	Symbol	Access	INI	Description
31:2	RSVD	R	-	Reserved
1	CC0G	R/W	0x0	Capture/Compare 0 generation This bit is set by software and is automatically cleared by hardware. A Capture/Compare event is generated on channel 0: the current value of the counter is captured in TIM_CCR0 register. The CC0IF flag is set, the corresponding interrupt or request is sent if enabled.
0	UG	R/W	0x0	Update generation Re-initialize the counter and generate an update of registers. Note that the prescaler counter is cleared too. (anyway the prescaler ratio is not affected)

REG_TIM_CNT

• Name: TIM counter

• Size: 32

• Address offset: 014h

• Read/write access: R

This is timer count register.

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	CNT	R	0x0	Counter value

REG_TIM_PSC

• Name: TIM prescaler register

• Size: 32

• Address offset: 018h

• Read/write access: R/W

This is prescaler value register.

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	PSC	R/W	0x0	Prescaler value PSC contains the value to be loaded in the actual prescaler register at each UEV (including when the counter is cleared through UG bit of TIM_EGR register).

REG_TIM_ARR

• Name: TIM auto-reload register

• Size: 32

• Address offset: 01Ch

• Read/write access: R/W

This is auto-reload value register.

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	ARR	R/W	0xFFFF	The value to be loaded in the actual auto-reload register. It can be preloaded by setting ARPE bit in TIM_CR.

REG_TIM_CCR0

• Name: TIM Capture register

• Size: 32

• Address offset: 024h

• Read/write access: R/W

This is the register about input capture configuration and the data of capture.

Bit	Symbol	Access	INI	Description
31:29	RSVD	R	-	Reserved
28	CC0PM	R/W	0x0	CC0 pulse mode 0: Pulse mode 0 1: Pulse mode 1
27	RSVD	R	-	Reserved
26	CC0P	R/W	0x0	CC0 channel configured as output: 0: OC0 active high 1: OC0 active low CC0 channel configured as input: 0: Positive edge of TRGI is active for capture 1: Negative edge of TRGI is active for capture
25	RSVD	R	-	Reserved
24	CC0E	R/W	0x0	Enable CC0
23:16	RSVD	R	-	Reserved
15:0	CCR0	R/W	0x0	Capture/Compare 0 value CC0 channel configured as pulse mode 0: the pulse width of TRGI CC0 channel configured as pulse mode 1: the pulse number of TRGI when the counter counts from 0 to ARR

REG_TIM_PULSE_DBC

• Name: Timer Pulse DBC Register

• Size: 32

• Address offset: 028h

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:1	R_DBC_CYC	R/W	0x0	DBC cycle
0	R_DBC_FEN	R/W	0x0	Enable debounce for pulse 0: Disable 1: Enable

REG_TIM_PULSE_DUMMY

• Name: Timer Pulse Dummy Register

• Size: 32

• Address offset: 02Ch

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31:0	DUMMY	R/W	ffffh	Dummy register

REGISTER_CONTENTS=RTL8720E

PWM timer Registers

RTL8721DxRTL8720ERTL8710ERTL8726ERTL8713ERTL8730ERTL8721F

Base Address: 0x41100000

Name	Address offset	Access	Description
REG_TIM_EN	000h	R/W	Users can configure and observe the counter operation.
REG_TIM_CR	004h	R/W	This is the register about the update operation and the work mode configuration.
REG_TIM_DIER	008h	R/W	This is the interrupt Enable register.
REG_TIM_SR	00Ch	R/W	This is the register about timer interrupt and update status.
REG_TIM_EGR	010h	R/W	This is the register about update generation, and is user-defined.
REG_TIM_CNT	014h	R	This is the register about timer count.
REG_TIM_PSC	018h	R/W	This is the register about prescaler value.
REG_TIM_ARR	01Ch	R/W	This is the register about auto-reload value.
REG_RSVD	020h	R	This is a security register for TIM 0~7.
REG_TIM_CCR0	024h	R/W	Refer to register 24h
REG_TIM_CCR1	028h	R/W	Refer to register 24h
REG_TIM_CCR2	02Ch	R/W	Refer to register 24h
REG_TIM_CCR3	030h	R/W	Refer to register 24h
REG_TIM_CCR4	034h	R/W	Refer to register 24h
REG_TIM_CCR5	038h	R/W	Refer to register 24h
REG_TIM_CCR6	03Ch	R/W	Refer to register 24h
REG_TIM_CCR7	040h	R/W	Refer to register 24h
REG_TIM_PSYNC0	044h	R/W	Refer to register 44h
REG_TIM_PSYNC1	048h	R/W	Refer to register 44h
REG_TIM_PSYNC2	04Ch	R/W	Refer to register 44h
REG_TIM_PSYNC3	050h	R/W	Refer to register 44h
REG_TIM_PSYNC4	054h	R/W	Refer to register 44h
REG_TIM_PSYNC5	058h	R/W	Refer to register 44h
REG_TIM_PSYNC6	05Ch	R/W	Refer to register 44h
REG_TIM_PSYNC7	060h	R/W	Refer to register 44h
REG_TIM_PHASECNT0	064h	R	Refer to register 64h
REG_TIM_PHASECNT1	068h	R	Refer to register 64h
REG_TIM_PHASECNT2	06Ch	R	Refer to register 64h
REG_TIM_PHASECNT3	070h	R	Refer to register 64h
REG_TIM_PHASECNT4	074h	R	Refer to register 64h
REG_TIM_PHASECNT5	078h	R	Refer to register 64h
REG_TIM_PHASECNT6	07Ch	R	Refer to register 64h
REG_TIM_PHASECNT7	080h	R	Refer to register 64h
REG_TIM_PWM_DUMMY	084h	R/W

REG_TIM_EN

• Name: TIM enable register

• Size: 32

• Address offset: 000h

• Read/write access: R/W

Users can configure and observe the counter operation.

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	CNT_EN	R	0x0	Counter working status 0: Counter is stopped 1: Counter is working
15:9	RSVD	R	-	Reserved
8	CEN	R	0x0	Counter run status 0: Counter is disabled 1: Counter is enabled
7:2	RSVD	R	-	Reserved
1	CNT_STOP	R/W	0x0	Disable the counter. Poll CNT_RUN to see the counter status. If CNT_RUN is 0, it means that the counter has been disabled internally.
0	CNT_START	R/W	0x0	Enable the counter. Poll CNT_RUN to see the counter status. If CNT_RUN is 1, it means that the counter has been enabled internally.

REG_TIM_CR

• Name: TIM control register

• Size: 32

• Address offset: 004h

• Read/write access: R/W

This is the register about the update operation and the work mode configuration.

Bit	Symbol	Access	INI	Description
31:10	RSVD	R	-	Reserved
9:8	ETP	R/W	0x0	External trigger polarity (TRGI) 0: Positive edge is active 1: Negative edge is active 2 or 3: Both edge is active Note These bits are only valid in one-pulse mode.
7:5	RSVD	R	-	Reserved
4	ARPE	R/W	0x0	Enable auto-reload preloading 0: TIM_ARR register is not buffered 1: TIM_ARR register is buffered
3	OPM	R/W	0x0	One-pulse mode 0: Counter is not stopped at UEV 1: Counter stops counting at next UEV
2	URS	R/W	0x0	Update request source 0: Counter overflow and setting the UG bit 1: Counter overflow
1	UDIS	R/W	0x0	Disable UEV Shadow registers keep their values. Otherwise, buffered registers are then loaded with their preload values when UEV happens.
0	RSVD	R	-	Reserved

REG_TIM_DIER

• Name: TIM interrupt enable register

• Size: 32

• Address offset: 008h

• Read/write access: R/W

This is the interrupt Enable register.

Bit	Symbol	Access	INI	Description
31:24	RSVD	R	-	Reserved
23	UIE7	R/W	0x0	Enable channel 7 update interrupt
22	UIE6	R/W	0x0	Enable channel 6 update interrupt
21	UIE5	R/W	0x0	Enable channel 5 update interrupt
20	UIE4	R/W	0x0	Enable channel 4 update interrupt
19	UIE3	R/W	0x0	Enable channel 3 update interrupt
18	UIE2	R/W	0x0	Enable channel 2 update interrupt
17	UIE1	R/W	0x0	Enable channel 1 update interrupt
16	UIE0	R/W	0x0	Enable channel 0 update interrupt
15:9	RSVD	R	-	Reserved
8	CC7IE	R/W	0x0	Enable Capture/Compare 7 interrupt
7	CC6IE	R/W	0x0	Enable Capture/Compare 6 interrupt
6	CC5IE	R/W	0x0	Enable Capture/Compare 5 interrupt
5	CC4IE	R/W	0x0	Enable Capture/Compare 4 interrupt
4	CC3IE	R/W	0x0	Enable Capture/Compare 3 interrupt
3	CC2IE	R/W	0x0	Enable Capture/Compare 2 interrupt
2	CC1IE	R/W	0x0	Enable Capture/Compare 1 interrupt
1	CC0IE	R/W	0x0	Enable Capture/Compare 0 interrupt
0	UIE	R/W	0x0	Enable counter update interrupt

REG_TIM_SR

• Name: TIM status register

• Size: 32

• Address offset: 00Ch

• Read/write access: R/W

This is the register about timer interrupt and update status.

Bit	Symbol	Access	INI	Description
31	UG_DONE	R	0x1	UG operation status This bit is cleared by hardware when the UG bit in the TIMx_EGR register is set. When the UG operation is done, hardware sets this bit to ‘1’. So, software can poll this bit to see the UG operation status.
30:24	RSVD	R	-	Reserved
23	UIF7	R/W	0x0	Refer to UIF0 description
22	UIF6	R/W	0x0	Refer to UIF0 description
21	UIF5	R/W	0x0	Refer to UIF0 description
20	UIF4	R/W	0x0	Refer to UIF0 description
19	UIF3	R/W	0x0	Refer to UIF0 description
18	UIF2	R/W	0x0	Refer to UIF0 description
17	UIF1	R/W	0x0	Refer to UIF0 description
16	UIF0	R/W	0x0	Update interrupt flag of channel 0 This flag is set by hardware when the UIE0 bit in the TIMx_EGR register is set, and update interrupt of channel 0 happens.
15:9	RSVD	R	-	Reserved
8	CC7IF	R/W	0x0	Refer to CC0IF description
7	CC6IF	R/W	0x0	Refer to CC0IF description
6	CC5IF	R/W	0x0	Refer to CC0IF description
5	CC4IF	R/W	0x0	Refer to CC0IF description
4	CC3IF	R/W	0x0	Refer to CC0IF description
3	CC2IF	R/W	0x0	Refer to CC0IF description
2	CC1IF	R/W	0x0	Refer to CC0IF description
1	CC0IF	R/W	0x0	Capture/Compare 0 interrupt flag Channel CC0 configured as output: This flag is set by hardware when the counter TIM_CNT value matches the value of TIM_CCR0 register. It is cleared by software. Channel CC0 configured as input: This flag is set by hardware and the counter value has been captured in CCR0 field of TIM_CCR0 register when an active edge has been detected. It is cleared by software.
0	UIF	R/W	0x0	Update interrupt flag

REG_TIM_EGR

• Name: TIM event generation register

• Size: 32

• Address offset: 010h

• Read/write access: R/W

This is the register about update generation, and is user-defined.

Bit	Symbol	Access	INI	Description
31:9	RSVD	R	-	Reserved
8	CC7G	R/W	0x0	Refer to CC0G description
7	CC6G	R/W	0x0	Refer to CC0G description
6	CC5G	R/W	0x0	Refer to CC0G description
5	CC4G	R/W	0x0	Refer to CC0G description
4	CC3G	R/W	0x0	Refer to CC0G description
3	CC2G	R/W	0x0	Refer to CC0G description
2	CC1G	R/W	0x0	Refer to CC0G description
1	CC0G	R/W	0x0	Capture/Compare 0 generation This bit is set by software and is automatically cleared by hardware. Channel CC0 configured as output: The CC0IF flag is set, the corresponding interrupt or request is sent if enabled. Channel CC0 configured as input: The current value of counter is capture in CCR0 field of TIM_CCR0 register. The CC0IF flag is set, the corresponding interrupt or request is sent if enabled.
0	UG	R/W	0x0	Update generation Re-initialize the counter and generate an update of registers. Note that the prescaler counter is cleared too. (anyway the prescaler ratio is not affected)

REG_TIM_CNT

• Name: TIM counter

• Size: 32

• Address offset: 014h

• Read/write access: R

This is the register about timer count.

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	CNT	R	0x0	Counter value

REG_TIM_PSC

• Name: TIM prescaler register

• Size: 32

• Address offset: 018h

• Read/write access: R/W

This is the register about prescaler value.

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	PSC	R/W	0x0	Prescaler value PSC contains the value to be loaded in the actual prescaler register at each UEV (including when the counter is cleared through UG bit of TIM_EGR register).

REG_TIM_ARR

• Name: TIM auto-reload register

• Size: 32

• Address offset: 01Ch

• Read/write access: R/W

This is the register about auto-reload value.

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	ARR	R/W	0xFFFF	The value to be loaded in the actual auto-reload register. It can be preloaded by setting ARPE bit in the TIM_CR register.

REG_RSVD

• Name: Reserved register

• Size: 32

• Address offset: 020h

• Read/write access: R

This is a security register for TIM 0~7.

Bit	Symbol	Access	INI	Description
31:0	RSVD	R	-	Reserved

REG_TIM_CCRx

• Name: TIM Capture/Compare register x

• Size: 32

• Address offset: 024h + 04h * x (x=0, 1, 2, 3, 4, 5, 6, 7)

• Read/write access: R/W

This is the register about the configuration of input capture and output compare work mode.

Bit	Symbol	Access	INI	Description
31:30	RSVD	R	-	Reserved
29	OPM_DLx	R/W	0x0	One-pulse mode default level 0: Default level is 0 1: Default level is 1 This bit takes effect only in PWM output one-pulse mode.
28	RSVD	R	-	Reserved
27	CCxM	R/W	0x0	CCx working mode 0: PWM mode 1: Input capture mode
26	CCxP	R/W	0x0	CCx channel configured as output: 0: OCx active high 1: OCx active low CCx channel configured as input: 0: Positive edge of TRGI is active for capture 1: Negative edge of TRGI is active for capture
25	OCxPE	R/W	0x0	Enable output capture x preload 0: Disable preload register on CCRx. CCRx can be written at any time, the new value is taken into account immediately. 1: Enable preload register on CCRx. Read/Write operations access the preload register. CCRx preload value is loaded in the active register at each UEV.
24	CCxE	R/W	0x0	Enable CCx
23:16	RSVD	R	-	Reserved
15:0	CCRx	R/W	0x0	Capture/Compare x value CCx channel configured as output: CCRx is the value to be loaded in the actual capture/compare x register (preload value). It is loaded permanently if the preload feature is not selected in the OCxPE bit. Else the preload value is copied in the active capture/compare x register when an UEV occurs. The active capture/compare x register contains the value to be compared to the counter TIM_CNT and signalled on OCx output. CCx channel configured as pulse mode 1: CCRx is the counter value transferred by the last input capture event (TRGI)

REG_TIM_PSYNCx

• Name: TIM Phase Synchronization register x

• Size: 32

• Address offset: 044h + 04h * x (x=0, 1, 2, 3, 4, 5, 6, 7)

• Read/write access: R/W

This is the register about the configuration of phase deviation for PWM output.

Bit	Symbol	Access	INI	Description
31:28	RSVD	R	-	Reserved
27	SYNCENx	R/W	0x0	Enable phase sync function in channel x. Phase sync takes effect only in output PWM mode.
26	SYNCDIRx	R/W	0x0	Phase sync direction to the reference counter 0: Delay to the reference counter 1: Ahead to the reference counter
25	SYNCPEx	R/W	0x0	Enable sync phase parameter preload 0: Disable preload register on PSYNCx. PSYNCx can be written at any time, the new value is taken into account immediately. 1: Enable preload register on PSYNCx. Read/Write operations access the preload register. PSYNCx preload value is loaded in the active Register at each UEV.
24:16	RSVD	R	-	Reserved
15:0	SYNCPHASEx	R/W	0x0	The deviation value of channel x to the reference counter

REG_TIM_PHASECNTx

• Name: TIM phase counter register x

• Size: 32

• Address offset: 064h + 04h * x (x=0, 1, 2, 3, 4, 5, 6, 7)

• Read/write access: R

This is the register about phase counter.

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	CNTx	R	0x0	Phase counter value of channel x

REG_TIM_PWM_DUMMY

• Name: Timer PWM Dummy Register

• Size: 32

• Address offset: 084h

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31:0	DUMMY	R/W	ffffh	Dummy register