DMA 控制器

简介

直接内存访问控制器（Direct Memory Access Controller，DMAC）可在无需 CPU 干预的情况下，自主执行源端（外设或内存）与目的端（外设或内存）之间的数据传输。

特性

• 提供 8 个独立可配置的单向传输通道，支持软件编程设置通道优先级，独立管理指定源端与目的端之间的数据传输。

• 完全兼容 AXI4 协议，提供 APB4 从接口用于寄存器编程与配置，以及 32 位数据位宽的 AXI 主接口。

• 支持内存到内存、内存到外设、外设到内存、外设到外设四种高速数据传输类型。

• 支持灵活选择流控制器，可配置 DMAC 或源端 / 目的端外设作为流控制器。

• 支持单次事务与突发事务。

• 支持源端与目的端地址独立配置，可选择地址递增或保持不变。

• 支持基于链表与通道寄存器自动重载机制，实现多块数据的连续传输。

• 支持通道暂停、恢复以及禁用操作，保证操作过程中数据不丢失。

• 具备单块传输完成、传输完成、传输错误（含安全错误、协议错误）等事件标志，支持中断请求组合、独立输出与屏蔽控制。

• 支持通道安全模式配置，AXI 主接口与 APB 从接口均支持安全访问控制，提升系统数据访问安全性。

RTL8721DxRTL8720ERTL8710ERTL8726ERTL8713ERTL8730ERTL8721FRTL8720F

RTL8721Dx:

• 每个通道具备独立 FIFO，通道 0/1 的 FIFO 深度为 128 字节，其他通道为 32 字节。

• 支持大容量数据块传输，单块最大传输大小为 65535 个数据项（以源端传输位宽为单位）。

• 提供 30 个硬件握手接口，用于 DMAC 与外设之间的传输请求与流控制。

框图

下图展示了 DMAC 的架构，包含控制接口、数据传输接口、独立的通道 FIFO、硬件请求接口以及内部仲裁器。

DMA 控制器架构框图

• APB 从接口：用于配置和访问 DMAC。系统通过 APB 总线对 DMAC 进行编程与配置，包括但不限于：设置源端与目的端地址、配置通道控制寄存器、选择流控制器等，同时也可通过该接口读取通道的中断与运行状态。

• AXI 主接口：DMAC 在 AXI 总线上作为主机运行。DMAC 通过此数据总线接口执行数据传输：从源端读取数据，并将其写入目的端。该接口完全支持单次事务与突发事务。

• 硬件握手接口：提供了一套专用于与外设交互的硬件握手信号集。当外设准备好发送或接收数据时，将通过此接口向 DMAC 发起硬件请求。DMAC 响应请求后，将依据协议控制双方之间的单次或突发事务。

• 通道与 FIFO：DMAC 内部集成了多个独立的传输通道，支持多任务并发执行。在传输过程中，从源端读取的数据会优先缓存至该通道专属的 FIFO 中，随后再写入目的端。这种基于 FIFO 的缓冲机制，有效缓解了源端与目的端之间因工作时钟或数据吞吐率差异导致的传输压力。

• 仲裁器：当存在多个激活的 DMA 通道同时请求进行数据传输时，仲裁器将根据预设的优先级调度策略，裁决并分配 AXI 总线的访问权。该机制确保在高吞吐量场景下，DMAC 主机接口资源能够被高效且有序地利用。

功能描述

本节描述 DMAC 组件的功能细节。

基本功能

传输层级

DMAC 的数据传输过程在逻辑上可划分为三个层级：

1. DMA 传输

   DMA 传输是 DMAC 执行的最高层级操作。一次完整的 DMA 传输始于软件启动 DMA 通道，终止于通道被禁用或产生传输完成中断。

   根据应用场景的复杂程度，一次 DMA 传输可划分为：

   • 单块传输：整个 DMA 传输周期内仅包含单一数据块。

   • 多块传输：包含多个数据块的串联运行（例如通过链表实现非连续内存空间的数据传输，或通过自动重载实现周期性刷新）。

2. 数据块传输

   数据块是构成 DMA 传输的次级逻辑单元，代表一组需要连续传输的数据。每次数据块传输结束时，DMAC 可选择性地触发数据块完成中断。

3. 总线事务

   事务（Transaction）是 DMAC 与系统总线（AXI）及外设 FIFO 之间进行数据交互的基本执行单元。为最大化总线带宽利用率，DMAC 会将数据块的传输需求拆分为多次事务来执行。事务分为以下两种类型：

   • 突发事务（Burst Transaction）：

     DMAC 取得总线仲裁权后，连续且不间断地执行指定数量的数据项（数据宽度由 CTLx_L.SRC_TR_WIDTH 或 CTLx_L.DST_TR_WIDTH 决定）读写操作。突发长度由源端或目的端突发长度参数（ CTLx_L.SRC_MSIZE 或 CTLx_L.DEST_MSIZE ）决定。该模式具备极高的总线吞吐率，适用于数据块的主体数据传输。

   • 单次事务（Single Transaction）：

     DMAC 取得总线仲裁权后，仅执行单次数据项的读写操作，随后即释放总线或等待下一次握手请求。该模式通常用于处理不足以构成完整突发长度的尾部非对齐数据，或响应缓冲深度极浅的低速外设请求。

假设软件配置某通道从外设读取 35 个数据项构成一个数据块（Block Size = 35），并设定突发长度为 8。在执行此数据块传输时，DMAC 底层的总线行为表现为： 执行 4 次突发事务（处理 4 × 8 = 32 个数据项），随后自动降级执行 3 次单次事务（处理剩余的 3 个尾部数据项）。上述所有事务共同完成了该单一数据块的完整传输。

备注

• 只有 DMAC 作为流控制器时，数据块大小才可配置；

• 当外设作为流控制器时，数据块大小未知，传输完全取决于外设发出的事务请求。详情参考 传输类型与流控制器 章节。

无论是单块还是多块传输，在使能通道前，必须通过编程通道的控制寄存器（ CTLx_L 与 CTLx_H ）和配置寄存器（ CFGx_L 与 CFGx_H ）来界定传输的基础硬件行为。下表定义了决定总线事务特性的核心参数：

寄存器/参数域	功能描述
DMAC_CHx_FIFO_DEPTH	内部 FIFO 深度：通道内部 FIFO 的深度，决定了通道缓冲数据的最大容量。
CTLx_L.TT_FC	传输类型与流控制：定义传输方向（支持 M2M、M2P、P2M、P2P）以及主导流控制的设备（可分配给 DMAC、源端外设或目的端外设）。
CTLx_H.BLOCK_TS	块传输大小：指定单一数据块传输中包含的数据项总数（以源端传输位宽为单位），仅当 DMAC 作为流控制器时有效。
CTLx_L.SRC_TR_WIDTH	源端传输位宽：定义源端单次总线访问的数据位宽。该值不可大于系统总线宽度，主要用于总数据块大小计算及流模式下的字节/半字传输。
CTLx_L.DST_TR_WIDTH	目的端传输位宽：定义目的端单次总线访问（通常为外设 FIFO）的数据位宽。该值同样不可大于系统总线宽度。
CTLx_L.SRC_MSIZE	源端突发长度：每次响应源端握手请求时，从源端读取的数据项数量。若源端地址递增模式设为固定，为符合 AXI 协议规范，该值不应大于 16。
CTLx_L.DEST_MSIZE	目的端突发长度：每次响应目的端握手请求时，写入目的端的数据项数量。若目的端地址递增模式设为固定，该值同样不应大于 16。
CTLx_L.SINC / DINC	源端/目的端地址递增模式：指示每次传输后地址是递增还是保持固定。若目的端为内存且设为固定，则对应传输位宽必须等于系统总线位宽。
CTLx_L.LLP_SRC_EN / LLP_DST_EN	链表控制使能：决定在源端或目的端是否使能基于链表的块链接功能，配合 LLP_Lx 寄存器实现复杂的多块传输。
CFGx_L.RELOAD_SRC / RELOAD_DST	自动重载使能：在多块传输模式下，决定每个数据块传输结束时，是否将源端地址寄存器（SARx）或目的端地址寄存器（DARx）自动恢复为初始值。
CFGx_H.SRC_PER / DEST_PER	外设握手接口分配：当选择硬件握手时，将通道的源端或目的端分配给特定的硬件握手接口编号。
CFGx_H.PROTCTL	保护控制：控制通道执行安全或非安全 DMA 传输。设为 0 使能安全传输，设为 1 使能非安全传输。
CFGx_H.FCMODE	流控制模式：当目的端外设作为流控制器时，决定源端事务请求的响应时机。设为 0 时立即响应并使能数据预取；设为 1 时需等待目的端请求发生后才响应，禁用数据预取。

传输类型与流控制器

流控制器是用于决定 DMA 数据块传输总数据量，并在传输完成时触发终止的硬件实体。当前芯片支持将 DMAC 或参与传输的外设（源端/目的端）配置为流控制器。

• 如果传输数据量已知，应配置 DMAC 为流控制器。块大小应编程到 CTLx_H.BLOCK_TS 字段中。

• 如果传输数据量未知，应配置外设为流控制器。实际数据传输量完全由外设决定。例如当 DMA 用于接收 UART 串口的不定长数据时，由于 CPU 无法预知对端发送的数据量，此时应由 UART 外设作为流控制器。当 UART 发生空闲超时等情况时，由外设向 DMAC 置位 dma_last 信号来终止当前数据块的传输。

• 内存没有与 DMAC 的硬件握手接口，因此内存永远不能作为流控制器。一旦使能 DMA 通道，面向内存的传输就会立即进行，无需等待任何事务请求。

DMAC 支持 4 种传输类型以及 2 种流控制器设置，通过 CTLx_L.TT_FC 字段进行配置。下表列出了有效的组合：

传输类型	流控制器
内存到内存	DMAC
内存到外设	DMAC
内存到外设	外设
外设到内存	DMAC
外设到内存	外设
外设到外设	DMAC
外设到外设	源端外设
外设到外设	目的端外设

流控制模式（ CFGx_H.FCMODE ）用于控制 DMAC 内部 FIFO 是否使能数据预取机制。它决定了在特定传输类型下，DMAC 响应源端请求的策略：

• 0：使能数据预取（默认）。DMAC 只要收到源端外设的请求，就会立即读取数据填入 FIFO，无需等待目的端外设发出请求。

• 1：禁用数据预取。DMAC 必须在收到目的端外设的请求后，才会去响应源端外设的请求并执行数据读取，防止源端数据被提前读出而滞留在 FIFO 中。

警告

CFGx_H.FCMODE 仅在传输类型为外设到外设，且目的端外设为流控制器（即 CTLx_L.TT_FC = 3'b111）时才有效。对于其他传输类型，必须将此位保持为 0。

事务模式和总线位宽

事务是 DMAC 在硬件层面上执行数据传输的最小独立动作。在外设传输场景中，事务严格定义了 DMAC 与源端/目的端外设之间的交互行为。硬件层面支持以下两种事务类型：

• 单次事务：每次传输一个数据项，在总线上直接映射为一次 AXI 读/写传输。

• 突发事务：由软件编程设定突发长度（ CTLx_L.SRC_MSIZE / CTLx_L.DEST_MSIZE ）。DMAC 会将此事务转换为一系列 AXI 增量突发（Incremental Burst）或单次事务组合，且单次 AXI 突发的长度不会超过设定的最大突发长度。突发长度的设定需与 DMAC 及外设内部的 FIFO 深度相匹配。

在数据事务中，实际在总线上传输的字节总数由传输位宽和突发长度共同决定。

DMAC 支持以下突发长度：

CTLx_L.SRC_MSIZE[2:0] / CTLx_L.DEST_MSIZE[2:0]	突发长度
000	1
001	4
010	8
011	16
100 及以上	不支持

DMAC 支持以下传输位宽：

CTLx_L.SRC_TR_WIDTH[2:0] / CTLx_L.DST_TR_WIDTH[2:0]	传输位宽解码值（字节）
000	1
001	2
010	4
011 及以上	不支持

当使用特定传输类型或流控制器时，需满足以下参数绑定条件：

• 外设到外设

  • 目的端作为流控制器：必须设置 SRC_MSIZE = 3'b000 且 DEST_MSIZE = 3'b000，且源端与目的端位宽必须相等（ SRC_TR_WIDTH == DST_TR_WIDTH ）。

  • 源端作为流控制器：目的端仅在 dma_single 信号有效时才执行传输。

• 内存到外设

  • 目的端作为流控制器：源端与目的端突发长度必须一致（ SRC_MSIZE = DEST_MSIZE ）。

地址对齐与传输位宽的强制要求：

• 当源端或目的端为外设且使用硬件握手时，其起始地址（ SARx/DARx ）必须与对应的传输位宽（ CTLx_L.SRC_TR_WIDTH / DST_TR_WIDTH ）保持边界对齐。

• 当目的端为外设且地址模式为固定时，源端传输的总字节数必须是目的端传输位宽（ DST_TR_WIDTH 字节数）的整数倍。

备注

面向内存的传输位宽，在物理总线上始终与 4 字节（32-bit）边界对齐，这独立于软件设置的逻辑传输位宽。

事务字节数

• 源端单次事务字节数

  src_single_size_bytes = (CTLx_L.SRC_TR_WIDTH 的解码值，单位：Byte)
  

• 源端突发事务字节数

  src_burst_size_bytes = (CTLx_L.SRC_MSIZE 的解码值) * src_single_size_bytes
  

• 目的端单次事务字节数

  dst_single_size_bytes = (CTLx_L.DST_TR_WIDTH 的解码值，单位：Byte)
  

• 目的端突发事务字节数

  dst_burst_size_bytes = (CTLx_L.DEST_MSIZE 的解码值) * dst_single_size_bytes
  

数据块总字节数

一个数据块包含的总字节数，取决于当前配置的流控制器。

1. DMAC 作为流控制器：当 DMAC 作为流控制器时，处理器需将数据块传输中包含的数据项总数编程至 CTLx_H.BLOCK_TS 寄存器中。此时数据块的总字节数为：

   blk_size_bytes_dma = CTLx_H.BLOCK_TS * src_single_size_bytes
   

2. 源端外设作为流控制器：当源端外设控制传输流程时，总字节数由其实际发起的突发和单次事务请求次数累加得出：

   blk_size_bytes_src = (num_of_src_burst_req * src_burst_size_bytes) +
                        (num_of_src_single_req * src_single_size_bytes)
   

3. 目的端外设作为流控制器：当目的端外设控制传输流程时，总字节数由其消耗的突发和单次事务请求次数累加得出：

   blk_size_bytes_dst = (num_of_dst_burst_req * dst_burst_size_bytes) +
                        (num_of_dst_single_req * dst_single_size_bytes)
   

地址模式

源端和目的端可以独立配置以下两种地址模式：

• 递增（Increment）：每次传输完成后，地址自动对齐到下一个 CTLx_L.SRC_TR_WIDTH 或 CTLx_L.DST_TR_WIDTH 边界，适用于连续地址空间（如内存）的数据传输。

• 固定（Fixed）：每次传输完成后地址保持固定，适用于单一固定地址的外设 FIFO 读写访问。

配置原则：

• 如果源端或目的端为内存，地址模式通常配置为递增。

• 如果源端或目的端为外设，地址模式通常配置为固定。

中断

当前 DMAC 支持以下 4 种中断类型，主要用于指示传输进度或异常状态：

DMA 中断类型与产生条件

中断源	中断类型	产生条件
IntTfr	DMA 传输完成中断	一次完整的 DMA 传输（可能由单个或多个数据块组成）顺利完成时触发。
IntBlock	块传输完成中断	单个数据块传输完成（当前块的数据成功写入目的端并完成应答）时触发。
IntPtcErr	协议错误中断	DMAC 主机端口在 AXI 总线上收到错误响应（Error Response）时触发。
IntSecErr	安全错误中断	当非安全环境的 CPU 尝试访问属于 TrustZone 安全通道的寄存器时触发（仅当使能安全模式时）。

以传输完成中断为例，中断生成的硬件逻辑如下：

传输完成中断的屏蔽和生成机制

中断处理流程分为以下几个阶段：

1. 原始状态锁存：当中断事件发生时，硬件首先将其锁存到对应的原始状态寄存器（RAW_*）中。该标志位会保持置位，直到被软件显式清除。

2. 中断屏蔽处理：硬件将原始状态（RAW_*）与对应的屏蔽寄存器（MASK_*）以及通道的全局中断使能位（ CTLx_L.INT_EN ）执行按位与（Bitwise AND）操作。

3. 状态生成与汇总：屏蔽操作的最终有效结果存储于状态寄存器（STAT_*）中。同时，综合状态寄存器（STAT_INT）会对各类单项状态寄存器执行按位或（Bitwise OR）操作，汇总输出当前通道未被屏蔽的中断状态。

4. 中断清除机制：软件向对应的清除寄存器（CLR_*）相应位写 1，即可在同一时钟周期内，同步清除原始状态（RAW_*）和屏蔽状态（STAT_*）中的对应标志，并撤销物理中断请求信号。

备注

若中断事件发生但被 MASK 寄存器或 INT_EN 屏蔽，对外的状态标志和物理中断信号将被拦截，但原始状态寄存器（RAW_*）中对应的位依然会置位，以此记录事件的发生轨迹。

Cache 一致性

• 若源端或目的端地址位于 Cache 区域，在使能 DMA 传输前，软件必须显式执行 D-Cache Clean（数据缓存清除）操作，将 Cache 中的脏数据写回主存。

• 在 DMA 传输完成且 CPU 准备读取目标内存数据前，必须执行 D-Cache Invalidate（数据缓存无效化）操作，强制 CPU 重新从主存加载最新数据，防止读取到过期的 Cache 行导致数据不一致。

握手接口

握手接口在事务级别用于控制单次或突发事务的传输流程。握手接口的操作因外设或 DMAC 是否为流控制器而异。

• 外设使用握手接口向 DMAC 指示它已准备好通过总线传输或接收数据。

• 外设可以通过硬件握手接口向 DMAC 请求 DMA 传输。

备注

在本文档的其余部分中，对源端和目的端硬件握手接口的引用均假定高电平有效（请参阅通道配置寄存器中的 CFGx.SRC_HS_POL 或 CFGx.DST_HS_POL 位）。当使用低电平有效握手接口时，有效电平和边沿与高电平有效接口相反。

握手接口的类型取决于外设是否为流控制器。

小技巧

源端和目的端外设可以独立选择握手接口类型。有两种接口类型：

• 硬件握手：默认支持。有关更多信息，请参阅 CFGx 寄存器中的 CFGx_L.HS_SEL_SRC 和 CFGx_L.HS_SEL_DST 参数。

• 软件握手：不支持。

所有硬件握手接口及其对应的外设在芯片设计时已固定，用户无法自行更改。当前芯片支持的硬件握手接口及其对应 IP 如下表所示：

RTL8721DxRTL8720ERTL8710ERTL8726ERTL8713ERTL8730ERTL8721FRTL8720F

RTL8721Dx:

功能	握手编号	说明
UART0 TX	0
UART0 RX	1
UART1 TX	2
UART1 RX	3
UART2 TX	4
UART2 RX	5
SPI0 TX	6
SPI0 RX	7
SPI1 TX	8
SPI1 RX	9
SPIC TX	10
SPIC RX	11
SPORT0 TX	12	两个FIFO，占用编号12和13
SPORT0 RX	14	两个FIFO，占用编号14和15
SPORT1 TX	16	两个FIFO，占用编号16和17
SPORT1 RX	18	两个FIFO，占用编号18和19
LEDC_TX	20
I2C0 TX	21
I2C0 RX	22
I2C1 TX	23
I2C1 RX	24

DMAC 作为流控制器

当 DMAC 是流控制器时，DMAC 尝试使用尽可能少的总线带宽高效传输数据。通常，DMAC 使用突发事务传输数据，并尽可能在一次突发事务中填充或清空通道 FIFO —— 前提是软件没有限制突发长度。

1. 信号

   图 DMAC 作为流控制器 展示了当 DMAC 作为流控制器时，外设与 DMAC 之间的硬件握手接口。

   

   DMAC 作为流控制器

   下表描述了 DMAC 作为流控制器时的硬件握手信号。可以使用 CFGx_L.SRC_HS_POL 和 CFGx_L.DST_HS_POL 字段编程信号极性。

   信号	方向	描述
   dma_req	输入	来自外设的突发事务请求。 无论 dma_single 的电平如何，DMAC 始终将 dma_req 解释为突发请求。 类型：电平敏感。 握手：外设一旦置位 dma_req，该信号必须保持有效状态，直到 DMAC 置位 dma_ack 为止。 完成：收到 DMAC 发出的 dma_ack 后（表示突发完成），外设应取消置位 dma_req。外设取消置位 dma_req 后，DMAC 就会取消置位 dma_ack。
   dma_single	输入	单次事务状态。 当目的端外设可以接受至少一个数据项，或源端外设可以发送至少一个数据项时，由对应外设置位；否则由对应外设取消置位。 握手：一旦置位 dma_single 后，必须保持置位，直到 dma_ack 被置位。然后外设必须取消置位 dma_single。 有效性：此信号仅在数据块传输的单次事务区域被采样。在此区域之外，它将被忽略（所有传输都被视为突发）。
   dma_last	输入	忽略。由于外设不是流控制器，DMAC 不采样此信号。
   dma_ack	输出	DMAC 确认信号。在当前事务（单次或突发）的最后一个 AXI 传输的数据阶段之后置位。 取消置位触发： 单次事务：保持置位，直到外设取消置位 dma_single。 突发事务：保持置位，直到外设取消置位 dma_req。 取消置位时序： 如果使用同步握手接口， dma_ack 会在 1 个 dmac_clk 周期后取消置位。 如果使用异步握手接口， dma_ack 会在 6 + SYNC 个 dmac_clk 周期后取消置位，其中 SYNC 为同步级数。
   dma_finish	输出	数据块完成信号。DMAC 置位此信号以指示整个数据块传输完成。 时序：通常遵循与 dma_ack 相同的时序。 握手循环：与 dma_req 或 dma_single 形成闭环。 例外：当目的端外设是流控制器时，dma_finish 与源端外设接口交互的时序定义与上述不同。

   备注

   对于 dma_ack 和 dma_finish，当使能通道且 HS_POL 配置为低电平有效时，由于模块尚未完全进入工作状态，在数据块真正开始传输之前，该信号可能仍然存在短暂的"有效"电平。

2. 时序图

   图 突发事务示例 显示了外设时钟 per_clk 等于 dmac_clk 的突发事务的时序图。在此示例中，外设位于单次事务区域之外，因此 DMAC 不采样 dma_single。

   

   突发事务示例

   握手序列如下：

   1. 外设置位 dma_req

   2. DMAC 置位 dma_ack

   3. 外设取消置位 dma_req

   4. DMAC 取消置位 dma_ack

   如果外设是 AXI 外设，则 per_clk 信号等于 dmac_clk；如果外设是 APB 外设，则等于 pclk。突发事务请求信号 dma_req 和单次事务状态信号 dma_single 由 per_clk 所在的外设生成，并由 DMAC 中的 clk 采样。确认信号 dma_ack 由 dmac_clk 所在的 DMAC 生成，并由外设中的 per_clk 进行采样。DMAC 与外设之间的握手机制支持准同步时钟：即 dmac_clk 和 per_clk 必须相位对齐，并且当使用同步握手接口时，dmac_clk 频率必须是 per_clk 频率的倍数。

3. APB 目的端外设和缓冲写入

   

   目的端外设是 APB 外设

   如果目的端外设是 APB 外设，并且通过 APB 桥进行缓冲写入，必须小心操作，以免目的端外设 FIFO 溢出。

   1. 溢出原因：写入在 AXI 总线上完成，而在 APB 总线上尚未完成（写入可能仍在 APB 桥中缓冲）。

   2. 溢出场景：

      1. 一旦写入事务在 AXI 接口上完成，DMAC 就置位 dma_ack。

      2. APB 外设在采样到确认信号被置位后，取消置位其请求信号。

      3. 由于数据仍在桥中缓冲且尚未到达 FIFO，外设感知到仍有空间。因此，它在一个 APB 时钟周期后重新置位请求信号。

      4. 外设可能只有一个数据项的空间，第一个（待处理的）缓冲写入最终将消耗该空间。第二个事务的启动可能会使 FIFO 溢出。

   3. 解决方案：为避免这种情况，系统设计时需要采取以下两种策略之一

      1. 禁用缓冲写入，保证总线写操作的同步。

      2. 如果使用缓冲写入，确保来自 DMAC 的 dma_ack 信号被强制延迟，直到数据真正写入到 APB 外设。具体方法是将 dma_ack 信号路由到 APB 桥。

   备注

   如果写入操作未被缓冲，则第二个事务的启动不会发生，因为目的端外设将正确感知到其 FIFO 已满。

外设作为流控制器

当外设配置为流控制器时，外设控制数据块的总长度。它负责在数据块传输完成时向 DMAC 显式发出信号。

• 发出完成信号：外设通过向 DMAC 指示当前事务（无论是突发还是单次）为数据块中的最后一个事务，来完成数据块的结束指示。

• 事务类型选择：外设直接向 DMAC 指示要执行的事务类型。当数据块大小不是 CTLx_L.SRC_MSIZE / CTLx_L.DEST_MSIZE 的整数倍，外设必须使用单次事务来完成数据块传输。

备注

由于外设能够发起单次事务并结束数据块，因此 单次事务传输场景 的概念不适用于此模式。

1. 信号

   图 外设是流控制器 显示了外设是流控制器时，目的端或源端外设与 DMAC 之间的硬件握手接口。

   

   外设是流控制器

   下表描述了外设是流控制器时硬件握手接口信号的操作：

   信号	方向	描述
   dma_req	输入	来自外设的事务请求。dma_req 上的有效电平启动请求，而具体的事务类型（单次或突发）由 dma_single 信号确定。 握手协议：一旦 dma_req 被置位，必须保持置位，直到 dma_ack 被置位为止。当外设检测到 dma_ack 被置位时，必须取消置位 dma_req。
   dma_single	输入	确定事务类型（单次或突发），在 dma_req 信号产生上升沿的同一个时钟周期内进行采样。 突发事务：当 dma_single 被取消置位时。 单次事务：当 dma_single 被置位时。 dma_single 必须在 dma_req 有效时保持稳定，不能随意翻转。
   dma_last	输入	指示数据块中的最后一个事务。当外设是流控制器时， dma_last 与 dma_req 在同一周期中置位。 如果 dma_single 为高电平：最后一个事务是单次事务。 如果 dma_single 为低电平：最后一个事务是突发事务。 dma_last 必须在 dma_req 有效时保持稳定。
   dma_ack	输出	DMAC 确认信号。在当前事务（单次或突发）的最后一次 AXI 传输的数据阶段完成后，该信号会被置位。该信号与 dma_req 形成握手循环，并保持置位，直到外设取消置位 dma_req。 如果使用同步握手接口：在检测到 dma_req 取消置位后 1 个周期内取消置位。 如果使用异步握手接口：在检测到 dma_req 取消置位后，延迟 （6 + SYNC） 个周期后取消置位。
   dma_finish	输出	数据块传输完成信号。DMAC 置位 dma_finish 以指示数据块传输完成，与 dma_ack 使用相同的时序，并与 dma_req 形成握手循环。

   备注

   对于 dma_ack 和 dma_finish，当使能通道且 HS_POL 配置为低电平有效时，由于模块尚未完全进入工作状态，在数据块真正开始传输之前，该信号可能仍然存在短暂的"有效"电平。

2. 时序图

   1. 在使用同步握手接口时，时序图 1 显示了突发事务后跟单次事务的情况，其中单次事务是数据块中的最后一个事务。

      1. 在时钟边沿 T1 上，DMAC 采样到 dma_req 被置位，dma_single 被取消置位，dma_last 被取消置位。这表明外设向 DMAC 请求一次突发传输，并且告知 DMAC 后续仍有数据。

      2. 在时钟边沿 T2 上，DMAC 采样到 dma_req、dma_single 和 dma_last 都被置位。这表明外设向 DMAC 请求一次单次传输，并且告知 DMAC 数据传输完成。其中，dma_last 和 dma_single 只需要在 dma_req 置位的同一时钟周期内有效即可。

      

      时序图 1

   2. 类似地，在使用同步握手接口时，时序图 2 显示了单次事务后跟突发事务的情况，其中突发事务是数据块中的最后一个事务。

      警告

      配置源端或目的端为流控制器但禁用相应的硬件握手是非法的。

      

      时序图 2

备注

如果传输类型是外设到外设，并且目的端是流控制器时：

• 突发长度限制：源端和目的端的突发长度（ CTLx_L.SRC_MSIZE 和 CTLx_L.DEST_MSIZE ）必须为 0。

• 位宽对齐限制：源端和目的端的传输位宽（ CTLx_L.SRC_TR_WIDTH 和 CTLx_L.DST_TR_WIDTH ）必须相等。

• 已知异常：当 CTLx_L.TT_FC 设置为 3'b111 且 CFGx_H.FCMODE 设置为 1 时，即使整个传输结束，源端的 dma_finish 也可能不会置位。

外设发起 DMA 传输请求

外设通过持续监控自身的 FIFO 数据量，并在达到预设的阈值时，发起不同类型的 DMA 传输请求：

• 源端外设：当源端外设内部 FIFO 的数据量达到或超过设定的阈值时，将置位 dma_req 信号（产生有效边沿），请求 DMAC 读取并搬走数据。

• 目的端外设：当目的端外设内部 FIFO 的数据量低于设定的阈值时，将置位 dma_req 信号，请求 DMAC 写入数据。

外设通知 DMAC 进行数据传输时，FIFO 的阈值配置应与 DMAC 通道的突发事务大小保持严格一致：

• 源端对应配置： CTLx_L.SRC_MSIZE

• 目的端对应配置： CTLx_L.DEST_MSIZE

为达到最高效的总线利用率，外设预留的数据量或可用空间应刚好满足 DMAC 一次突发事务的需求。

在外设到内存的传输场景中，若外设 FIFO 中的残留数据不足以达到触发 DMA 请求的阈值（且总线处于空闲状态，无新数据流入），通常依赖外设硬件内置的超时机制或强制 Flush 机制，来主动触发残留数据的 DMA 传输或向处理器上报中断请求。

事务请求与总线控制

单次事务传输场景

在数据块传输中，某些情况下使用单次事务传输，具体取决于流控制器角色：

• 当 DMAC 作为流控制器时：传输的总数据量是已知的。若满足以下任一条件，DMAC 将自动控制源端或目的端执行单次事务传输：

  • 源端或目的端突发长度（ CTLx_L.SRC_MSIZE 或 CTLx_L.DEST_MSIZE ）被软件配置为 0。

  • 数据块传输接近尾声，剩余的未传输数据量不足以凑齐一次完整的突发读/写事务（此时底层硬件会自动降级，使用单次事务进行尾部数据的收尾）。

• 当外设作为流控制器时：传输的总数据量是未知的。外设必须通过硬件握手信号主动向 DMAC 请求单次传输（通常用于处理非对齐的尾部数据）。若满足以下条件，对应端将执行单次事务：

  • 源端外设作为流控制器：当其发起的 dma_single 和 dma_req 信号在同一时钟周期内有效时。

  • 目的端外设作为流控制器：当其发起的 dma_single 和 dma_req 信号在同一时钟周期内有效时。

发起传输

总线仲裁

每个 DMA 通道内部都包含两个独立且并行运行的状态机：

• 源端状态机

• 目的端状态机

这两个状态机根据传输需求，向内部仲裁器发出占用总线的请求。一次成功的数据传输，必须严格按顺序满足以下三个条件：

1. 内部 FIFO 就绪：只有当 DMAC 通道内部的 FIFO 达到就绪状态（源端有足够空间写入，或目的端有足够数据读出）时，后续的总线请求才能继续推进。

2. 获得 AXI 主接口控制权（第一级仲裁）：源端或目的端状态机发出请求后，必须被通道内部仲裁器选中，从而获得 DMA AXI 主接口的控制权。

3. 获得外部 AXI 总线控制权（第二级仲裁）：AXI 主接口在代表状态机向外发起读写事务时，必须经过系统总线矩阵的仲裁，最终获得外部 AXI 总线的物理控制权。

FIFO 就绪标准

AXI 传输能否启动，直接依赖于 DMAC 内部通道 FIFO 的就绪状态：

• 单次事务：

  • 源端读取就绪：通道 FIFO 内部必须有足够的剩余空间，至少能容纳一次 CTLx_L.SRC_TR_WIDTH 宽度的数据。

  • 目的端写入就绪：通道 FIFO 内部必须已缓冲足够的数据，至少能满足一次 CTLx_L.DST_TR_WIDTH 宽度的数据量。

• 突发事务：

  • 源端读取就绪：通道 FIFO 内部必须有足够的剩余空间，以容纳整个突发长度（ CTLx_L.SRC_MSIZE 次 CTLx_L.SRC_TR_WIDTH ）的数据。

  • 目的端写入就绪：通道 FIFO 内部必须已经准备好整个突发长度（ CTLx_L.DEST_MSIZE 次 CTLx_L.DST_TR_WIDTH ）的数据。

在某些特殊配置下，AXI 总线上的实际读/写突发长度会被硬件强制截断，限制为不超过 FIFO_DEPTH / 2（即 FIFO 深度的一半）。触发此限制的条件包括：

• 源端地址（ SARx ）或目的端地址（ DARx ）与 DMAC 的传输位宽未对齐。

• 使能了分散/聚集功能，且传输类型配置为地址递增。详细机制请参阅 分散/聚集（Scatter/Gather） 章节。

• 当前 DMAC 硬件配置不支持“突发长度大于 FIFO 深度”，且在当前系统总线宽度下，通道 FIFO 的深度不超过 256。

发起传输请求

• 对于外设传输：源端或目的端状态机必须同时满足“FIFO 已就绪”并且“收到外设的单次/突发握手请求信号”，才会正式向 AXI 主接口发出总线读写请求。

• 对于内存传输：由于内存没有硬件握手信号，状态机只要检测到内部 FIFO 准备就绪，就会立刻向 AXI 主接口发起请求。如果目标存储器（或总线从机）尚未准备好接收或提供数据，将会在 AXI 总线上插入等待状态（Wait States）。

小心

当目的端外设作为流控制器，且软件设置了 CFGx_H.FCMODE = 1 （即禁用数据预取）时，即便源端 FIFO 的剩余空间已准备就绪，且源端外设也发出了请求，源端状态机也绝对不会生成 AXI 读请求，除非目的端外设明确发出了请求新数据的握手信号。

多数据块传输

DMAC 支持单数据块与多数据块传输模式。在多数据块连续传输过程中，当前数据块（Block N）传输完成时，硬件会自动对通道寄存器进行重新编程，以无缝衔接下一个数据块（Block N+1）的传输。

DMAC 提供了三种基础的寄存器更新策略，并且支持在源端和目的端独立配置这些机制：

• 链表模式（Linked List）：通过 LLP_Lx 寄存器，硬件主动从系统内存中抓取下一条链表项（Linked List Item，LLI），利用其内容覆写通道寄存器以启动新数据块。

• 自动重载（Auto-reload）：数据块传输完成时，硬件自动将指定的通道寄存器恢复为该通道首次启动时的初始配置值。

• 连续地址块（Contiguous）：当前数据块的起始地址由硬件自动设定为上一个数据块结束时的末尾地址（平滑递增）。

下表列出了各模式下的寄存器更新策略详细信息：

寄存器更新策略

寄存器	连续寻址	自动重载	链表模式
SARx	硬件自动递增地址指针（若源端使用当前策略）	硬件自动恢复为通道启动时的初始地址（若源端使用当前策略）	硬件从下一个链表项中更新地址（若源端使用当前策略）
DARx	硬件自动递增地址指针（若目的端使用当前策略）	硬件自动恢复为通道启动时的初始地址（若目的端使用当前策略）	硬件从下一个链表项中更新地址（若目的端使用当前策略）
CTL_L/Hx	不支持 （保持当前值）	硬件自动恢复为通道启动时的初始配置	硬件从下一个链表项中更新配置
LLP_Lx	不支持 （保持当前值）	不支持 （保持当前值）	硬件从下一个链表项中更新下一节点地址

备注

• 在多块传输场景下，如果采用块级串接机制，通常优先使用链表方式进行多块管理。

• 连续地址块模式必须和其他两种模式结合使用。

• 不支持在传输执行期间互换源端与目的端的地址。

• 不支持在整个多块传输期间更改传输方向。

链表模式

链表模式常用于处理非连续数据块的传输，示意图如 源端/目的端均使用链表 。在该模式下，驱动软件需要在系统内存中按顺序组织一条链表，链表中包含一系列链表项。在每个数据块传输开始前，DMAC 主动从系统内存中抓取预先创建好的链表项，以此对通道内部寄存器进行重新编程，实现多块传输。

源端/目的端均使用链表

链表模式下，链表项由以下几个核心寄存器组成，它们与通道配置寄存器 CFG_L/Hx 共同决定数据块的传输行为：

• SARx：源地址寄存器

• DARx：目的地址寄存器

• CTLx_L/H：控制寄存器

• LLP_Lx：链表指针寄存器

链表项的具体结构示意图如下：

链表项结构

其中链表项与通道寄存器之间的映射关系如下图：

从 LLP_Lx 指向的位置读取 LLI.CTLx，其物理地址等于 LLI 基地址（存放在 LLP_Lx 寄存器中）加上固定偏移量。例如， LLI.CTLx 的地址为 LLP_Lx.LOC + 0x0C 。

LLP_Lx 始终通过链表机制进行更新。在传输开始前，链表首地址需要写入通道寄存器 LLP_Lx 中，链表项的 LLP_Lx 成员总是指向下一个链表项。

• 线性链表：如果最后一个链表项的 LLP_Lx 的值为空地址，且 CTLx.LLP_SRC_EN 或 CTLx.LLP_DST_EN 被清除，DMAC 将识别当前数据块为多块传输的最后一个数据块，传输完毕后停止传输。

• 环形链表：如果最后一个链表项的 LLP_Lx 的值为链表首地址，且 CTLx.LLP_SRC_EN 或 CTLx.LLP_DST_EN 被使能，DMAC 将识别当前数据块为多块传输中的中间数据块，传输完毕后继续从首地址开始传输。

警告

对链表项的访问严格使用 32 位对齐访问，且该访问特性不可配置。

自动重载

自动重载模式无需依赖链表，通过使能 CFGx_L.RELOAD_SRC 或者 CFGx_L.RELOAD_DST，DMAC 可以在每个数据块传输完成时自动将 SARx、DARx 和 CTLx 中的部分或全部字段恢复为初始值，随后启动新的数据块传输。

自动重载模式示意图如下：

源端/目的端均使用自动重载

备注

使能自动重载功能时，如果开启块完成中断（block-complete），用户需要在当前数据块传输完成后清除块完成中断。否则，该中断值将保持高电平，无法再次触发。

连续地址块

连续（Contiguous）地址块模式下，下一个数据块的起始地址将无缝衔接上一个数据块末尾地址。连续地址块模式通常与其他模式（自动重载或链表模式）组合使用，非常适合一端数据连续递增，另一端数据固定或离散的非对称传输场景，例如：

• 大块连续内存到固定地址块：源端配置为连续地址模式，连续读取庞大的数据缓冲区；目的端配置为自动重载模式，始终向固定的地址块写入数据。

• 离散内存到大块连续内存：源端配置为链表模式，从离散地址块读取数据；目的端配置为连续地址模式，将接收的多个数据块依次拼接到一段连续的大内存中。

连续地址块模式示意图如下：

源端自动重载/目的端连续地址

源端或目的端是否采用连续地址块模式，由控制寄存器（ CTLx_L ）中的链表使能位与配置寄存器（ CFGx_L ）中的自动重载使能位共同决定。

要将某一端（源端或目的端）配置为连续地址模式，必须同时禁用该端的链表更新和自动重载功能：

• 配置源端为连续地址：

  • 禁用源端链表更新：清除 CTLx_L.LLP_SRC_EN

  • 禁用源端自动重载：清除 CFGx_L.RELOAD_SRC

• 配置目的端为连续地址：

  • 禁用目的端链表更新：清除 CTLx_L.LLP_DST_EN

  • 禁用目的端自动重载：清除 CFGx_L.RELOAD_DST

小心

不能同时将 SARx 和 DARx 的更新方式都配置为连续地址块。如果应用需要源端和目的端在块间同时连续，可采用以下方法：

• 增大单块传输大小：配置 CTLx_H.BLOCK_TS，尽量在单个数据块内完成所有数据的传输。

• 使用链表模式：若 CTLx_H.BLOCK_TS 已达到上限，则可以使用链表模式，将下一链表项（LLI）的 LLI.SARx 和 LLI.DARx 显式设置为等于上一数据块结束时的对应结束地址。

块间暂停

• 链表模式：DMA 传输在数据块之间连续执行，不会在块边界停顿。例如，在第 N 个块完成后，DMAC 会直接进入第 N+1 个块的传输。

• 自动重载模式：

  • 如果使能且未屏蔽块结束中断，DMA 会在块结束中断产生后自动暂停，等待软件响应。DMAC 在检测到软件向 ClearBlock[n] 寄存器写入（清除该通道块完成中断）之前，不会启动下一个数据块的传输。

  • 如果中断被禁用（ CTLx_L.INT_EN = 0 ），或块中断被屏蔽（ MaskBlock[n] = 0 ），则 DMA 传输在块之间不会暂停，将直接继续下一个块。

警告

在使用自动重载的多块传输模式时，软件必须在倒数第二个数据块的块传输完成中断服务例程（ISR）中，清除自动重载控制位（ CFGx_L.RELOAD_SRC / CFGx_L.RELOAD_DST ），以防止发生意外的重载和传输。

多块传输终止

源端与目的端具体采用何种更新机制，由链表指针是否为空（ LLP_Lx.LOC = 0）、链表使能位（ CTLx_L.LLP_EN）以及自动重载使能位（ CFGx_L.RELOAD）共同决定。DMAC 共支持 10 种多块传输组合模式，表 传输类型与配置参数位 列出了典型配置。

传输类型与配置参数位

行号	传输类型说明	LLP_Lx.LOC	SRC 链表使能	SRC 自动重载	DST 链表使能	DST 自动重载	状态回写
1	单块传输或多块传输的最后一块（SARx/DARx 由软件重新编程）	0	0	0	0	0	否
2	自动重载：源端自动重载，目的端连续地址	0	0	0	0	1	否
3	自动重载：源端连续地址，目的端自动重载	0	0	1	0	0	否
4	自动重载：源端与目的端均自动重载	0	0	1	0	1	否
5	单块传输或多块传输的最后一块（SARx/DARx 由软件重新编程）	1	0	0	0	0	是
6	链表传输：源端连续地址，目的端链表更新	1	0	0	1	0	是
7	链表传输：源端自动重载，目的端链表更新	1	0	1	1	0	是
8	链表传输：源端链表更新，目的端连续地址	1	1	0	0	0	是
9	链表传输：源端链表更新，目的端自动重载	1	1	0	0	1	是
10	链表传输：源端与目的端均链表更新	1	1	0	1	0	是

表 传输类型与配置参数位 第 1 行或第 5 行列出了传输最后一个数据块（单个数据块或者多数据块）时的寄存器状态。根据起始模式的不同，终止路径有严格要求：

• 行 2、3、4 发起的传输：只能以第 1 行的寄存器状态结束。此状态禁用对最后一个数据块的状态获取与回写。

• 行 6 至 10 发起的传输：只能以第 5 行的寄存器状态结束。此状态使能对最后一个数据块的状态获取与回写。

备注

LLP_Lx.LOC 位的采样仅在通道被使能且传输启动时执行一次，该位用于决定整个传输过程中是否使能状态回写行为。对于同一次多块传输，在后续数据块阶段对该位的修改不会产生任何硬件效果。

基于上述规则，针对不同模式的终止操作如下：

• 终止自动重载：当 LLP_Lx.LOC = 0 且源端或目的端使能了自动重载时，多块 DMA 传输会持续执行。软件需要在处理倒数第二个数据块的 ISR 中，同时将 CFGx_L.RELOAD_SRC 和 CFGx_L.RELOAD_DST 清零，使得下一块的寄存器状态符合表格第 1 行，从而在该块完成时结束传输。

• 终止链表传输：软件需在系统内存中为最后一个数据块的链表项设置合适的 LLI.CTLx_L，确保其中的 LLI.CTLx_L.LLP_SRC_EN 和 LLI.CTLx_L.LLP_DST_EN 均为 0，以便符合表格第 5 行状态，在该块完成时终止传输。

合法状态切换： 配置表格中唯一允许的寄存器状态转换，是从任意一行切换到第 1 行或第 5 行（用于终止 DMA 传输）。不允许在其他任意两行之间直接切换。例如，如果数据块 N 的配置处于第 10 行，则数据块 N+1 仅允许继续保持第 10 行，或切换到第 5 行；若通过修改寄存器直接切换到第 8 行或其他行，均被视为非法配置。

分散/聚集（Scatter/Gather）

Scatter/Gather 是在同一个数据块内部，按照固定的规律（步长 SGI/DSI 和计数 SGC/DSC）跳跃传输数据，常用于 2D 图像裁剪、矩阵转置、固定步长的音频通道分离等。

Scatter

Scatter 与目的端传输相关。当达到 Scatter 边界时，目的端地址按编程量递增 —— Scatter 增量。

图 目的端 Scatter 传输示例 显示了一个目的端 Scatter 传输示例。当达到 Scatter 边界时，目的端地址按目的端 Scatter 增量（ DSRx_L.DSI ）乘以单次 AXI 传输位宽（ CTLx_L.DST_TR_WIDTH 的解码值）递增。用户可以通过编程 DSRx_L 寄存器中的 DSC 字段，来设定连续 Scatter 边界之间的传输次数。

通过将 1 写入 CTLx_L.DST_SCATTER_EN 字段来使能 Scatter。 CTLx_L.DINC 字段确定地址是递增还是保持固定。如果 CTLx_L.DINC 字段指示在整个 DMA 传输期间地址保持固定，则 CTLx_L.DST_SCATTER_EN 字段将被忽略，并且 Scatter 功能将自动禁用。

目的端 Scatter 传输示例

DST_TR_WIDTH = 3'b011 (64 bit = 8 bytes)
DSRx_L.DSI = 0x16
DSRx_L.DSC = 0x04 (destination scatter count)
CTLx_L.DST_SCATTER_EN = 1 (destination scatter enabled)
DARx = A0 (starting Destination address)

Gather

Gather 与源端传输相关。当达到 Gather 边界时，源端地址按编程量递增。

连续 Gather 边界之间的源端传输数量被编程到源端 Gather 计数字段中（ SGRx_L.SGC ）。

当达到 Gather 边界时，源端地址按上述增量递增。

通过将 1 写入 CTLx_L.SRC_GATHER_EN 字段来使能 Gather。 CTLx_L.SINC 字段确定当达到 Gather 边界时地址是递增还是保持固定。如果 CTLx_L.SINC 字段指示在整个 DMA 传输期间固定地址控制，则 CTLx_L.SRC_GATHER_EN 字段将被忽略，并且 Gather 功能将自动禁用。

图 源端 Gather 传输示例 显示了一个源端 Gather 传输示例。连续 Gather 边界之间的源端传输数量被编程到源端 Gather 计数字段中。源端地址增量 = SGRx_L.SGI × SRC_TR_WIDTH（字节）。

当达到 Gather 边界时，源端地址按上述增量递增。

源端 Gather 传输示例

SRC_TR_WIDTH = 3'b010 (32 bit)
SGRx_L.SGI = 0x01
SGRx_L.SGC = 0x04 (source gather count)
CTLx_L.SRC_GATHER_EN = 1 (source gather enabled)
SARx = A0 (starting source address)

通常，如果起始地址是 A0 且 CTLx_L.SINC = 2'b00 （增量源端地址控制），则传输将是：

• A0 ， A0 + TWB ， A0 + 2*TWB ....... (A0 + (SGRx_L.SGC - 1) * TWB)

• <-gather_increment-> (A0 + (SGRx_L.SGC * TWB) + (SGRx_L.SGI * TWB))

其中 TWB 是传输宽度（字节）， CTLx_L.SRC_TR_WIDTH / 8 的解码值 = src_single_size_bytes。

备注

对于多块传输，跟踪到达 Gather/Scatter 边界所需的传输数量的计数器在每个数据块传输开始时重新初始化为源端 Gather 计数（ SGRx_L.SGC ）和目的端 Scatter 计数（ DSRx_L.DSC ）。

安全模式

DMAC 完全兼容系统的安全隔离架构（如 ARM TrustZone）。它允许将特定通道配置为安全通道，用于执行受保护内存或外设区域之间的数据传输，同时防止非安全域越权访问。

在标准的隔离机制下，如果非安全的 DMA 通道尝试访问受保护的安全内存或外设，系统级防火墙会拦截该操作：读取操作通常会返回总线错误或无效数据，而写入事务将被直接丢弃。

只有在配置寄存器中为该通道明确分配了安全权限，DMAC 才会以安全属性发起访问，从而合法通过系统的安全检查节点。

安全 DMA 传输的标准工作流程如下：

备注

以下配置必须在 CPU 的安全状态（Secure State）下执行，处于非安全状态的 CPU 尝试访问 DMAC 的安全受控寄存器将被硬件拒绝。

1. 在指定通道的配置寄存器中，将安全访问位设置为 0，为该通道赋予安全读写权限。

2. 使能 DMAC 通道以启动数据传输。

3. 等待 DMA 传输自然完成或响应中断。传输结束后，DMAC 硬件会自动将该通道的使能位清零。

4. 基于安全最小权限原则，当该通道不再需要传输安全数据时，软件应主动将该安全访问位恢复为默认值（非安全），撤销其安全权限，防止该通道被恶意代码利用。

通道暂停与禁用

在正常操作下，软件通过向通道使能寄存器（CHENREG_L/H.CH_EN）写入 1 来启动通道，传输完成后，硬件会自动清零该位以禁用通道。如果软件需要在传输自然完成前介入，DMAC 提供了安全暂停与异常终止两种机制。

暂停并取消传输

为避免数据丢失或总线死锁，在提前禁用通道时，强烈推荐使用 CFGx_L.CH_SUSP 与 CFGx_L.INACTIVE 标志配合的安全流程：

1. 触发暂停：向 CFGx_L.CH_SUSP 写入 1。DMAC 将停止从源端获取新数据，通道 FIFO 不再接收新输入。

2. 等待排空：轮询 CFGx_L.INACTIVE 位直至其置 1，表明通道 FIFO 已空且总线上的当前事务已结束。

   备注

   若使用外设硬件握手传输，外设必须保持握手信号（ dma_req / dma_single ）有效，直到 INACTIVE 置位，以确保 DMAC 完成当前暂停时的握手动作。

3. 禁用通道： INACTIVE 置位后，软件向 CHENREG_L/H.CH_EN 写入 0 以安全禁用通道。硬件会自动将 CH_SUSP 清零。（若 INACTIVE 未置位，写入 0 的操作将被硬件忽略）。

4. 清理状态：通道禁用后，软件必须手动清除该通道的所有中断状态位。

备注

执行“暂停-取消”流程后，除 CH_SUSP 外的所有通道寄存器均保持原值。软件只需重新置位 CH_EN 即可再次启动相同的传输。

暂停后恢复传输

如果在禁用通道（即清除 CH_EN ）之前，软件向 CFGx_L.CH_SUSP 重新写入 0，通道将退出暂停状态。DMA 会从暂停点无缝恢复传输，不会丢失任何数据。

数据完整性与读回精度

当 INACTIVE 置位时，FIFO 中可能仍有残留数据。一旦此时禁用通道，残留数据的处理方式及地址寄存器的读回精度取决于传输流向：

• 内存到内存 / 外设到内存：不会丢失数据。DMAC 会确保将 FIFO 中的剩余数据写入目的内存。暂停并禁用后， CURR_SARx 、 CURR_DARx 和 CTLx_H 的读回值是精确的。

• 内存到外设 / 外设到外设：FIFO 中的剩余数据可能会丢失。暂停时若目的端外设无法接收更多数据（如未置位握手信号），DMAC 无法写出并会直接丢弃 FIFO 中的残留数据。暂停并禁用后， CTLx_H 的读回值精确，但 CURR_SARx 和 CURR_DARx （针对固定地址）的读回值不精确。

异常传输终止

软件可通过强制清除使能位瞬间终止传输，但必须严格遵守轮询机制并承担相应副作用。

警告

• 若硬件配置未开启暂停功能（Suspend Feature），则在通道使能期间严禁向 CH_EN 写入 0。

操作方式包括清除单个通道的 CHENREG_L/H.CH_EN，或清除 DMAC 配置寄存器中的全局使能位。发出禁用请求后，软件必须轮询读回 0 才能确认通道被彻底关闭，因为 DMAC 必须完成总线上正在处理的 AXI 响应。

异常终止的副作用：

1. 数据永久截断：强制禁用时 FIFO 中的数据将被丢弃。对于读取敏感型源端外设（如 FIFO），会导致实质性数据丢失。

2. 握手中断：被强行禁用的通道可能无法向处于活动状态的事务发送硬件确认信号。

3. 突发限制：若通道配置为定长突发（ DMAC_INCR_BURSTS = 0 ），则不支持在传输完成前通过软件强行禁用通道。

编程示例

必须对三个寄存器（LLP_Lx、CTL_L/Hx 和 CFG_L/Hx）进行编程，以确定执行单块还是多块传输，以及使用哪种类型的多块传输。不同的传输类型如 传输类型与配置参数位 所示。

“更新方法”列表明了在使能多块 DMAC 传输时，下一次数据块传输的 SARx、CURR_SARx、DARx、CURR_DARx、CTL_L/Hx 和 LLP_Lx 寄存器的值是从何处获取的。

备注

在 传输类型与配置参数位 中，除规定配置外，LLP_Lx 的 LOC = 0、CTLx_L 的 LLP_SRC_EN、CFGx_L 的 RELOAD_SRC、CTLx_L 的 LLP_DST_EN 和 CFGx_L 的 RELOAD_DST 的所有其他组合均是非法的，会导致不确定或错误的系统行为。

单块传输

本节描述了单块传输的编程步骤，对应 传输类型与配置参数位 中的第 1 行。

备注

传输类型与配置参数位 中的第 5 行也是一种单块传输，但在单块传输结束时使能了控制和状态信息的写回功能。

1. 读取通道使能寄存器以选择一个空闲（禁用）的通道。

2. 通过向中断清除寄存器（CLEARTFR_L/H、CLEARBLOCK_L/H 和 CLEARERR_L/H）写入数据，清除该通道上来自上一次 DMA 传输的任何挂起中断。读取中断原始状态和中断状态寄存器可确认所有中断已成功清除。

3. 对以下通道寄存器进行编程：

   1. 将起始源端地址写入通道 x 的 SARx 寄存器。

   2. 将起始目的端地址写入通道 x 的 DARx 寄存器。

   3. 根据 传输类型与配置参数位 中所示的第 1 行配置，对 CTL_L/Hx 和 CFG_L/Hx 进行编程。将 LLP_Lx 寄存器编程为 0。

   4. 将 DMA 传输的控制信息写入通道 x 的 CTL_L/Hx 寄存器。例如：

      • 通过编程 CTLx_L 的 TT_FC 字段，设置传输类型（源端和目的端是内存还是外设）以及流控设备。

      • 设置传输特性：

        • 在 SRC_TR_WIDTH 字段中设置源端的传输位宽。

        • 在 DST_TR_WIDTH 字段中设置目的端的传输位宽。

        • 在 SINC 字段中配置源端地址为递增、递减或固定地址。

        • 在 DINC 字段中配置目的端地址为递增、递减或固定地址。

   5. 将通道配置信息写入通道 x 的 CFG_L/Hx 寄存器：

      • 为源端和目的端外设指定硬件握手接口类型（内存传输不需要）。这需要对 HS_SEL_SRC / HS_SEL_DST 位进行编程。写入 0 激活硬件握手接口；写入 1 表示由软件触发握手（当前芯片不支持软件握手模式）。

      • 如果激活了硬件握手接口，则通过编程 SRC_PER 和 DEST_PER 位将其分配给相应的外设。

   6. 如果使能了 Gather 功能（硬件宏开启且 CTLx_L 的 SRC_GATHER_EN 已使能），请编程 SGR_L/Hx 寄存器。

   7. 如果使能了 Scatter 功能（硬件宏开启且 CTLx_L 的 DST_SCATTER_EN 已使能），请编程 DSR_L/Hx 寄存器。

4. 对选定的通道完成编程后，通过向 CHENREG_L/H 的 CH_EN 写入 1 来使能该通道。确保 DMACFGREG_L/H 寄存器的第 0 位也已使能。

5. 源端和目的端外设请求单次和突发 DMA 事务以传输数据块。DMAC 在每次事务完成时发出确认信号，并执行数据块传输。

6. 传输完成后，硬件会置位相应的中断并禁用该通道。软件可以响应数据块完成或传输完成中断，或者轮询原始中断状态寄存器（RAWTFR[n]）直到其被置位。如果使用轮询方式，软件必须确保在重新使能通道之前，通过向 CLEARTFR[n] 写入数据来清除中断。

多块传输

源端和目的端均使用链表

1. 读取通道使能寄存器以选择一个空闲（禁用）的通道。

2. 在内存中设置链表项（LLI）链。将控制信息写入每个 LLI 链表项（LLI）的 LLI.CTL_L/Hx 寄存器位置。例如：

   • 在 CTLx_L 的 TT_FC 字段中设置传输类型和流控设备。

   • 设置传输特性（SRC_TR_WIDTH、DST_TR_WIDTH、SINC、DINC）。

3. 将通道配置信息写入 CFG_L/Hx 寄存器：

   1. 指定握手接口类型（HS_SEL_SRC / HS_SEL_DST）。

   2. 如果激活了硬件握手，通过 SRC_PER 和 DEST_PER 分配握手接口。

4. 确保所有链表项（最后一个除外）的 CTLx_L 寄存器位置如 传输类型与配置参数位 的第 10 行所示进行配置。最后一个 LLI 必须按第 1 行或第 5 行描述进行配置。

   图 源端和目的端均使用链表 展示了一个包含两个 LLI 的链表示例。

   

   源端和目的端均使用链表

5. 确保所有链表项（最后一个除外）的 LLP_Lx 寄存器位置不为零，并指向下一个 LLI 的基地址。

6. 确保所有链表项的 LLI.SARx / LLI.DARx 寄存器位置指向该次 LLI 获取之前的源端/目的端数据块起始地址。

7. 如果使能了 Gather，请编程 SGR_L/Hx 寄存器。

8. 如果使能了 Scatter，请编程 DSR_L/Hx 寄存器。

9. 清除该通道上的任何挂起中断。

10. 根据第 10 行对 CTL_L/Hx 和 CFG_L/Hx 寄存器进行编程。

11. 将指向第一个 LLI 的指针编程到 LLP_Lx 寄存器中。

12. 通过向 CHENREG_L/H 的 CH_EN 写入 1 来使能通道。

13. DMAC 获取第一个 LLI。

备注

DMAC 会根据 LLI 数据自动重新编程 SARx、DARx、LLP_Lx 和 CTL_L/Hx 通道寄存器。

14. DMAC 根据请求执行数据块传输。

15. DMAC 不会等待数据块中断被清除，而是立即继续获取下一个 LLI。DMA 传输持续进行，直到检测到与第 1 行或第 5 行匹配的 LLI（表明这是最后一个数据块）。

源端和目的端地址均自动重载

1. 读取通道使能寄存器以选择一个可用的（禁用）通道。

2. 清除通道上的任何挂起中断。

3. 对以下通道寄存器进行编程：

   1. 将起始源端和目的端地址写入 SARx 和 DARx。

   2. 根据第 4 行配置 CTL_L/Hx 和 CFG_L/Hx。将 LLP_Lx 编程为 0。

   3. 将控制信息写入 CTL_L/Hx（传输类型、位宽、Scatter/Gather 配置）。

   4. 将通道配置写入 CFG_L/Hx。确保已使能重载位 CFGx_L 的 RELOAD_SRC 和 RELOAD_DST。

   5. 根据需要配置握手接口。

4. 通过向 CHENREG_L/H 的 CH_EN 写入 1 使能通道。确保已使能 DMACFGREG_L/H 的第 0 位。

5. DMAC 执行数据块传输。

6. 当数据块传输完成时，DMAC 会重载 SARx、DARx 和 CTL_L/Hx。硬件随后置位数据块完成中断。如果 DMAC 转换至第 1 行配置，则整体传输完成。

7. 如果 DMAC 未进入第 1 行，则传输按如下方式进行：

   • 如果中断已使能且数据块完成中断未被屏蔽：硬件将停顿，直到软件清除该中断。如果下一个数据块是最后一个，ISR 应清除 CFGx_L 的 RELOAD_SRC 和 RELOAD_DST 以使 DMAC 进入第 1 行。

   • 如果中断被禁用或被屏蔽：硬件不会停顿并立即开始下一个数据块的传输。软件必须在最后一块传输完成前主动清除重载位，以确保进入第 1 行。

   该传输行为与图 源端和目的端地址均自动重载 中所示类似。

   

   源端和目的端地址均自动重载

源端自动重载 & 目的端使用链表

1. 读取通道使能寄存器以选择一个空闲通道。

2. 在内存中设置 LLI 链。编程 LLI.CTL_L/Hx 寄存器（传输类型、位宽、地址递增等）。

3. 将起始源端地址写入 SARx 寄存器。

   备注

   虽然 DMAC 会获取内存中 LLI.SARx 位置的值，但这些值将被忽略。

4. 将通道配置写入 CFG_L/Hx 寄存器（握手类型和外设分配）。

5. 确保 LLI 中的所有 CTLx_L 位置（最后一个除外）符合第 7 行的配置。最后一个 LLI 必须符合第 1 行或第 5 行。

6. 确保所有 LLP_Lx 位置（最后一个除外）均指向下一个 LLI。

7. 确保 LLI 中的所有 DARx 位置指向起始目的端数据块地址。

8. 如果使能，请编程 Scatter/Gather 配置。

9. 清除挂起的中断。

10. 根据第 7 行对 CTL_L/Hx 和 CFG_L/Hx 寄存器进行编程。

11. 将指向第一个 LLI 的指针编程到 LLP_Lx 寄存器中。

12. 通过 CHENREG_L/H 的 CH_EN 使能通道。

13. DMAC 获取第一个 LLI 并启动传输。

14. 数据块传输完成后，SARx 会自动重载为其初始值。

15. 根据中断配置，软件必须在适当时机清除 CFGx_L 的 RELOAD_SRC 位，以将 DMAC 转换为第 1 行以进行最后一块的传输。

16. DMAC 获取下一个 LLI，更新 DARx、CTL_L/Hx 和 LLP_Lx。SARx 寄存器则使用重载后的值。

该传输行为与图 源端自动重载 & 目的端使用链表 中所示类似。

源端自动重载 & 目的端使用链表

源端自动重载 & 目的端地址连续

1. 读取通道使能寄存器以选择一个空闲通道。

2. 清除任何挂起的中断。

3. 编程通道寄存器：

   1. 将起始地址写入 SARx 和 DARx。

   2. 根据第 3 行编程 CTL_L/Hx 和 CFG_L/Hx。将 LLP_Lx 编程为 0。

   3. 配置传输类型、位宽和流控。如果使能，请设置 Scatter/Gather。

   4. 在 CFG_L/Hx 中配置握手设置。

4. 通过 CHENREG_L/H 的 CH_EN 使能通道。

5. DMAC 执行数据块传输。

6. 传输完成后，DMAC 重载 SARx 寄存器；DARx 寄存器保持连续（即重载值未更改）。

7. DMA 传输根据配置的中断设置继续进行。软件必须在最后一块之前清除 CFGx_L 的 RELOAD_SRC 位，以便转换至第 1 行并正确终止传输序列。

   DMA 传输序列可能如图 源端自动重载 & 目的端地址连续 中所示。

   

   源端自动重载 & 目的端地址连续

源端使用链表 & 目的端地址连续

1. 读取通道使能寄存器以选择一个空闲通道。

2. 在内存中设置链表结构。相应地编程 LLI.CTLx_L 寄存器。

3. 将起始目的端地址写入 DARx 寄存器。

   备注

   虽然 DMAC 会获取内存中 LLI.DARx 位置的值，但这些值将被忽略。

4. 将通道配置写入 CFG_L/Hx（握手设置）。

5. 确保 LLI 中的所有 CTLx_L 位置（最后一个除外）符合第 8 行配置。

6. 确保 LLP_Lx 位置指向下一个 LLI。

7. 确保 LLI 中的 SARx 位置指向正确的源端数据块地址。

8. 如果使能，请编程 Scatter/Gather 配置。

9. 清除挂起的中断。

10. 根据第 8 行对 CTL_L/Hx 和 CFG_L/Hx 寄存器进行编程。

11. 将指向第一个 LLI 的指针编程到 LLP_Lx 寄存器中。

12. 通过 CHENREG_L/H 的 CH_EN 使能通道。

13. DMAC 获取第一个 LLI。随后 SARx、LLP_Lx 和 CTL_L/Hx 将被更新，而 DARx 保持连续。

14. DMAC 执行传输并自动获取后续的 LLI，直至到达最终的 LLI（配置为第 1 行或第 5 行），从而完成整个 DMA 传输操作。

DMA 传输序列可能如图 源端使用链表 & 目的端地址连续 中所示。

源端使用链表 & 目的端地址连续

寄存器

本节介绍 DMAC 的可编程寄存器。所有寄存器都按 64 位边界对齐，并且为 64 位宽。通常，寄存器的高 32 位被保留。如果没有特殊说明，对寄存器内保留位的写入将被忽略。

备注

• 本章中引用了软件参数和硬件参数。

• 软件参数是每个寄存器描述表中的字段名称，并以寄存器名称为前缀；例如，通道 x 的控制寄存器中的块传输大小字段被指定为 CTL_Hx.BLOCK_TS。

• 硬件参数以 DMAC_* 为前缀，并使用 Realtek coreTools 配置一次。

• 随 RTK_DMAC 组件一起提供的是一个地址定义（内存映射）C 头文件。当在 C 环境中编程 DMAC 时，可以使用此头文件。

RTL8721DxRTL8720ERTL8710ERTL8726ERTL8713ERTL8730ERTL8721FRTL8720F

RTL8721Dx:

Base Address: 0x40110000

Name	Address offset	Access	Description
REG_SAR0	000h	R/W	Source address register for DMA channel x, specifies the source memory address
REG_CURR_SAR0	004h	R	Current source address register for DMA channel x, indicates the current source address during transfer
REG_DAR0	008h	R/W	Destination address register for DMA channel x, specifies the destination memory address
REG_CURR_DAR0	00Ch	R	Current destination address register for DMA channel x, indicates the current destination address during transfer
REG_LLP0_L	010h	R/W	Linked list pointer register low for DMA channel x, points to the starting address of linked list item
REG_CTL0_L	018h	R/W	Control register low for DMA channel x, configures channel control settings
REG_CTL0_H	01Ch	R	Control register high for DMA channel x for block size
REG_CFG0_L	040h	R/W	Configuration register low for DMA channel x, configures transfer parameters
REG_CFG0_H	044h	R/W	Configuration register high for DMA channel x, configures additional transfer parameters
REG_SAR1	058h	R/W	Source address register for DMA channel x, specifies the source memory address
REG_CURR_SAR1	05Ch	R	Current source address register for DMA channel x, indicates the current source address during transfer
REG_DAR1	060h	R/W	Destination address register for DMA channel x, specifies the destination memory address
REG_CURR_DAR1	064h	R	Current destination address register for DMA channel x, indicates the current destination address during transfer
REG_LLP1_L	068h	R/W	Linked list pointer register low for DMA channel x, points to the starting address of linked list item
REG_CTL1_L	070h	R/W	Control register low for DMA channel x, configures channel control settings
REG_CTL1_H	074h	R	Control register high for DMA channel x for block size
REG_CFG1_L	098h	R/W	Configuration register low for DMA channel x, configures transfer parameters
REG_CFG1_H	09Ch	R/W	Configuration register high for DMA channel x, configures additional transfer parameters
REG_SAR2	0B0h	R/W	Source address register for DMA channel x, specifies the source memory address
REG_CURR_SAR2	0B4h	R	Current source address register for DMA channel x, indicates the current source address during transfer
REG_DAR2	0B8h	R/W	Destination address register for DMA channel x, specifies the destination memory address
REG_CURR_DAR2	0BCh	R	Current destination address register for DMA channel x, indicates the current destination address during transfer
REG_LLP2_L	0C0h	R/W	Linked list pointer register low for DMA channel x, points to the starting address of linked list item
REG_CTL2_L	0C8h	R/W	Control register low for DMA channel x, configures channel control settings
REG_CTL2_H	0CCh	R	Control register high for DMA channel x for block size
REG_CFG2_L	0F0h	R/W	Configuration register low for DMA channel x, configures transfer parameters
REG_CFG2_H	0F4h	R/W	Configuration register high for DMA channel x, configures additional transfer parameters
REG_SAR3	108h	R/W	Source address register for DMA channel x, specifies the source memory address
REG_CURR_SAR3	10Ch	R	Current source address register for DMA channel x, indicates the current source address during transfer
REG_DAR3	110h	R/W	Destination address register for DMA channel x, specifies the destination memory address
REG_CURR_DAR3	114h	R	Current destination address register for DMA channel x, indicates the current destination address during transfer
REG_LLP3_L	118h	R/W	Linked list pointer register low for DMA channel x, points to the starting address of linked list item
REG_CTL3_L	120h	R/W	Control register low for DMA channel x, configures channel control settings
REG_CTL3_H	124h	R	Control register high for DMA channel x for block size
REG_CFG3_L	148h	R/W	Configuration register low for DMA channel x, configures transfer parameters
REG_CFG3_H	14Ch	R/W	Configuration register high for DMA channel x, configures additional transfer parameters
REG_SAR4	160h	R/W	Source address register for DMA channel x, specifies the source memory address
REG_CURR_SAR4	164h	R	Current source address register for DMA channel x, indicates the current source address during transfer
REG_DAR4	168h	R/W	Destination address register for DMA channel x, specifies the destination memory address
REG_CURR_DAR4	16Ch	R	Current destination address register for DMA channel x, indicates the current destination address during transfer
REG_LLP4_L	170h	R/W	Linked list pointer register low for DMA channel x, points to the starting address of linked list item
REG_CTL4_L	178h	R/W	Control register low for DMA channel x, configures channel control settings
REG_CTL4_H	17Ch	R	Control register high for DMA channel x for block size
REG_CFG4_L	1A0h	R/W	Configuration register low for DMA channel x, configures transfer parameters
REG_CFG4_H	1A4h	R/W	Configuration register high for DMA channel x, configures additional transfer parameters
REG_SAR5	1B8h	R/W	Source address register for DMA channel x, specifies the source memory address
REG_CURR_SAR5	1BCh	R	Current source address register for DMA channel x, indicates the current source address during transfer
REG_DAR5	1C0h	R/W	Destination address register for DMA channel x, specifies the destination memory address
REG_CURR_DAR5	1C4h	R	Current destination address register for DMA channel x, indicates the current destination address during transfer
REG_LLP5_L	1C8h	R/W	Linked list pointer register low for DMA channel x, points to the starting address of linked list item
REG_CTL5_L	1D0h	R/W	Control register low for DMA channel x, configures channel control settings
REG_CTL5_H	1D4h	R	Control register high for DMA channel x for block size
REG_CFG5_L	1F8h	R/W	Configuration register low for DMA channel x, configures transfer parameters
REG_CFG5_H	1FCh	R/W	Configuration register high for DMA channel x, configures additional transfer parameters
REG_SAR6	210h	R/W	Source address register for DMA channel x, specifies the source memory address
REG_CURR_SAR6	214h	R	Current source address register for DMA channel x, indicates the current source address during transfer
REG_DAR6	218h	R/W	Destination address register for DMA channel x, specifies the destination memory address
REG_CURR_DAR6	21Ch	R	Current destination address register for DMA channel x, indicates the current destination address during transfer
REG_LLP6_L	220h	R/W	Linked list pointer register low for DMA channel x, points to the starting address of linked list item
REG_CTL6_L	228h	R/W	Control register low for DMA channel x, configures channel control settings
REG_CTL6_H	22Ch	R	Control register high for DMA channel x for block size
REG_CFG6_L	250h	R/W	Configuration register low for DMA channel x, configures transfer parameters
REG_CFG6_H	254h	R/W	Configuration register high for DMA channel x, configures additional transfer parameters
REG_SAR7	268h	R/W	Source address register for DMA channel x, specifies the source memory address
REG_CURR_SAR7	26Ch	R	Current source address register for DMA channel x, indicates the current source address during transfer
REG_DAR7	270h	R/W	Destination address register for DMA channel x, specifies the destination memory address
REG_CURR_DAR7	274h	R	Current destination address register for DMA channel x, indicates the current destination address during transfer
REG_LLP7_L	278h	R/W	Linked list pointer register low for DMA channel x, points to the starting address of linked list item
REG_CTL7_L	280h	R/W	Control register low for DMA channel x, configures channel control settings
REG_CTL7_H	284h	R	Control register high for DMA channel x for block size
REG_CFG7_L	2A8h	R/W	Configuration register low for DMA channel x, configures transfer parameters
REG_CFG7_H	2ACh	R/W	Configuration register high for DMA channel x, configures additional transfer parameters
REG_RAWTFR_L	2C0h	R	Raw transfer complete interrupt status register, shows unmasked transfer complete interrupts
REG_RAWBLOCK_L	2C8h	R	Raw block transfer complete interrupt status register, shows unmasked block transfer complete interrupts
REG_RAWERR_L	2E0h	R	Raw error interrupt status register low, shows unmasked protocol error interrupts
REG_RAWERR_H	2E4h	R	Raw error interrupt status register high, shows unmasked secure error interrupts
REG_STATUSTFR_L	2E8h	R	Transfer complete interrupt status register, shows masked transfer complete interrupts
REG_STATUSBLOCK_L	2F0h	R	Block transfer complete interrupt status register, shows masked block transfer complete interrupts
REG_STATUSERR_L	308h	R	Error interrupt status register low, shows masked protocol error interrupts
REG_STATUSERR_H	30Ch	R	Error interrupt status register high, shows masked secure error interrupts
REG_MASKTFR_L	310h	R/W	Transfer complete interrupt mask register, enables or disables transfer complete interrupts
REG_MASKBLOCK_L	318h	R/W	Block transfer complete interrupt mask register, enables or disables block transfer complete interrupts
REG_MASKERR_L	330h	R/W	Error interrupt mask register low, enables or disables protocol error interrupts
REG_MASKERR_H	334h	R/W	Error interrupt mask register high, enables or disables secure error interrupts
REG_CLEARTFR_L	338h	R/W	Transfer complete interrupt clear register, clears transfer complete interrupt status
REG_CLEARBLOCK_L	340h	R/W	Block transfer complete interrupt clear register, clears block transfer complete interrupt status
REG_CLEARERR_L	358h	R/W	Error interrupt clear register low, clears protocol error interrupt status
REG_CLEARERR_H	35Ch	R/W	Error interrupt clear register high, clears secure error interrupt status
REG_STATUSINT_L	360h	R	Interrupt status register low, shows combined interrupt status
REG_STATUSINT_H	364h	R	Interrupt status register high, shows combined interrupt status
REG_DMACFGREG_L	398h	R/W	DMA configuration register, configures global DMA controller settings
REG_CHENREG_L_1	3A0h	R/W	Channel enable register, enables or disables DMA channels
REG_DMAIDREG_L	3A8h	R	DMA ID register, Hardcoded RTK_DMAC peripheral ID
REG_DMA_COMP_PARAMS_6_L	3C8h	R	DMA component parameters register 6 low, contains component identification information
REG_DMA_COMP_PARAMS_6_H	3CCh	R	DMA component parameters register 6 high, contains component identification information
REG_DMA_COMP_PARAMS_5_L	3D0h	R	DMA component parameters register 5 low, contains component identification information
REG_DMA_COMP_PARAMS_5_H	3D4h	R	DMA component parameters register 5 high, contains component identification information
REG_DMA_COMP_PARAMS_4_L	3D8h	R	DMA component parameters register 4 low, contains component identification information
REG_DMA_COMP_PARAMS_4_H	3DCh	R	DMA component parameters register 4 high, contains component identification information
REG_DMA_COMP_PARAMS_3_L	3E0h	R	DMA component parameters register 3 low, contains component identification information
REG_DMA_COMP_PARAMS_3_H	3E4h	R	DMA component parameters register 3 high, contains component identification information
REG_DMA_COMP_PARAMS_2_L	3E8h	R	DMA component parameters register 2 low, contains component identification information
REG_DMA_COMP_PARAMS_2_H	3ECh	R	DMA component parameters register 2 high, contains component identification information
REG_DMA_COMP_PARAMS_1_L	3F0h	R	DMA component parameters register 1 low, contains component identification information
REG_DMA_COMP_PARAMS_1_H	3F4h	R	DMA component parameters register 1 high, contains component identification information
REG_DMA_COMPONENT_ID_REGS_L	3F8h	R	DMA component ID register low, identifies the DMA controller release date
REG_DMA_COMPONENT_ID_REGS_H	3FCh	R	DMA component ID register high, identifies the DMA controller rtl version

REG_SAR0

• Name: Channel 0 Source Address Register

• Size: 32

• Address offset: 000h

• Read/write access: R/W

Source address register for DMA channel x, specifies the source memory address

Bit	Symbol	Access	INI	Description
31:0	SAR0	R/W	Unknown	Source Address of DMA transfer.Updated after each source transfer. The SINC field in the CTLx register determines whether the address increments, or is left unchanged on every source transfer throughout the block transfer.

REG_CURR_SAR0

• Name: The read back value is channel 0 source reading address at present

• Size: 32

• Address offset: 004h

• Read/write access: R

Current source address register for DMA channel x, indicates the current source address during

transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_SAR0	R	0x0	The read back value is source reading address at present

REG_DAR0

• Name: Channel 0 Destination Address Register

• Size: 32

• Address offset: 008h

• Read/write access: R/W

Destination address register for DMA channel x, specifies the destination memory address

Bit	Symbol	Access	INI	Description
31:0	DAR0	R/W	Unknown	Destination address of DMA transfer.Updated after each destination transfer. The DINC field in the CTLx register determines whether the address increments, or is left unchanged on every destination transfer throughout the block transfer.

REG_CURR_DAR0

• Name: The read back value is channel 0 destination writing address at present

• Size: 32

• Address offset: 00Ch

• Read/write access: R

Current destination address register for DMA channel x, indicates the current destination address

during transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_DAR0	R	0x0	The read back value is destination writing address at present

REG_LLP0_L

• Name: Channel 0 low-32 bits Linked List Pointer Register

• Size: 32

• Address offset: 010h

• Read/write access: R/W

Linked list pointer register low for DMA channel x, points to the starting address of linked list

item

Bit	Symbol	Access	INI	Description
31:2	LLP0_L_LOC	R/W	Unknown	Starting Address In Memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary.LLI accesses are always 32-bit accesses aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit.
1:0	RSVD	R	-	Reserved

REG_CTL0_L

• Name: Channel 0 low-32 bits Control Register

• Size: 32

• Address offset: 018h

• Read/write access: R/W

Control register low for DMA channel x, configures channel control settings

Bit	Symbol	Access	INI	Description
31:29	RSVD	R	-	Reserved
28	CTL0_L_LLP_SRC_EN	R/W	0x0	Block chanining is enabled on the source side only if the LLP_SRC_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
27	CTL0_L_LLP_DST_EN	R/W	0x0	Block chanining is enabled on the destination side only if the LLP_DST_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
26:23	RSVD	R	-	Reserved
22:20	CTL0_L_TT_FC	R/W	0x0	Transfer Type and Flow Control.The following transfer types are supported. Memory to Memory Memory to Peripheral Peripheral to Memory Peripheral to Peripheral Flow Control can be assigned to the RTK_DMAC, the source peripheral, or the destination peripheral. Table 6-4 lists the decoding for this field. For more information on transfer types and flow control, refer to “Setup/Operation of RTK_DMAC Transfers”. Reset Value: 3’h0 Dependencies: If hardware handshake isn’t support, then TT_FC can only be set to 3’b0. TT_FC[2] can only be read.
19	RSVD	R	-	Reserved
18	CTL0_L_DST_SCATTER_EN	R/W	0x0	Destination scatter enable bit:0 = Scatter disabled1 = Scatter enabledScatter on the destination side is applicable only when the CTLx_L.DINC bit indicates an incrementing address control and DARx should be aligned with DST_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_DST_SCA_EN is not selected.
17	CTL0_L_SRC_GATHER_EN	R/W	0x0	Source gather enable bit: 0 = Gather disabled 1 = Gather enabled Gather on the source side is applicable only when the CTLx_L.SINC bit indicates an incrementing address control and SARx should be aligned with SRC_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_SRC_GAT_EN is not selected.
16:14	CTL0_L_SRC_MSIZE	R/W	0x1	Source Burst Transaction Length. Number of data items, each of width CTLx_L.SRC_TR_WIDTH if source is not memory, otherwise each of width DMAC_TR_WIDTH_DEFAULT, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface. Read burst transaction length on bus (ARLen) will not exceed this value, but may be less than this value. If SINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-0 lists the decoding for this field.
13:11	CTL0_L_DEST_MSIZE	R/W	0x1	Destination Burst Transaction Length. Number of data items, each of width DATA_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. Write burst transaction length on bus (AWLen) will not exceed this value, but may be less than this value. If DINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-1 lists the decoding for this field.
10:9	CTL0_L_SINC	R/W	0x0	Source Address Increment. Indicates whether to increment the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to “No change.”If source is memory appointed by CTLx_L.TT_FC, and set SINC=No change, then SRC_TR_WIDTH must be set to BUS width. And DMAC will read data from the fixed memory address until block transfer finish, but It is not recommended to read memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01 =Not support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.SRC_TR_WIDTH boundary.
8:7	CTL0_L_DINC	R/W	0x0	Destination Address Increment. Indicates whether to increment destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change.”If destination is memory appointed by CTLx_L.TT_FC, and set DINC=No change, then DST_TR_WIDTH must be set to BUS width. And DMAC will write data to the fixed memory address until block transfer finish, but It is not recommended to write memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01=Not Support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.DST_TR_WIDTH boundary.
6:4	CTL0_L_SRC_TR_WIDTH	R/W	0x0	Source Transfer Width. Table 6-3 lists the decoding for this field.It can’t be mapped to AXI bus data width directly. Since AXI bus data width is fixed (such as 32bit/64bit), AXI use byte enable signal for byte/half word transfer (still burst). So, the SRC_TR_WIDTH is only used for total block data size calculation and streaming mode byte/half word transfer (for FIFO transfer). 备注 SRC_TR_WIDTH must not be bigger than BUS width.
3:1	CTL0_L_DST_TR_WIDTH	R/W	0x0	Destination Transfer Width.Table 6-3 lists the decoding for this field. It can’t be mapped to AXI bus data width directly. For a non-memory peripheral, typically the peripheral (destination) FIFO width.Note: DST_TR_WIDTH must not be bigger than BUS width
0	CTL0_L_INT_EN	R/W	0x1	Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel; raw* interrupt registers still assert if CTLx_L.INT_EN = 0.

REG_CTL0_H

• Name: Channel 0 high-32 bits Control Register

• Size: 32

• Address offset: 01Ch

• Read/write access: R

Control register high for DMA channel x for block size

Bit	Symbol	Access	INI	Description
31:0	CTL0_H_TRANS_DATA_CNT	R	0x0	Data Transfered Count.Once the transfer starts, the read-back value is the total number of data bytes already write to destination memory or peripheral.

REG_CFG0_L

• Name: Channel 0 low-32 bits Configuration Register

• Size: 32

• Address offset: 040h

• Read/write access: R/W

Configuration register low for DMA channel x, configures transfer parameters

Bit	Symbol	Access	INI	Description
31	CFG0_L_RELOAD_DST	R/W	0x0	Automatic Destination Reload. The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.This register does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
30	CFG0_L_RELOAD_SRC	R/W	0x0	Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. This field does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
29:20	RSVD	R	-	Reserved
19	CFG0_L_SRC_HS_POL	R/W	0x0	Source Handshaking Interface Polarity. 0 = Active high 1 = Active low
18	CFG0_L_DST_HS_POL	R/W	0x0	Destination Handshaking Interface Polarity. 0 = Active high 1 = Active low For information on this, refer to “Handshaking Interface” .
17:12	RSVD	R	-	Reserved
11	CFG0_L_HS_SEL_SRC	R/W	0x1	Source Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for source requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware-initiated transaction requests are ignored. If the source peripheral is memory, then this bit is ignored.
10	CFG0_L_HS_SEL_DST	R/W	0x1	Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for destination requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware- initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored.
9	CFG0_L_FIFO_EMPTY	R	0x1	Indicates if there is data left in the channel FIFO. 1 = Channel FIFO empty 0 = Channel FIFO not empty
8	CFG0_L_CH_SUSP	R/W	0x0	Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx_l.INACTIVE to cleanly disable a channel without losing any data. 0 = Not suspended 1 = Suspend DMA transfer from the source. This field will be reset to 0 after “Disabling a Channel Prior to Transfer Completion” automatically by hardware.For more information, refer to “7.7 Disabling a Channel Prior to Transfer Completion” . 备注 if user not define DMAC_CH*_SUPPORT_SUSPEND, it only can be readed.
7:4	CFG0_L_CH_PRIOR	R/W	0x0	Channel priority. RTK DMAC supports three kinds of channel priority now, fixed priority, round robin priority and programmable priority. The default way is fixed priority to reduce area, and channel0 has the highest priority, channel15 has the lowest priority. Changing the definition of parameter FIX_PRIORITY or Programmable_PRIORITY can change priority way. If RTK DMAC is configured to support Programmable priority, this field will be used to set priority between channels. CH_PRIOR’s legal value is 0 ~ (DMAC_NUM_CHANNELS-1), and 0 is the highest priority value, (DMAC_NUM_CHANNELS-1) is the lowest priroty value. If more than one channel are set with the same priroty value, the channel with small channel number index has higher priority. If DMAC is configured to support fix priority or round-robin priority, this field is not exist. 备注 if user not define ProgrammablePriority, it only can be readed.
3	RSVD	R	-	Reserved
2	CFG0_L_DST_PCTL_OVER	R	0x1	DMA destination bus protocol finish, indicating the current write command has finished.
1	CFG0_L_SRC_PCTL_OVER	R	0x1	DMA Source bus protocol finish, indicating the current read command has finished.
0	CFG0_L_INACTIVE	R	0x1	Indicates if the channel is inactive. Can be used in conjunction with CFGx_L.CH_SUSP to cleanly disable a channel when destination is peripheral. For more information, refer to “Disabling a Channel Prior to Transfer Completion” . 1 = Channel Inactive for axi interface 0 = Channel not Inactive for axi interface

REG_CFG0_H

• Name: Channel 0 high-32 bits Configuration Register

• Size: 32

• Address offset: 044h

• Read/write access: R/W

Configuration register high for DMA channel x, configures additional transfer parameters

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	CFG0_H_EXTENDED_DEST_PER1	R/W	0x0	The extened 4th bit of DEST_PER when hardware handshake interfaces number is configured to 32.
15	CFG0_H_EXTENDED_SRC_PER1	R/W	0x0	The extened 4th bit of SRC_PER when hardware handshake interfaces number is configured to 32.
14:11	CFG0_H_DEST_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the destination of channel x if the FGx.HS_SEL_DST field is 0; otherwise, this field is ignored. The channel can then communicate with the destinationperipheral connected to that interface through the assignedhardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (sourceor destination) should be assigned to the same handshaking interface NOTE2: This field does not exist if the configuration parameterDMAC_NUM_HS_INT is set to 0.
10:7	CFG0_H_SRC_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the source of channel x if the CFGx.HS_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct RTK_DMAC operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. NOTE2: This field does not exist if the configuration parameter DMAC_NUM_HS_INT is set to 0.
6:4	RSVD	R	-	Reserved
3	CFG0_H_PROTCTL	R/W	0x1	Protection Control.Set the bit 35 to 0 will enable the channel secure DMA transfer. Set the bit 35 to 1 will enable the channel non-secure DMAC transfer. 备注 if user not define DMAC_SECURE_MODE, it only can be readed.
2:1	RSVD	R	-	Reserved
0	CFG0_H_FCMODE	R/W	0x0	Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are servied when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs. Data pre-fetching is disabled. 备注 Please keep this bit 0 when Transfer Type and Flow Control is not ”destination peripheral is the flow controller and transfer type is peripheral to peripheral” (TT_FC!=7).

REG_SAR1

• Name: Channel 1 Source Address Register

• Size: 32

• Address offset: 058h

• Read/write access: R/W

Source address register for DMA channel x, specifies the source memory address

Bit	Symbol	Access	INI	Description
31:0	SAR1	R/W	Unknown	Source Address of DMA transfer.Updated after each source transfer. The SINC field in the CTLx register determines whether the address increments, or is left unchanged on every source transfer throughout the block transfer.

REG_CURR_SAR1

• Name: The read back value is channel 1 source reading address at present

• Size: 32

• Address offset: 05Ch

• Read/write access: R

Current source address register for DMA channel x, indicates the current source address during

transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_SAR1	R	0x0	The read back value is source reading address at present

REG_DAR1

• Name: Channel 1 Destination Address Register

• Size: 32

• Address offset: 060h

• Read/write access: R/W

Destination address register for DMA channel x, specifies the destination memory address

Bit	Symbol	Access	INI	Description
31:0	DAR1	R/W	Unknown	Destination address of DMA transfer.Updated after each destination transfer. The DINC field in the CTLx register determines whether the address increments, or is left unchanged on every destination transfer throughout the block transfer.

REG_CURR_DAR1

• Name: The read back value is channel 1 destination writing address at present

• Size: 32

• Address offset: 064h

• Read/write access: R

Current destination address register for DMA channel x, indicates the current destination address

during transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_DAR1	R	0x0	The read back value is destination writing address at present

REG_LLP1_L

• Name: Channel 1 low-32 bits Linked List Pointer Register

• Size: 32

• Address offset: 068h

• Read/write access: R/W

Linked list pointer register low for DMA channel x, points to the starting address of linked list

item

Bit	Symbol	Access	INI	Description
31:2	LLP1_L_LOC	R/W	Unknown	Starting Address In Memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary.LLI accesses are always 32-bit accesses aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit.
1:0	RSVD	R	-	Reserved

REG_CTL1_L

• Name: Channel 1 low-32 bits Control Register

• Size: 32

• Address offset: 070h

• Read/write access: R/W

Control register low for DMA channel x, configures channel control settings

Bit	Symbol	Access	INI	Description
31:29	RSVD	R	-	Reserved
28	CTL1_L_LLP_SRC_EN	R/W	0x0	Block chanining is enabled on the source side only if the LLP_SRC_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
27	CTL1_L_LLP_DST_EN	R/W	0x0	Block chanining is enabled on the destination side only if the LLP_DST_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
26:23	RSVD	R	-	Reserved
22:20	CTL1_L_TT_FC	R/W	0x0	Transfer Type and Flow Control.The following transfer types are supported. Memory to Memory Memory to Peripheral Peripheral to Memory Peripheral to Peripheral Flow Control can be assigned to the RTK_DMAC, the source peripheral, or the destination peripheral. Table 6-4 lists the decoding for this field. For more information on transfer types and flow control, refer to “Setup/Operation of RTK_DMAC Transfers”. Reset Value: 3’h0 Dependencies: If hardware handshake isn’t support, then TT_FC can only be set to 3’b0. TT_FC[2] can only be read.
19	RSVD	R	-	Reserved
18	CTL1_L_DST_SCATTER_EN	R/W	0x0	Destination scatter enable bit:0 = Scatter disabled1 = Scatter enabledScatter on the destination side is applicable only when the CTLx_L.DINC bit indicates an incrementing address control and DARx should be aligned with DST_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_DST_SCA_EN is not selected.
17	CTL1_L_SRC_GATHER_EN	R/W	0x0	Source gather enable bit: 0 = Gather disabled 1 = Gather enabled Gather on the source side is applicable only when the CTLx_L.SINC bit indicates an incrementing address control and SARx should be aligned with SRC_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_SRC_GAT_EN is not selected.
16:14	CTL1_L_SRC_MSIZE	R/W	0x1	Source Burst Transaction Length. Number of data items, each of width CTLx_L.SRC_TR_WIDTH if source is not memory, otherwise each of width DMAC_TR_WIDTH_DEFAULT, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface. Read burst transaction length on bus (ARLen) will not exceed this value, but may be less than this value. If SINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-0 lists the decoding for this field.
13:11	CTL1_L_DEST_MSIZE	R/W	0x1	Destination Burst Transaction Length. Number of data items, each of width DATA_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. Write burst transaction length on bus (AWLen) will not exceed this value, but may be less than this value. If DINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-1 lists the decoding for this field.
10:9	CTL1_L_SINC	R/W	0x0	Source Address Increment. Indicates whether to increment the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to “No change.”If source is memory appointed by CTLx_L.TT_FC, and set SINC=No change, then SRC_TR_WIDTH must be set to BUS width. And DMAC will read data from the fixed memory address until block transfer finish, but It is not recommended to read memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01 =Not support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.SRC_TR_WIDTH boundary.
8:7	CTL1_L_DINC	R/W	0x0	Destination Address Increment. Indicates whether to increment destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change.”If destination is memory appointed by CTLx_L.TT_FC, and set DINC=No change, then DST_TR_WIDTH must be set to BUS width. And DMAC will write data to the fixed memory address until block transfer finish, but It is not recommended to write memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01=Not Support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.DST_TR_WIDTH boundary.
6:4	CTL1_L_SRC_TR_WIDTH	R/W	0x0	Source Transfer Width. Table 6-3 lists the decoding for this field.It can’t be mapped to AXI bus data width directly. Since AXI bus data width is fixed (such as 32bit/64bit), AXI use byte enable signal for byte/half word transfer (still burst). So, the SRC_TR_WIDTH is only used for total block data size calculation and streaming mode byte/half word transfer (for FIFO transfer). 备注 SRC_TR_WIDTH must not be bigger than BUS width.
3:1	CTL1_L_DST_TR_WIDTH	R/W	0x0	Destination Transfer Width.Table 6-3 lists the decoding for this field. It can’t be mapped to AXI bus data width directly. For a non-memory peripheral, typically the peripheral (destination) FIFO width.Note: DST_TR_WIDTH must not be bigger than BUS width
0	CTL1_L_INT_EN	R/W	0x1	Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel; raw* interrupt registers still assert if CTLx_L.INT_EN = 0.

REG_CTL1_H

• Name: Channel 1 high-32 bits Control Register

• Size: 32

• Address offset: 074h

• Read/write access: R

Control register high for DMA channel x for block size

Bit	Symbol	Access	INI	Description
31:0	CTL1_H_TRANS_DATA_CNT	R	0x0	Data Transfered Count.Once the transfer starts, the read-back value is the total number of data bytes already write to destination memory or peripheral.

REG_CFG1_L

• Name: Channel 1 low-32 bits Configuration Register

• Size: 32

• Address offset: 098h

• Read/write access: R/W

Configuration register low for DMA channel x, configures transfer parameters

Bit	Symbol	Access	INI	Description
31	CFG1_L_RELOAD_DST	R/W	0x0	Automatic Destination Reload. The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.This register does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
30	CFG1_L_RELOAD_SRC	R/W	0x0	Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. This field does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
29:20	RSVD	R	-	Reserved
19	CFG1_L_SRC_HS_POL	R/W	0x0	Source Handshaking Interface Polarity. 0 = Active high 1 = Active low
18	CFG1_L_DST_HS_POL	R/W	0x0	Destination Handshaking Interface Polarity. 0 = Active high 1 = Active low For information on this, refer to “Handshaking Interface” .
17:12	RSVD	R	-	Reserved
11	CFG1_L_HS_SEL_SRC	R/W	0x1	Source Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for source requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware-initiated transaction requests are ignored. If the source peripheral is memory, then this bit is ignored.
10	CFG1_L_HS_SEL_DST	R/W	0x1	Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for destination requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware- initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored.
9	CFG1_L_FIFO_EMPTY	R	0x1	Indicates if there is data left in the channel FIFO. 1 = Channel FIFO empty 0 = Channel FIFO not empty
8	CFG1_L_CH_SUSP	R/W	0x0	Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx_l.INACTIVE to cleanly disable a channel without losing any data. 0 = Not suspended 1 = Suspend DMA transfer from the source. This field will be reset to 0 after “Disabling a Channel Prior to Transfer Completion” automatically by hardware.For more information, refer to “7.7 Disabling a Channel Prior to Transfer Completion” . 备注 if user not define DMAC_CH*_SUPPORT_SUSPEND, it only can be readed.
7:4	CFG1_L_CH_PRIOR	R/W	0x0	Channel priority. RTK DMAC supports three kinds of channel priority now, fixed priority, round robin priority and programmable priority. The default way is fixed priority to reduce area, and channel0 has the highest priority, channel15 has the lowest priority. Changing the definition of parameter FIX_PRIORITY or Programmable_PRIORITY can change priority way. If RTK DMAC is configured to support Programmable priority, this field will be used to set priority between channels. CH_PRIOR’s legal value is 0 ~ (DMAC_NUM_CHANNELS-1), and 0 is the highest priority value, (DMAC_NUM_CHANNELS-1) is the lowest priroty value. If more than one channel are set with the same priroty value, the channel with small channel number index has higher priority. If DMAC is configured to support fix priority or round-robin priority, this field is not exist. 备注 if user not define ProgrammablePriority, it only can be readed.
3	RSVD	R	-	Reserved
2	CFG1_L_DST_PCTL_OVER	R	0x1	DMA destination bus protocol finish, indicating the current write command has finished.
1	CFG1_L_SRC_PCTL_OVER	R	0x1	DMA Source bus protocol finish, indicating the current read command has finished.
0	CFG1_L_INACTIVE	R	0x1	Indicates if the channel is inactive. Can be used in conjunction with CFGx_L.CH_SUSP to cleanly disable a channel when destination is peripheral. For more information, refer to “Disabling a Channel Prior to Transfer Completion” . 1 = Channel Inactive for axi interface 0 = Channel not Inactive for axi interface

REG_CFG1_H

• Name: Channel 1 high-32 bits Configuration Register

• Size: 32

• Address offset: 09Ch

• Read/write access: R/W

Configuration register high for DMA channel x, configures additional transfer parameters

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	CFG1_H_EXTENDED_DEST_PER1	R/W	0x0	The extened 4th bit of DEST_PER when hardware handshake interfaces number is configured to 32.
15	CFG1_H_EXTENDED_SRC_PER1	R/W	0x0	The extened 4th bit of SRC_PER when hardware handshake interfaces number is configured to 32.
14:11	CFG1_H_DEST_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the destination of channel x if the FGx.HS_SEL_DST field is 0; otherwise, this field is ignored. The channel can then communicate with the destinationperipheral connected to that interface through the assignedhardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (sourceor destination) should be assigned to the same handshaking interface NOTE2: This field does not exist if the configuration parameterDMAC_NUM_HS_INT is set to 0.
10:7	CFG1_H_SRC_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the source of channel x if the CFGx.HS_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct RTK_DMAC operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. NOTE2: This field does not exist if the configuration parameter DMAC_NUM_HS_INT is set to 0.
6:4	RSVD	R	-	Reserved
3	CFG1_H_PROTCTL	R/W	0x1	Protection Control.Set the bit 35 to 0 will enable the channel secure DMA transfer. Set the bit 35 to 1 will enable the channel non-secure DMAC transfer. 备注 if user not define DMAC_SECURE_MODE, it only can be readed.
2:1	RSVD	R	-	Reserved
0	CFG1_H_FCMODE	R/W	0x0	Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are servied when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs. Data pre-fetching is disabled. 备注 Please keep this bit 0 when Transfer Type and Flow Control is not ”destination peripheral is the flow controller and transfer type is peripheral to peripheral” (TT_FC!=7).

REG_SAR2

• Name: Channel 2 Source Address Register

• Size: 32

• Address offset: 0B0h

• Read/write access: R/W

Source address register for DMA channel x, specifies the source memory address

Bit	Symbol	Access	INI	Description
31:0	SAR2	R/W	Unknown	Source Address of DMA transfer.Updated after each source transfer. The SINC field in the CTLx register determines whether the address increments, or is left unchanged on every source transfer throughout the block transfer.

REG_CURR_SAR2

• Name: The read back value is channel 2 source reading address at present

• Size: 32

• Address offset: 0B4h

• Read/write access: R

Current source address register for DMA channel x, indicates the current source address during

transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_SAR2	R	0x0	The read back value is source reading address at present

REG_DAR2

• Name: Channel 2 Destination Address Register

• Size: 32

• Address offset: 0B8h

• Read/write access: R/W

Destination address register for DMA channel x, specifies the destination memory address

Bit	Symbol	Access	INI	Description
31:0	DAR2	R/W	Unknown	Destination address of DMA transfer.Updated after each destination transfer. The DINC field in the CTLx register determines whether the address increments, or is left unchanged on every destination transfer throughout the block transfer.

REG_CURR_DAR2

• Name: The read back value is channel 2 destination writing address at present

• Size: 32

• Address offset: 0BCh

• Read/write access: R

Current destination address register for DMA channel x, indicates the current destination address

during transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_DAR2	R	0x0	The read back value is destination writing address at present

REG_LLP2_L

• Name: Channel 2 low-32 bits Linked List Pointer Register

• Size: 32

• Address offset: 0C0h

• Read/write access: R/W

Linked list pointer register low for DMA channel x, points to the starting address of linked list

item

Bit	Symbol	Access	INI	Description
31:2	LLP2_L_LOC	R/W	Unknown	Starting Address In Memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary.LLI accesses are always 32-bit accesses aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit.
1:0	RSVD	R	-	Reserved

REG_CTL2_L

• Name: Channel 2 low-32 bits Control Register

• Size: 32

• Address offset: 0C8h

• Read/write access: R/W

Control register low for DMA channel x, configures channel control settings

Bit	Symbol	Access	INI	Description
31:29	RSVD	R	-	Reserved
28	CTL2_L_LLP_SRC_EN	R/W	0x0	Block chanining is enabled on the source side only if the LLP_SRC_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
27	CTL2_L_LLP_DST_EN	R/W	0x0	Block chanining is enabled on the destination side only if the LLP_DST_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
26:23	RSVD	R	-	Reserved
22:20	CTL2_L_TT_FC	R/W	0x0	Transfer Type and Flow Control.The following transfer types are supported. Memory to Memory Memory to Peripheral Peripheral to Memory Peripheral to Peripheral Flow Control can be assigned to the RTK_DMAC, the source peripheral, or the destination peripheral. Table 6-4 lists the decoding for this field. For more information on transfer types and flow control, refer to “Setup/Operation of RTK_DMAC Transfers”. Reset Value: 3’h0 Dependencies: If hardware handshake isn’t support, then TT_FC can only be set to 3’b0. TT_FC[2] can only be read.
19	RSVD	R	-	Reserved
18	CTL2_L_DST_SCATTER_EN	R/W	0x0	Destination scatter enable bit:0 = Scatter disabled1 = Scatter enabledScatter on the destination side is applicable only when the CTLx_L.DINC bit indicates an incrementing address control and DARx should be aligned with DST_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_DST_SCA_EN is not selected.
17	CTL2_L_SRC_GATHER_EN	R/W	0x0	Source gather enable bit: 0 = Gather disabled 1 = Gather enabled Gather on the source side is applicable only when the CTLx_L.SINC bit indicates an incrementing address control and SARx should be aligned with SRC_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_SRC_GAT_EN is not selected.
16:14	CTL2_L_SRC_MSIZE	R/W	0x1	Source Burst Transaction Length. Number of data items, each of width CTLx_L.SRC_TR_WIDTH if source is not memory, otherwise each of width DMAC_TR_WIDTH_DEFAULT, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface. Read burst transaction length on bus (ARLen) will not exceed this value, but may be less than this value. If SINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-0 lists the decoding for this field.
13:11	CTL2_L_DEST_MSIZE	R/W	0x1	Destination Burst Transaction Length. Number of data items, each of width DATA_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. Write burst transaction length on bus (AWLen) will not exceed this value, but may be less than this value. If DINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-1 lists the decoding for this field.
10:9	CTL2_L_SINC	R/W	0x0	Source Address Increment. Indicates whether to increment the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to “No change.”If source is memory appointed by CTLx_L.TT_FC, and set SINC=No change, then SRC_TR_WIDTH must be set to BUS width. And DMAC will read data from the fixed memory address until block transfer finish, but It is not recommended to read memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01 =Not support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.SRC_TR_WIDTH boundary.
8:7	CTL2_L_DINC	R/W	0x0	Destination Address Increment. Indicates whether to increment destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change.”If destination is memory appointed by CTLx_L.TT_FC, and set DINC=No change, then DST_TR_WIDTH must be set to BUS width. And DMAC will write data to the fixed memory address until block transfer finish, but It is not recommended to write memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01=Not Support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.DST_TR_WIDTH boundary.
6:4	CTL2_L_SRC_TR_WIDTH	R/W	0x0	Source Transfer Width. Table 6-3 lists the decoding for this field.It can’t be mapped to AXI bus data width directly. Since AXI bus data width is fixed (such as 32bit/64bit), AXI use byte enable signal for byte/half word transfer (still burst). So, the SRC_TR_WIDTH is only used for total block data size calculation and streaming mode byte/half word transfer (for FIFO transfer). 备注 SRC_TR_WIDTH must not be bigger than BUS width.
3:1	CTL2_L_DST_TR_WIDTH	R/W	0x0	Destination Transfer Width.Table 6-3 lists the decoding for this field. It can’t be mapped to AXI bus data width directly. For a non-memory peripheral, typically the peripheral (destination) FIFO width.Note: DST_TR_WIDTH must not be bigger than BUS width
0	CTL2_L_INT_EN	R/W	0x1	Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel; raw* interrupt registers still assert if CTLx_L.INT_EN = 0.

REG_CTL2_H

• Name: Channel 2 high-32 bits Control Register

• Size: 32

• Address offset: 0CCh

• Read/write access: R

Control register high for DMA channel x for block size

Bit	Symbol	Access	INI	Description
31:0	CTL2_H_TRANS_DATA_CNT	R	0x0	Data Transfered Count.Once the transfer starts, the read-back value is the total number of data bytes already write to destination memory or peripheral.

REG_CFG2_L

• Name: Channel 2 low-32 bits Configuration Register

• Size: 32

• Address offset: 0F0h

• Read/write access: R/W

Configuration register low for DMA channel x, configures transfer parameters

Bit	Symbol	Access	INI	Description
31	CFG2_L_RELOAD_DST	R/W	0x0	Automatic Destination Reload. The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.This register does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
30	CFG2_L_RELOAD_SRC	R/W	0x0	Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. This field does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
29:20	RSVD	R	-	Reserved
19	CFG2_L_SRC_HS_POL	R/W	0x0	Source Handshaking Interface Polarity. 0 = Active high 1 = Active low
18	CFG2_L_DST_HS_POL	R/W	0x0	Destination Handshaking Interface Polarity. 0 = Active high 1 = Active low For information on this, refer to “Handshaking Interface” .
17:12	RSVD	R	-	Reserved
11	CFG2_L_HS_SEL_SRC	R/W	0x1	Source Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for source requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware-initiated transaction requests are ignored. If the source peripheral is memory, then this bit is ignored.
10	CFG2_L_HS_SEL_DST	R/W	0x1	Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for destination requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware- initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored.
9	CFG2_L_FIFO_EMPTY	R	0x1	Indicates if there is data left in the channel FIFO. 1 = Channel FIFO empty 0 = Channel FIFO not empty
8	CFG2_L_CH_SUSP	R/W	0x0	Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx_l.INACTIVE to cleanly disable a channel without losing any data. 0 = Not suspended 1 = Suspend DMA transfer from the source. This field will be reset to 0 after “Disabling a Channel Prior to Transfer Completion” automatically by hardware.For more information, refer to “7.7 Disabling a Channel Prior to Transfer Completion” . 备注 if user not define DMAC_CH*_SUPPORT_SUSPEND, it only can be readed.
7:4	CFG2_L_CH_PRIOR	R/W	0x0	Channel priority. RTK DMAC supports three kinds of channel priority now, fixed priority, round robin priority and programmable priority. The default way is fixed priority to reduce area, and channel0 has the highest priority, channel15 has the lowest priority. Changing the definition of parameter FIX_PRIORITY or Programmable_PRIORITY can change priority way. If RTK DMAC is configured to support Programmable priority, this field will be used to set priority between channels. CH_PRIOR’s legal value is 0 ~ (DMAC_NUM_CHANNELS-1), and 0 is the highest priority value, (DMAC_NUM_CHANNELS-1) is the lowest priroty value. If more than one channel are set with the same priroty value, the channel with small channel number index has higher priority. If DMAC is configured to support fix priority or round-robin priority, this field is not exist. 备注 if user not define ProgrammablePriority, it only can be readed.
3	RSVD	R	-	Reserved
2	CFG2_L_DST_PCTL_OVER	R	0x1	DMA destination bus protocol finish, indicating the current write command has finished.
1	CFG2_L_SRC_PCTL_OVER	R	0x1	DMA Source bus protocol finish, indicating the current read command has finished.
0	CFG2_L_INACTIVE	R	0x1	Indicates if the channel is inactive. Can be used in conjunction with CFGx_L.CH_SUSP to cleanly disable a channel when destination is peripheral. For more information, refer to “Disabling a Channel Prior to Transfer Completion” . 1 = Channel Inactive for axi interface 0 = Channel not Inactive for axi interface

REG_CFG2_H

• Name: Channel 2 high-32 bits Configuration Register

• Size: 32

• Address offset: 0F4h

• Read/write access: R/W

Configuration register high for DMA channel x, configures additional transfer parameters

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	CFG2_H_EXTENDED_DEST_PER1	R/W	0x0	The extened 4th bit of DEST_PER when hardware handshake interfaces number is configured to 32.
15	CFG2_H_EXTENDED_SRC_PER1	R/W	0x0	The extened 4th bit of SRC_PER when hardware handshake interfaces number is configured to 32.
14:11	CFG2_H_DEST_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the destination of channel x if the FGx.HS_SEL_DST field is 0; otherwise, this field is ignored. The channel can then communicate with the destinationperipheral connected to that interface through the assignedhardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (sourceor destination) should be assigned to the same handshaking interface NOTE2: This field does not exist if the configuration parameterDMAC_NUM_HS_INT is set to 0.
10:7	CFG2_H_SRC_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the source of channel x if the CFGx.HS_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct RTK_DMAC operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. NOTE2: This field does not exist if the configuration parameter DMAC_NUM_HS_INT is set to 0.
6:4	RSVD	R	-	Reserved
3	CFG2_H_PROTCTL	R/W	0x1	Protection Control.Set the bit 35 to 0 will enable the channel secure DMA transfer. Set the bit 35 to 1 will enable the channel non-secure DMAC transfer. 备注 if user not define DMAC_SECURE_MODE, it only can be readed.
2:1	RSVD	R	-	Reserved
0	CFG2_H_FCMODE	R/W	0x0	Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are servied when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs. Data pre-fetching is disabled. 备注 Please keep this bit 0 when Transfer Type and Flow Control is not ”destination peripheral is the flow controller and transfer type is peripheral to peripheral” (TT_FC!=7).

REG_SAR3

• Name: Channel 3 Source Address Register

• Size: 32

• Address offset: 108h

• Read/write access: R/W

Source address register for DMA channel x, specifies the source memory address

Bit	Symbol	Access	INI	Description
31:0	SAR3	R/W	Unknown	Source Address of DMA transfer.Updated after each source transfer. The SINC field in the CTLx register determines whether the address increments, or is left unchanged on every source transfer throughout the block transfer.

REG_CURR_SAR3

• Name: The read back value is channel 3 source reading address at present

• Size: 32

• Address offset: 10Ch

• Read/write access: R

Current source address register for DMA channel x, indicates the current source address during

transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_SAR3	R	0x0	The read back value is source reading address at present

REG_DAR3

• Name: Channel 3 Destination Address Register

• Size: 32

• Address offset: 110h

• Read/write access: R/W

Destination address register for DMA channel x, specifies the destination memory address

Bit	Symbol	Access	INI	Description
31:0	DAR3	R/W	Unknown	Destination address of DMA transfer.Updated after each destination transfer. The DINC field in the CTLx register determines whether the address increments, or is left unchanged on every destination transfer throughout the block transfer.

REG_CURR_DAR3

• Name: The read back value is channel 3 destination writing address at present

• Size: 32

• Address offset: 114h

• Read/write access: R

Current destination address register for DMA channel x, indicates the current destination address

during transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_DAR3	R	0x0	The read back value is destination writing address at present

REG_LLP3_L

• Name: Channel 3 low-32 bits Linked List Pointer Register

• Size: 32

• Address offset: 118h

• Read/write access: R/W

Linked list pointer register low for DMA channel x, points to the starting address of linked list

item

Bit	Symbol	Access	INI	Description
31:2	LLP3_L_LOC	R/W	Unknown	Starting Address In Memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary.LLI accesses are always 32-bit accesses aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit.
1:0	RSVD	R	-	Reserved

REG_CTL3_L

• Name: Channel 3 low-32 bits Control Register

• Size: 32

• Address offset: 120h

• Read/write access: R/W

Control register low for DMA channel x, configures channel control settings

Bit	Symbol	Access	INI	Description
31:29	RSVD	R	-	Reserved
28	CTL3_L_LLP_SRC_EN	R/W	0x0	Block chanining is enabled on the source side only if the LLP_SRC_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
27	CTL3_L_LLP_DST_EN	R/W	0x0	Block chanining is enabled on the destination side only if the LLP_DST_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
26:23	RSVD	R	-	Reserved
22:20	CTL3_L_TT_FC	R/W	0x0	Transfer Type and Flow Control.The following transfer types are supported. Memory to Memory Memory to Peripheral Peripheral to Memory Peripheral to Peripheral Flow Control can be assigned to the RTK_DMAC, the source peripheral, or the destination peripheral. Table 6-4 lists the decoding for this field. For more information on transfer types and flow control, refer to “Setup/Operation of RTK_DMAC Transfers”. Reset Value: 3’h0 Dependencies: If hardware handshake isn’t support, then TT_FC can only be set to 3’b0. TT_FC[2] can only be read.
19	RSVD	R	-	Reserved
18	CTL3_L_DST_SCATTER_EN	R/W	0x0	Destination scatter enable bit:0 = Scatter disabled1 = Scatter enabledScatter on the destination side is applicable only when the CTLx_L.DINC bit indicates an incrementing address control and DARx should be aligned with DST_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_DST_SCA_EN is not selected.
17	CTL3_L_SRC_GATHER_EN	R/W	0x0	Source gather enable bit: 0 = Gather disabled 1 = Gather enabled Gather on the source side is applicable only when the CTLx_L.SINC bit indicates an incrementing address control and SARx should be aligned with SRC_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_SRC_GAT_EN is not selected.
16:14	CTL3_L_SRC_MSIZE	R/W	0x1	Source Burst Transaction Length. Number of data items, each of width CTLx_L.SRC_TR_WIDTH if source is not memory, otherwise each of width DMAC_TR_WIDTH_DEFAULT, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface. Read burst transaction length on bus (ARLen) will not exceed this value, but may be less than this value. If SINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-0 lists the decoding for this field.
13:11	CTL3_L_DEST_MSIZE	R/W	0x1	Destination Burst Transaction Length. Number of data items, each of width DATA_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. Write burst transaction length on bus (AWLen) will not exceed this value, but may be less than this value. If DINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-1 lists the decoding for this field.
10:9	CTL3_L_SINC	R/W	0x0	Source Address Increment. Indicates whether to increment the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to “No change.”If source is memory appointed by CTLx_L.TT_FC, and set SINC=No change, then SRC_TR_WIDTH must be set to BUS width. And DMAC will read data from the fixed memory address until block transfer finish, but It is not recommended to read memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01 =Not support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.SRC_TR_WIDTH boundary.
8:7	CTL3_L_DINC	R/W	0x0	Destination Address Increment. Indicates whether to increment destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change.”If destination is memory appointed by CTLx_L.TT_FC, and set DINC=No change, then DST_TR_WIDTH must be set to BUS width. And DMAC will write data to the fixed memory address until block transfer finish, but It is not recommended to write memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01=Not Support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.DST_TR_WIDTH boundary.
6:4	CTL3_L_SRC_TR_WIDTH	R/W	0x0	Source Transfer Width. Table 6-3 lists the decoding for this field.It can’t be mapped to AXI bus data width directly. Since AXI bus data width is fixed (such as 32bit/64bit), AXI use byte enable signal for byte/half word transfer (still burst). So, the SRC_TR_WIDTH is only used for total block data size calculation and streaming mode byte/half word transfer (for FIFO transfer). 备注 SRC_TR_WIDTH must not be bigger than BUS width.
3:1	CTL3_L_DST_TR_WIDTH	R/W	0x0	Destination Transfer Width.Table 6-3 lists the decoding for this field. It can’t be mapped to AXI bus data width directly. For a non-memory peripheral, typically the peripheral (destination) FIFO width.Note: DST_TR_WIDTH must not be bigger than BUS width
0	CTL3_L_INT_EN	R/W	0x1	Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel; raw* interrupt registers still assert if CTLx_L.INT_EN = 0.

REG_CTL3_H

• Name: Channel 3 high-32 bits Control Register

• Size: 32

• Address offset: 124h

• Read/write access: R

Control register high for DMA channel x for block size

Bit	Symbol	Access	INI	Description
31:0	CTL3_H_TRANS_DATA_CNT	R	0x0	Data Transfered Count.Once the transfer starts, the read-back value is the total number of data bytes already write to destination memory or peripheral.

REG_CFG3_L

• Name: Channel 3 low-32 bits Configuration Register

• Size: 32

• Address offset: 148h

• Read/write access: R/W

Configuration register low for DMA channel x, configures transfer parameters

Bit	Symbol	Access	INI	Description
31	CFG3_L_RELOAD_DST	R/W	0x0	Automatic Destination Reload. The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.This register does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
30	CFG3_L_RELOAD_SRC	R/W	0x0	Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. This field does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
29:20	RSVD	R	-	Reserved
19	CFG3_L_SRC_HS_POL	R/W	0x0	Source Handshaking Interface Polarity. 0 = Active high 1 = Active low
18	CFG3_L_DST_HS_POL	R/W	0x0	Destination Handshaking Interface Polarity. 0 = Active high 1 = Active low For information on this, refer to “Handshaking Interface” .
17:12	RSVD	R	-	Reserved
11	CFG3_L_HS_SEL_SRC	R/W	0x1	Source Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for source requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware-initiated transaction requests are ignored. If the source peripheral is memory, then this bit is ignored.
10	CFG3_L_HS_SEL_DST	R/W	0x1	Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for destination requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware- initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored.
9	CFG3_L_FIFO_EMPTY	R	0x1	Indicates if there is data left in the channel FIFO. 1 = Channel FIFO empty 0 = Channel FIFO not empty
8	CFG3_L_CH_SUSP	R/W	0x0	Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx_l.INACTIVE to cleanly disable a channel without losing any data. 0 = Not suspended 1 = Suspend DMA transfer from the source. This field will be reset to 0 after “Disabling a Channel Prior to Transfer Completion” automatically by hardware.For more information, refer to “7.7 Disabling a Channel Prior to Transfer Completion” . 备注 if user not define DMAC_CH*_SUPPORT_SUSPEND, it only can be readed.
7:4	CFG3_L_CH_PRIOR	R/W	0x0	Channel priority. RTK DMAC supports three kinds of channel priority now, fixed priority, round robin priority and programmable priority. The default way is fixed priority to reduce area, and channel0 has the highest priority, channel15 has the lowest priority. Changing the definition of parameter FIX_PRIORITY or Programmable_PRIORITY can change priority way. If RTK DMAC is configured to support Programmable priority, this field will be used to set priority between channels. CH_PRIOR’s legal value is 0 ~ (DMAC_NUM_CHANNELS-1), and 0 is the highest priority value, (DMAC_NUM_CHANNELS-1) is the lowest priroty value. If more than one channel are set with the same priroty value, the channel with small channel number index has higher priority. If DMAC is configured to support fix priority or round-robin priority, this field is not exist. 备注 if user not define ProgrammablePriority, it only can be readed.
3	RSVD	R	-	Reserved
2	CFG3_L_DST_PCTL_OVER	R	0x1	DMA destination bus protocol finish, indicating the current write command has finished.
1	CFG3_L_SRC_PCTL_OVER	R	0x1	DMA Source bus protocol finish, indicating the current read command has finished.
0	CFG3_L_INACTIVE	R	0x1	Indicates if the channel is inactive. Can be used in conjunction with CFGx_L.CH_SUSP to cleanly disable a channel when destination is peripheral. For more information, refer to “Disabling a Channel Prior to Transfer Completion” . 1 = Channel Inactive for axi interface 0 = Channel not Inactive for axi interface

REG_CFG3_H

• Name: Channel 3 high-32 bits Configuration Register

• Size: 32

• Address offset: 14Ch

• Read/write access: R/W

Configuration register high for DMA channel x, configures additional transfer parameters

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	CFG3_H_EXTENDED_DEST_PER1	R/W	0x0	The extened 4th bit of DEST_PER when hardware handshake interfaces number is configured to 32.
15	CFG3_H_EXTENDED_SRC_PER1	R/W	0x0	The extened 4th bit of SRC_PER when hardware handshake interfaces number is configured to 32.
14:11	CFG3_H_DEST_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the destination of channel x if the FGx.HS_SEL_DST field is 0; otherwise, this field is ignored. The channel can then communicate with the destinationperipheral connected to that interface through the assignedhardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (sourceor destination) should be assigned to the same handshaking interface NOTE2: This field does not exist if the configuration parameterDMAC_NUM_HS_INT is set to 0.
10:7	CFG3_H_SRC_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the source of channel x if the CFGx.HS_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct RTK_DMAC operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. NOTE2: This field does not exist if the configuration parameter DMAC_NUM_HS_INT is set to 0.
6:4	RSVD	R	-	Reserved
3	CFG3_H_PROTCTL	R/W	0x1	Protection Control.Set the bit 35 to 0 will enable the channel secure DMA transfer. Set the bit 35 to 1 will enable the channel non-secure DMAC transfer. 备注 if user not define DMAC_SECURE_MODE, it only can be readed.
2:1	RSVD	R	-	Reserved
0	CFG3_H_FCMODE	R/W	0x0	Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are servied when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs. Data pre-fetching is disabled. 备注 Please keep this bit 0 when Transfer Type and Flow Control is not ”destination peripheral is the flow controller and transfer type is peripheral to peripheral” (TT_FC!=7).

REG_SAR4

• Name: Channel 4 Source Address Register

• Size: 32

• Address offset: 160h

• Read/write access: R/W

Source address register for DMA channel x, specifies the source memory address

Bit	Symbol	Access	INI	Description
31:0	SAR4	R/W	Unknown	Source Address of DMA transfer.Updated after each source transfer. The SINC field in the CTLx register determines whether the address increments, or is left unchanged on every source transfer throughout the block transfer.

REG_CURR_SAR4

• Name: The read back value is channel 4 source reading address at present

• Size: 32

• Address offset: 164h

• Read/write access: R

Current source address register for DMA channel x, indicates the current source address during

transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_SAR4	R	0x0	The read back value is source reading address at present

REG_DAR4

• Name: Channel 4 Destination Address Register

• Size: 32

• Address offset: 168h

• Read/write access: R/W

Destination address register for DMA channel x, specifies the destination memory address

Bit	Symbol	Access	INI	Description
31:0	DAR4	R/W	Unknown	Destination address of DMA transfer.Updated after each destination transfer. The DINC field in the CTLx register determines whether the address increments, or is left unchanged on every destination transfer throughout the block transfer.

REG_CURR_DAR4

• Name: The read back value is channel 4 destination writing address at present

• Size: 32

• Address offset: 16Ch

• Read/write access: R

Current destination address register for DMA channel x, indicates the current destination address

during transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_DAR4	R	0x0	The read back value is destination writing address at present

REG_LLP4_L

• Name: Channel 4 low-32 bits Linked List Pointer Register

• Size: 32

• Address offset: 170h

• Read/write access: R/W

Linked list pointer register low for DMA channel x, points to the starting address of linked list

item

Bit	Symbol	Access	INI	Description
31:2	LLP4_L_LOC	R/W	Unknown	Starting Address In Memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary.LLI accesses are always 32-bit accesses aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit.
1:0	RSVD	R	-	Reserved

REG_CTL4_L

• Name: Channel 4 low-32 bits Control Register

• Size: 32

• Address offset: 178h

• Read/write access: R/W

Control register low for DMA channel x, configures channel control settings

Bit	Symbol	Access	INI	Description
31:29	RSVD	R	-	Reserved
28	CTL4_L_LLP_SRC_EN	R/W	0x0	Block chanining is enabled on the source side only if the LLP_SRC_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
27	CTL4_L_LLP_DST_EN	R/W	0x0	Block chanining is enabled on the destination side only if the LLP_DST_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
26:23	RSVD	R	-	Reserved
22:20	CTL4_L_TT_FC	R/W	0x0	Transfer Type and Flow Control.The following transfer types are supported. Memory to Memory Memory to Peripheral Peripheral to Memory Peripheral to Peripheral Flow Control can be assigned to the RTK_DMAC, the source peripheral, or the destination peripheral. Table 6-4 lists the decoding for this field. For more information on transfer types and flow control, refer to “Setup/Operation of RTK_DMAC Transfers”. Reset Value: 3’h0 Dependencies: If hardware handshake isn’t support, then TT_FC can only be set to 3’b0. TT_FC[2] can only be read.
19	RSVD	R	-	Reserved
18	CTL4_L_DST_SCATTER_EN	R/W	0x0	Destination scatter enable bit:0 = Scatter disabled1 = Scatter enabledScatter on the destination side is applicable only when the CTLx_L.DINC bit indicates an incrementing address control and DARx should be aligned with DST_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_DST_SCA_EN is not selected.
17	CTL4_L_SRC_GATHER_EN	R/W	0x0	Source gather enable bit: 0 = Gather disabled 1 = Gather enabled Gather on the source side is applicable only when the CTLx_L.SINC bit indicates an incrementing address control and SARx should be aligned with SRC_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_SRC_GAT_EN is not selected.
16:14	CTL4_L_SRC_MSIZE	R/W	0x1	Source Burst Transaction Length. Number of data items, each of width CTLx_L.SRC_TR_WIDTH if source is not memory, otherwise each of width DMAC_TR_WIDTH_DEFAULT, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface. Read burst transaction length on bus (ARLen) will not exceed this value, but may be less than this value. If SINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-0 lists the decoding for this field.
13:11	CTL4_L_DEST_MSIZE	R/W	0x1	Destination Burst Transaction Length. Number of data items, each of width DATA_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. Write burst transaction length on bus (AWLen) will not exceed this value, but may be less than this value. If DINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-1 lists the decoding for this field.
10:9	CTL4_L_SINC	R/W	0x0	Source Address Increment. Indicates whether to increment the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to “No change.”If source is memory appointed by CTLx_L.TT_FC, and set SINC=No change, then SRC_TR_WIDTH must be set to BUS width. And DMAC will read data from the fixed memory address until block transfer finish, but It is not recommended to read memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01 =Not support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.SRC_TR_WIDTH boundary.
8:7	CTL4_L_DINC	R/W	0x0	Destination Address Increment. Indicates whether to increment destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change.”If destination is memory appointed by CTLx_L.TT_FC, and set DINC=No change, then DST_TR_WIDTH must be set to BUS width. And DMAC will write data to the fixed memory address until block transfer finish, but It is not recommended to write memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01=Not Support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.DST_TR_WIDTH boundary.
6:4	CTL4_L_SRC_TR_WIDTH	R/W	0x0	Source Transfer Width. Table 6-3 lists the decoding for this field.It can’t be mapped to AXI bus data width directly. Since AXI bus data width is fixed (such as 32bit/64bit), AXI use byte enable signal for byte/half word transfer (still burst). So, the SRC_TR_WIDTH is only used for total block data size calculation and streaming mode byte/half word transfer (for FIFO transfer). 备注 SRC_TR_WIDTH must not be bigger than BUS width.
3:1	CTL4_L_DST_TR_WIDTH	R/W	0x0	Destination Transfer Width.Table 6-3 lists the decoding for this field. It can’t be mapped to AXI bus data width directly. For a non-memory peripheral, typically the peripheral (destination) FIFO width.Note: DST_TR_WIDTH must not be bigger than BUS width
0	CTL4_L_INT_EN	R/W	0x1	Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel; raw* interrupt registers still assert if CTLx_L.INT_EN = 0.

REG_CTL4_H

• Name: Channel 4 high-32 bits Control Register

• Size: 32

• Address offset: 17Ch

• Read/write access: R

Control register high for DMA channel x for block size

Bit	Symbol	Access	INI	Description
31:0	CTL4_H_TRANS_DATA_CNT	R	0x0	Data Transfered Count.Once the transfer starts, the read-back value is the total number of data bytes already write to destination memory or peripheral.

REG_CFG4_L

• Name: Channel 4 low-32 bits Configuration Register

• Size: 32

• Address offset: 1A0h

• Read/write access: R/W

Configuration register low for DMA channel x, configures transfer parameters

Bit	Symbol	Access	INI	Description
31	CFG4_L_RELOAD_DST	R/W	0x0	Automatic Destination Reload. The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.This register does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
30	CFG4_L_RELOAD_SRC	R/W	0x0	Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. This field does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
29:20	RSVD	R	-	Reserved
19	CFG4_L_SRC_HS_POL	R/W	0x0	Source Handshaking Interface Polarity. 0 = Active high 1 = Active low
18	CFG4_L_DST_HS_POL	R/W	0x0	Destination Handshaking Interface Polarity. 0 = Active high 1 = Active low For information on this, refer to “Handshaking Interface” .
17:12	RSVD	R	-	Reserved
11	CFG4_L_HS_SEL_SRC	R/W	0x1	Source Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for source requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware-initiated transaction requests are ignored. If the source peripheral is memory, then this bit is ignored.
10	CFG4_L_HS_SEL_DST	R/W	0x1	Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for destination requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware- initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored.
9	CFG4_L_FIFO_EMPTY	R	0x1	Indicates if there is data left in the channel FIFO. 1 = Channel FIFO empty 0 = Channel FIFO not empty
8	CFG4_L_CH_SUSP	R/W	0x0	Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx_l.INACTIVE to cleanly disable a channel without losing any data. 0 = Not suspended 1 = Suspend DMA transfer from the source. This field will be reset to 0 after “Disabling a Channel Prior to Transfer Completion” automatically by hardware.For more information, refer to “7.7 Disabling a Channel Prior to Transfer Completion” . 备注 if user not define DMAC_CH*_SUPPORT_SUSPEND, it only can be readed.
7:4	CFG4_L_CH_PRIOR	R/W	0x0	Channel priority. RTK DMAC supports three kinds of channel priority now, fixed priority, round robin priority and programmable priority. The default way is fixed priority to reduce area, and channel0 has the highest priority, channel15 has the lowest priority. Changing the definition of parameter FIX_PRIORITY or Programmable_PRIORITY can change priority way. If RTK DMAC is configured to support Programmable priority, this field will be used to set priority between channels. CH_PRIOR’s legal value is 0 ~ (DMAC_NUM_CHANNELS-1), and 0 is the highest priority value, (DMAC_NUM_CHANNELS-1) is the lowest priroty value. If more than one channel are set with the same priroty value, the channel with small channel number index has higher priority. If DMAC is configured to support fix priority or round-robin priority, this field is not exist. 备注 if user not define ProgrammablePriority, it only can be readed.
3	RSVD	R	-	Reserved
2	CFG4_L_DST_PCTL_OVER	R	0x1	DMA destination bus protocol finish, indicating the current write command has finished.
1	CFG4_L_SRC_PCTL_OVER	R	0x1	DMA Source bus protocol finish, indicating the current read command has finished.
0	CFG4_L_INACTIVE	R	0x1	Indicates if the channel is inactive. Can be used in conjunction with CFGx_L.CH_SUSP to cleanly disable a channel when destination is peripheral. For more information, refer to “Disabling a Channel Prior to Transfer Completion” . 1 = Channel Inactive for axi interface 0 = Channel not Inactive for axi interface

REG_CFG4_H

• Name: Channel 4 high-32 bits Configuration Register

• Size: 32

• Address offset: 1A4h

• Read/write access: R/W

Configuration register high for DMA channel x, configures additional transfer parameters

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	CFG4_H_EXTENDED_DEST_PER1	R/W	0x0	The extened 4th bit of DEST_PER when hardware handshake interfaces number is configured to 32.
15	CFG4_H_EXTENDED_SRC_PER1	R/W	0x0	The extened 4th bit of SRC_PER when hardware handshake interfaces number is configured to 32.
14:11	CFG4_H_DEST_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the destination of channel x if the FGx.HS_SEL_DST field is 0; otherwise, this field is ignored. The channel can then communicate with the destinationperipheral connected to that interface through the assignedhardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (sourceor destination) should be assigned to the same handshaking interface NOTE2: This field does not exist if the configuration parameterDMAC_NUM_HS_INT is set to 0.
10:7	CFG4_H_SRC_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the source of channel x if the CFGx.HS_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct RTK_DMAC operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. NOTE2: This field does not exist if the configuration parameter DMAC_NUM_HS_INT is set to 0.
6:4	RSVD	R	-	Reserved
3	CFG4_H_PROTCTL	R/W	0x1	Protection Control.Set the bit 35 to 0 will enable the channel secure DMA transfer. Set the bit 35 to 1 will enable the channel non-secure DMAC transfer. 备注 if user not define DMAC_SECURE_MODE, it only can be readed.
2:1	RSVD	R	-	Reserved
0	CFG4_H_FCMODE	R/W	0x0	Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are servied when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs. Data pre-fetching is disabled. 备注 Please keep this bit 0 when Transfer Type and Flow Control is not ”destination peripheral is the flow controller and transfer type is peripheral to peripheral” (TT_FC!=7).

REG_SAR5

• Name: Channel 5 Source Address Register

• Size: 32

• Address offset: 1B8h

• Read/write access: R/W

Source address register for DMA channel x, specifies the source memory address

Bit	Symbol	Access	INI	Description
31:0	SAR5	R/W	Unknown	Source Address of DMA transfer.Updated after each source transfer. The SINC field in the CTLx register determines whether the address increments, or is left unchanged on every source transfer throughout the block transfer.

REG_CURR_SAR5

• Name: The read back value is channel 5 source reading address at present

• Size: 32

• Address offset: 1BCh

• Read/write access: R

Current source address register for DMA channel x, indicates the current source address during

transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_SAR5	R	0x0	The read back value is source reading address at present

REG_DAR5

• Name: Channel 5 Destination Address Register

• Size: 32

• Address offset: 1C0h

• Read/write access: R/W

Destination address register for DMA channel x, specifies the destination memory address

Bit	Symbol	Access	INI	Description
31:0	DAR5	R/W	Unknown	Destination address of DMA transfer.Updated after each destination transfer. The DINC field in the CTLx register determines whether the address increments, or is left unchanged on every destination transfer throughout the block transfer.

REG_CURR_DAR5

• Name: The read back value is channel 5 destination writing address at present

• Size: 32

• Address offset: 1C4h

• Read/write access: R

Current destination address register for DMA channel x, indicates the current destination address

during transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_DAR5	R	0x0	The read back value is destination writing address at present

REG_LLP5_L

• Name: Channel 5 low-32 bits Linked List Pointer Register

• Size: 32

• Address offset: 1C8h

• Read/write access: R/W

Linked list pointer register low for DMA channel x, points to the starting address of linked list

item

Bit	Symbol	Access	INI	Description
31:2	LLP5_L_LOC	R/W	Unknown	Starting Address In Memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary.LLI accesses are always 32-bit accesses aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit.
1:0	RSVD	R	-	Reserved

REG_CTL5_L

• Name: Channel 5 low-32 bits Control Register

• Size: 32

• Address offset: 1D0h

• Read/write access: R/W

Control register low for DMA channel x, configures channel control settings

Bit	Symbol	Access	INI	Description
31:29	RSVD	R	-	Reserved
28	CTL5_L_LLP_SRC_EN	R/W	0x0	Block chanining is enabled on the source side only if the LLP_SRC_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
27	CTL5_L_LLP_DST_EN	R/W	0x0	Block chanining is enabled on the destination side only if the LLP_DST_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
26:23	RSVD	R	-	Reserved
22:20	CTL5_L_TT_FC	R/W	0x0	Transfer Type and Flow Control.The following transfer types are supported. Memory to Memory Memory to Peripheral Peripheral to Memory Peripheral to Peripheral Flow Control can be assigned to the RTK_DMAC, the source peripheral, or the destination peripheral. Table 6-4 lists the decoding for this field. For more information on transfer types and flow control, refer to “Setup/Operation of RTK_DMAC Transfers”. Reset Value: 3’h0 Dependencies: If hardware handshake isn’t support, then TT_FC can only be set to 3’b0. TT_FC[2] can only be read.
19	RSVD	R	-	Reserved
18	CTL5_L_DST_SCATTER_EN	R/W	0x0	Destination scatter enable bit:0 = Scatter disabled1 = Scatter enabledScatter on the destination side is applicable only when the CTLx_L.DINC bit indicates an incrementing address control and DARx should be aligned with DST_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_DST_SCA_EN is not selected.
17	CTL5_L_SRC_GATHER_EN	R/W	0x0	Source gather enable bit: 0 = Gather disabled 1 = Gather enabled Gather on the source side is applicable only when the CTLx_L.SINC bit indicates an incrementing address control and SARx should be aligned with SRC_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_SRC_GAT_EN is not selected.
16:14	CTL5_L_SRC_MSIZE	R/W	0x1	Source Burst Transaction Length. Number of data items, each of width CTLx_L.SRC_TR_WIDTH if source is not memory, otherwise each of width DMAC_TR_WIDTH_DEFAULT, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface. Read burst transaction length on bus (ARLen) will not exceed this value, but may be less than this value. If SINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-0 lists the decoding for this field.
13:11	CTL5_L_DEST_MSIZE	R/W	0x1	Destination Burst Transaction Length. Number of data items, each of width DATA_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. Write burst transaction length on bus (AWLen) will not exceed this value, but may be less than this value. If DINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-1 lists the decoding for this field.
10:9	CTL5_L_SINC	R/W	0x0	Source Address Increment. Indicates whether to increment the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to “No change.”If source is memory appointed by CTLx_L.TT_FC, and set SINC=No change, then SRC_TR_WIDTH must be set to BUS width. And DMAC will read data from the fixed memory address until block transfer finish, but It is not recommended to read memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01 =Not support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.SRC_TR_WIDTH boundary.
8:7	CTL5_L_DINC	R/W	0x0	Destination Address Increment. Indicates whether to increment destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change.”If destination is memory appointed by CTLx_L.TT_FC, and set DINC=No change, then DST_TR_WIDTH must be set to BUS width. And DMAC will write data to the fixed memory address until block transfer finish, but It is not recommended to write memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01=Not Support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.DST_TR_WIDTH boundary.
6:4	CTL5_L_SRC_TR_WIDTH	R/W	0x0	Source Transfer Width. Table 6-3 lists the decoding for this field.It can’t be mapped to AXI bus data width directly. Since AXI bus data width is fixed (such as 32bit/64bit), AXI use byte enable signal for byte/half word transfer (still burst). So, the SRC_TR_WIDTH is only used for total block data size calculation and streaming mode byte/half word transfer (for FIFO transfer). 备注 SRC_TR_WIDTH must not be bigger than BUS width.
3:1	CTL5_L_DST_TR_WIDTH	R/W	0x0	Destination Transfer Width.Table 6-3 lists the decoding for this field. It can’t be mapped to AXI bus data width directly. For a non-memory peripheral, typically the peripheral (destination) FIFO width.Note: DST_TR_WIDTH must not be bigger than BUS width
0	CTL5_L_INT_EN	R/W	0x1	Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel; raw* interrupt registers still assert if CTLx_L.INT_EN = 0.

REG_CTL5_H

• Name: Channel 5 high-32 bits Control Register

• Size: 32

• Address offset: 1D4h

• Read/write access: R

Control register high for DMA channel x for block size

Bit	Symbol	Access	INI	Description
31:0	CTL5_H_TRANS_DATA_CNT	R	0x0	Data Transfered Count.Once the transfer starts, the read-back value is the total number of data bytes already write to destination memory or peripheral.

REG_CFG5_L

• Name: Channel 5 low-32 bits Configuration Register

• Size: 32

• Address offset: 1F8h

• Read/write access: R/W

Configuration register low for DMA channel x, configures transfer parameters

Bit	Symbol	Access	INI	Description
31	CFG5_L_RELOAD_DST	R/W	0x0	Automatic Destination Reload. The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.This register does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
30	CFG5_L_RELOAD_SRC	R/W	0x0	Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. This field does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
29:20	RSVD	R	-	Reserved
19	CFG5_L_SRC_HS_POL	R/W	0x0	Source Handshaking Interface Polarity. 0 = Active high 1 = Active low
18	CFG5_L_DST_HS_POL	R/W	0x0	Destination Handshaking Interface Polarity. 0 = Active high 1 = Active low For information on this, refer to “Handshaking Interface” .
17:12	RSVD	R	-	Reserved
11	CFG5_L_HS_SEL_SRC	R/W	0x1	Source Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for source requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware-initiated transaction requests are ignored. If the source peripheral is memory, then this bit is ignored.
10	CFG5_L_HS_SEL_DST	R/W	0x1	Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for destination requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware- initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored.
9	CFG5_L_FIFO_EMPTY	R	0x1	Indicates if there is data left in the channel FIFO. 1 = Channel FIFO empty 0 = Channel FIFO not empty
8	CFG5_L_CH_SUSP	R/W	0x0	Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx_l.INACTIVE to cleanly disable a channel without losing any data. 0 = Not suspended 1 = Suspend DMA transfer from the source. This field will be reset to 0 after “Disabling a Channel Prior to Transfer Completion” automatically by hardware.For more information, refer to “7.7 Disabling a Channel Prior to Transfer Completion” . 备注 if user not define DMAC_CH*_SUPPORT_SUSPEND, it only can be readed.
7:4	CFG5_L_CH_PRIOR	R/W	0x0	Channel priority. RTK DMAC supports three kinds of channel priority now, fixed priority, round robin priority and programmable priority. The default way is fixed priority to reduce area, and channel0 has the highest priority, channel15 has the lowest priority. Changing the definition of parameter FIX_PRIORITY or Programmable_PRIORITY can change priority way. If RTK DMAC is configured to support Programmable priority, this field will be used to set priority between channels. CH_PRIOR’s legal value is 0 ~ (DMAC_NUM_CHANNELS-1), and 0 is the highest priority value, (DMAC_NUM_CHANNELS-1) is the lowest priroty value. If more than one channel are set with the same priroty value, the channel with small channel number index has higher priority. If DMAC is configured to support fix priority or round-robin priority, this field is not exist. 备注 if user not define ProgrammablePriority, it only can be readed.
3	RSVD	R	-	Reserved
2	CFG5_L_DST_PCTL_OVER	R	0x1	DMA destination bus protocol finish, indicating the current write command has finished.
1	CFG5_L_SRC_PCTL_OVER	R	0x1	DMA Source bus protocol finish, indicating the current read command has finished.
0	CFG5_L_INACTIVE	R	0x1	Indicates if the channel is inactive. Can be used in conjunction with CFGx_L.CH_SUSP to cleanly disable a channel when destination is peripheral. For more information, refer to “Disabling a Channel Prior to Transfer Completion” . 1 = Channel Inactive for axi interface 0 = Channel not Inactive for axi interface

REG_CFG5_H

• Name: Channel 5 high-32 bits Configuration Register

• Size: 32

• Address offset: 1FCh

• Read/write access: R/W

Configuration register high for DMA channel x, configures additional transfer parameters

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	CFG5_H_EXTENDED_DEST_PER1	R/W	0x0	The extened 4th bit of DEST_PER when hardware handshake interfaces number is configured to 32.
15	CFG5_H_EXTENDED_SRC_PER1	R/W	0x0	The extened 4th bit of SRC_PER when hardware handshake interfaces number is configured to 32.
14:11	CFG5_H_DEST_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the destination of channel x if the FGx.HS_SEL_DST field is 0; otherwise, this field is ignored. The channel can then communicate with the destinationperipheral connected to that interface through the assignedhardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (sourceor destination) should be assigned to the same handshaking interface NOTE2: This field does not exist if the configuration parameterDMAC_NUM_HS_INT is set to 0.
10:7	CFG5_H_SRC_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the source of channel x if the CFGx.HS_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct RTK_DMAC operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. NOTE2: This field does not exist if the configuration parameter DMAC_NUM_HS_INT is set to 0.
6:4	RSVD	R	-	Reserved
3	CFG5_H_PROTCTL	R/W	0x1	Protection Control.Set the bit 35 to 0 will enable the channel secure DMA transfer. Set the bit 35 to 1 will enable the channel non-secure DMAC transfer. 备注 if user not define DMAC_SECURE_MODE, it only can be readed.
2:1	RSVD	R	-	Reserved
0	CFG5_H_FCMODE	R/W	0x0	Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are servied when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs. Data pre-fetching is disabled. 备注 Please keep this bit 0 when Transfer Type and Flow Control is not ”destination peripheral is the flow controller and transfer type is peripheral to peripheral” (TT_FC!=7).

REG_SAR6

• Name: Channel 6 Source Address Register

• Size: 32

• Address offset: 210h

• Read/write access: R/W

Source address register for DMA channel x, specifies the source memory address

Bit	Symbol	Access	INI	Description
31:0	SAR6	R/W	Unknown	Source Address of DMA transfer.Updated after each source transfer. The SINC field in the CTLx register determines whether the address increments, or is left unchanged on every source transfer throughout the block transfer.

REG_CURR_SAR6

• Name: The read back value is channel 6 source reading address at present

• Size: 32

• Address offset: 214h

• Read/write access: R

Current source address register for DMA channel x, indicates the current source address during

transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_SAR6	R	0x0	The read back value is source reading address at present

REG_DAR6

• Name: Channel 6 Destination Address Register

• Size: 32

• Address offset: 218h

• Read/write access: R/W

Destination address register for DMA channel x, specifies the destination memory address

Bit	Symbol	Access	INI	Description
31:0	DAR6	R/W	Unknown	Destination address of DMA transfer.Updated after each destination transfer. The DINC field in the CTLx register determines whether the address increments, or is left unchanged on every destination transfer throughout the block transfer.

REG_CURR_DAR6

• Name: The read back value is channel 6 destination writing address at present

• Size: 32

• Address offset: 21Ch

• Read/write access: R

Current destination address register for DMA channel x, indicates the current destination address

during transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_DAR6	R	0x0	The read back value is destination writing address at present

REG_LLP6_L

• Name: Channel 6 low-32 bits Linked List Pointer Register

• Size: 32

• Address offset: 220h

• Read/write access: R/W

Linked list pointer register low for DMA channel x, points to the starting address of linked list

item

Bit	Symbol	Access	INI	Description
31:2	LLP6_L_LOC	R/W	Unknown	Starting Address In Memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary.LLI accesses are always 32-bit accesses aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit.
1:0	RSVD	R	-	Reserved

REG_CTL6_L

• Name: Channel 6 low-32 bits Control Register

• Size: 32

• Address offset: 228h

• Read/write access: R/W

Control register low for DMA channel x, configures channel control settings

Bit	Symbol	Access	INI	Description
31:29	RSVD	R	-	Reserved
28	CTL6_L_LLP_SRC_EN	R/W	0x0	Block chanining is enabled on the source side only if the LLP_SRC_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
27	CTL6_L_LLP_DST_EN	R/W	0x0	Block chanining is enabled on the destination side only if the LLP_DST_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
26:23	RSVD	R	-	Reserved
22:20	CTL6_L_TT_FC	R/W	0x0	Transfer Type and Flow Control.The following transfer types are supported. Memory to Memory Memory to Peripheral Peripheral to Memory Peripheral to Peripheral Flow Control can be assigned to the RTK_DMAC, the source peripheral, or the destination peripheral. Table 6-4 lists the decoding for this field. For more information on transfer types and flow control, refer to “Setup/Operation of RTK_DMAC Transfers”. Reset Value: 3’h0 Dependencies: If hardware handshake isn’t support, then TT_FC can only be set to 3’b0. TT_FC[2] can only be read.
19	RSVD	R	-	Reserved
18	CTL6_L_DST_SCATTER_EN	R/W	0x0	Destination scatter enable bit:0 = Scatter disabled1 = Scatter enabledScatter on the destination side is applicable only when the CTLx_L.DINC bit indicates an incrementing address control and DARx should be aligned with DST_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_DST_SCA_EN is not selected.
17	CTL6_L_SRC_GATHER_EN	R/W	0x0	Source gather enable bit: 0 = Gather disabled 1 = Gather enabled Gather on the source side is applicable only when the CTLx_L.SINC bit indicates an incrementing address control and SARx should be aligned with SRC_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_SRC_GAT_EN is not selected.
16:14	CTL6_L_SRC_MSIZE	R/W	0x1	Source Burst Transaction Length. Number of data items, each of width CTLx_L.SRC_TR_WIDTH if source is not memory, otherwise each of width DMAC_TR_WIDTH_DEFAULT, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface. Read burst transaction length on bus (ARLen) will not exceed this value, but may be less than this value. If SINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-0 lists the decoding for this field.
13:11	CTL6_L_DEST_MSIZE	R/W	0x1	Destination Burst Transaction Length. Number of data items, each of width DATA_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. Write burst transaction length on bus (AWLen) will not exceed this value, but may be less than this value. If DINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-1 lists the decoding for this field.
10:9	CTL6_L_SINC	R/W	0x0	Source Address Increment. Indicates whether to increment the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to “No change.”If source is memory appointed by CTLx_L.TT_FC, and set SINC=No change, then SRC_TR_WIDTH must be set to BUS width. And DMAC will read data from the fixed memory address until block transfer finish, but It is not recommended to read memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01 =Not support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.SRC_TR_WIDTH boundary.
8:7	CTL6_L_DINC	R/W	0x0	Destination Address Increment. Indicates whether to increment destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change.”If destination is memory appointed by CTLx_L.TT_FC, and set DINC=No change, then DST_TR_WIDTH must be set to BUS width. And DMAC will write data to the fixed memory address until block transfer finish, but It is not recommended to write memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01=Not Support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.DST_TR_WIDTH boundary.
6:4	CTL6_L_SRC_TR_WIDTH	R/W	0x0	Source Transfer Width. Table 6-3 lists the decoding for this field.It can’t be mapped to AXI bus data width directly. Since AXI bus data width is fixed (such as 32bit/64bit), AXI use byte enable signal for byte/half word transfer (still burst). So, the SRC_TR_WIDTH is only used for total block data size calculation and streaming mode byte/half word transfer (for FIFO transfer). 备注 SRC_TR_WIDTH must not be bigger than BUS width.
3:1	CTL6_L_DST_TR_WIDTH	R/W	0x0	Destination Transfer Width.Table 6-3 lists the decoding for this field. It can’t be mapped to AXI bus data width directly. For a non-memory peripheral, typically the peripheral (destination) FIFO width.Note: DST_TR_WIDTH must not be bigger than BUS width
0	CTL6_L_INT_EN	R/W	0x1	Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel; raw* interrupt registers still assert if CTLx_L.INT_EN = 0.

REG_CTL6_H

• Name: Channel 6 high-32 bits Control Register

• Size: 32

• Address offset: 22Ch

• Read/write access: R

Control register high for DMA channel x for block size

Bit	Symbol	Access	INI	Description
31:0	CTL6_H_TRANS_DATA_CNT	R	0x0	Data Transfered Count.Once the transfer starts, the read-back value is the total number of data bytes already write to destination memory or peripheral.

REG_CFG6_L

• Name: Channel 6 low-32 bits Configuration Register

• Size: 32

• Address offset: 250h

• Read/write access: R/W

Configuration register low for DMA channel x, configures transfer parameters

Bit	Symbol	Access	INI	Description
31	CFG6_L_RELOAD_DST	R/W	0x0	Automatic Destination Reload. The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.This register does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
30	CFG6_L_RELOAD_SRC	R/W	0x0	Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. This field does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
29:20	RSVD	R	-	Reserved
19	CFG6_L_SRC_HS_POL	R/W	0x0	Source Handshaking Interface Polarity. 0 = Active high 1 = Active low
18	CFG6_L_DST_HS_POL	R/W	0x0	Destination Handshaking Interface Polarity. 0 = Active high 1 = Active low For information on this, refer to “Handshaking Interface” .
17:12	RSVD	R	-	Reserved
11	CFG6_L_HS_SEL_SRC	R/W	0x1	Source Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for source requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware-initiated transaction requests are ignored. If the source peripheral is memory, then this bit is ignored.
10	CFG6_L_HS_SEL_DST	R/W	0x1	Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for destination requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware- initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored.
9	CFG6_L_FIFO_EMPTY	R	0x1	Indicates if there is data left in the channel FIFO. 1 = Channel FIFO empty 0 = Channel FIFO not empty
8	CFG6_L_CH_SUSP	R/W	0x0	Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx_l.INACTIVE to cleanly disable a channel without losing any data. 0 = Not suspended 1 = Suspend DMA transfer from the source. This field will be reset to 0 after “Disabling a Channel Prior to Transfer Completion” automatically by hardware.For more information, refer to “7.7 Disabling a Channel Prior to Transfer Completion” . 备注 if user not define DMAC_CH*_SUPPORT_SUSPEND, it only can be readed.
7:4	CFG6_L_CH_PRIOR	R/W	0x0	Channel priority. RTK DMAC supports three kinds of channel priority now, fixed priority, round robin priority and programmable priority. The default way is fixed priority to reduce area, and channel0 has the highest priority, channel15 has the lowest priority. Changing the definition of parameter FIX_PRIORITY or Programmable_PRIORITY can change priority way. If RTK DMAC is configured to support Programmable priority, this field will be used to set priority between channels. CH_PRIOR’s legal value is 0 ~ (DMAC_NUM_CHANNELS-1), and 0 is the highest priority value, (DMAC_NUM_CHANNELS-1) is the lowest priroty value. If more than one channel are set with the same priroty value, the channel with small channel number index has higher priority. If DMAC is configured to support fix priority or round-robin priority, this field is not exist. 备注 if user not define ProgrammablePriority, it only can be readed.
3	RSVD	R	-	Reserved
2	CFG6_L_DST_PCTL_OVER	R	0x1	DMA destination bus protocol finish, indicating the current write command has finished.
1	CFG6_L_SRC_PCTL_OVER	R	0x1	DMA Source bus protocol finish, indicating the current read command has finished.
0	CFG6_L_INACTIVE	R	0x1	Indicates if the channel is inactive. Can be used in conjunction with CFGx_L.CH_SUSP to cleanly disable a channel when destination is peripheral. For more information, refer to “Disabling a Channel Prior to Transfer Completion” . 1 = Channel Inactive for axi interface 0 = Channel not Inactive for axi interface

REG_CFG6_H

• Name: Channel 6 high-32 bits Configuration Register

• Size: 32

• Address offset: 254h

• Read/write access: R/W

Configuration register high for DMA channel x, configures additional transfer parameters

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	CFG6_H_EXTENDED_DEST_PER1	R/W	0x0	The extened 4th bit of DEST_PER when hardware handshake interfaces number is configured to 32.
15	CFG6_H_EXTENDED_SRC_PER1	R/W	0x0	The extened 4th bit of SRC_PER when hardware handshake interfaces number is configured to 32.
14:11	CFG6_H_DEST_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the destination of channel x if the FGx.HS_SEL_DST field is 0; otherwise, this field is ignored. The channel can then communicate with the destinationperipheral connected to that interface through the assignedhardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (sourceor destination) should be assigned to the same handshaking interface NOTE2: This field does not exist if the configuration parameterDMAC_NUM_HS_INT is set to 0.
10:7	CFG6_H_SRC_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the source of channel x if the CFGx.HS_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct RTK_DMAC operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. NOTE2: This field does not exist if the configuration parameter DMAC_NUM_HS_INT is set to 0.
6:4	RSVD	R	-	Reserved
3	CFG6_H_PROTCTL	R/W	0x1	Protection Control.Set the bit 35 to 0 will enable the channel secure DMA transfer. Set the bit 35 to 1 will enable the channel non-secure DMAC transfer. 备注 if user not define DMAC_SECURE_MODE, it only can be readed.
2:1	RSVD	R	-	Reserved
0	CFG6_H_FCMODE	R/W	0x0	Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are servied when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs. Data pre-fetching is disabled. 备注 Please keep this bit 0 when Transfer Type and Flow Control is not ”destination peripheral is the flow controller and transfer type is peripheral to peripheral” (TT_FC!=7).

REG_SAR7

• Name: Channel 7 Source Address Register

• Size: 32

• Address offset: 268h

• Read/write access: R/W

Source address register for DMA channel x, specifies the source memory address

Bit	Symbol	Access	INI	Description
31:0	SAR7	R/W	Unknown	Source Address of DMA transfer.Updated after each source transfer. The SINC field in the CTLx register determines whether the address increments, or is left unchanged on every source transfer throughout the block transfer.

REG_CURR_SAR7

• Name: The read back value is channel 7 source reading address at present

• Size: 32

• Address offset: 26Ch

• Read/write access: R

Current source address register for DMA channel x, indicates the current source address during

transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_SAR7	R	0x0	The read back value is source reading address at present

REG_DAR7

• Name: Channel 7 Destination Address Register

• Size: 32

• Address offset: 270h

• Read/write access: R/W

Destination address register for DMA channel x, specifies the destination memory address

Bit	Symbol	Access	INI	Description
31:0	DAR7	R/W	Unknown	Destination address of DMA transfer.Updated after each destination transfer. The DINC field in the CTLx register determines whether the address increments, or is left unchanged on every destination transfer throughout the block transfer.

REG_CURR_DAR7

• Name: The read back value is channel 7 destination writing address at present

• Size: 32

• Address offset: 274h

• Read/write access: R

Current destination address register for DMA channel x, indicates the current destination address

during transfer

Bit	Symbol	Access	INI	Description
31:0	CURR_DAR7	R	0x0	The read back value is destination writing address at present

REG_LLP7_L

• Name: Channel 7 low-32 bits Linked List Pointer Register

• Size: 32

• Address offset: 278h

• Read/write access: R/W

Linked list pointer register low for DMA channel x, points to the starting address of linked list

item

Bit	Symbol	Access	INI	Description
31:2	LLP7_L_LOC	R/W	Unknown	Starting Address In Memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary.LLI accesses are always 32-bit accesses aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit.
1:0	RSVD	R	-	Reserved

REG_CTL7_L

• Name: Channel 7 low-32 bits Control Register

• Size: 32

• Address offset: 280h

• Read/write access: R/W

Control register low for DMA channel x, configures channel control settings

Bit	Symbol	Access	INI	Description
31:29	RSVD	R	-	Reserved
28	CTL7_L_LLP_SRC_EN	R/W	0x0	Block chanining is enabled on the source side only if the LLP_SRC_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
27	CTL7_L_LLP_DST_EN	R/W	0x0	Block chanining is enabled on the destination side only if the LLP_DST_EN field id high and LLPx_L.LOC is non-zero; for more information,see 7.4.1.1 “Block Chaining Using Linked Lists” Dependencies:This field does not exist if the configuration parameterDMAC_CHx_MULTI_BLK_EN is not selected or if DMAC_CHx_HC_LLP is selected; in this case, the read-back value is always 0.
26:23	RSVD	R	-	Reserved
22:20	CTL7_L_TT_FC	R/W	0x0	Transfer Type and Flow Control.The following transfer types are supported. Memory to Memory Memory to Peripheral Peripheral to Memory Peripheral to Peripheral Flow Control can be assigned to the RTK_DMAC, the source peripheral, or the destination peripheral. Table 6-4 lists the decoding for this field. For more information on transfer types and flow control, refer to “Setup/Operation of RTK_DMAC Transfers”. Reset Value: 3’h0 Dependencies: If hardware handshake isn’t support, then TT_FC can only be set to 3’b0. TT_FC[2] can only be read.
19	RSVD	R	-	Reserved
18	CTL7_L_DST_SCATTER_EN	R/W	0x0	Destination scatter enable bit:0 = Scatter disabled1 = Scatter enabledScatter on the destination side is applicable only when the CTLx_L.DINC bit indicates an incrementing address control and DARx should be aligned with DST_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_DST_SCA_EN is not selected.
17	CTL7_L_SRC_GATHER_EN	R/W	0x0	Source gather enable bit: 0 = Gather disabled 1 = Gather enabled Gather on the source side is applicable only when the CTLx_L.SINC bit indicates an incrementing address control and SARx should be aligned with SRC_TR_WIDTH. Dependencies: This field does not exist if DMAC_CHx_SRC_GAT_EN is not selected.
16:14	CTL7_L_SRC_MSIZE	R/W	0x1	Source Burst Transaction Length. Number of data items, each of width CTLx_L.SRC_TR_WIDTH if source is not memory, otherwise each of width DMAC_TR_WIDTH_DEFAULT, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface. Read burst transaction length on bus (ARLen) will not exceed this value, but may be less than this value. If SINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-0 lists the decoding for this field.
13:11	CTL7_L_DEST_MSIZE	R/W	0x1	Destination Burst Transaction Length. Number of data items, each of width DATA_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. Write burst transaction length on bus (AWLen) will not exceed this value, but may be less than this value. If DINC is setted to “no change”, this value should not be greater than 16 to conform to the AXI protocol. If enabled ‘DMAC_CHx_MSIZE_BIGGER_THAN_FIFO_DEPTH’ feature, to improve performance, can set CTLx_L.SRC_MSIZE to a high value to make DMAC send longer burst length command. But to avoid deadlock, if Source slave and Destination slave is the same slave, should not set CTLx_L.SRC_MSIZE over than FIFO_depth; Table 6-2-1 lists the decoding for this field.
10:9	CTL7_L_SINC	R/W	0x0	Source Address Increment. Indicates whether to increment the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to “No change.”If source is memory appointed by CTLx_L.TT_FC, and set SINC=No change, then SRC_TR_WIDTH must be set to BUS width. And DMAC will read data from the fixed memory address until block transfer finish, but It is not recommended to read memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01 =Not support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.SRC_TR_WIDTH boundary.
8:7	CTL7_L_DINC	R/W	0x0	Destination Address Increment. Indicates whether to increment destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change.”If destination is memory appointed by CTLx_L.TT_FC, and set DINC=No change, then DST_TR_WIDTH must be set to BUS width. And DMAC will write data to the fixed memory address until block transfer finish, but It is not recommended to write memory like this, because some memory controller not support fixed burst transaction and may transform the fixed burst transaction to incremental burst transaction. 00 = Increment 01=Not Support 1x = No change 备注 Incrementing is done for alignment to the next CTLx_L.DST_TR_WIDTH boundary.
6:4	CTL7_L_SRC_TR_WIDTH	R/W	0x0	Source Transfer Width. Table 6-3 lists the decoding for this field.It can’t be mapped to AXI bus data width directly. Since AXI bus data width is fixed (such as 32bit/64bit), AXI use byte enable signal for byte/half word transfer (still burst). So, the SRC_TR_WIDTH is only used for total block data size calculation and streaming mode byte/half word transfer (for FIFO transfer). 备注 SRC_TR_WIDTH must not be bigger than BUS width.
3:1	CTL7_L_DST_TR_WIDTH	R/W	0x0	Destination Transfer Width.Table 6-3 lists the decoding for this field. It can’t be mapped to AXI bus data width directly. For a non-memory peripheral, typically the peripheral (destination) FIFO width.Note: DST_TR_WIDTH must not be bigger than BUS width
0	CTL7_L_INT_EN	R/W	0x1	Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel; raw* interrupt registers still assert if CTLx_L.INT_EN = 0.

REG_CTL7_H

• Name: Channel 7 high-32 bits Control Register

• Size: 32

• Address offset: 284h

• Read/write access: R

Control register high for DMA channel x for block size

Bit	Symbol	Access	INI	Description
31:0	CTL7_H_TRANS_DATA_CNT	R	0x0	Data Transfered Count.Once the transfer starts, the read-back value is the total number of data bytes already write to destination memory or peripheral.

REG_CFG7_L

• Name: Channel 7 low-32 bits Configuration Register

• Size: 32

• Address offset: 2A8h

• Read/write access: R/W

Configuration register low for DMA channel x, configures transfer parameters

Bit	Symbol	Access	INI	Description
31	CFG7_L_RELOAD_DST	R/W	0x0	Automatic Destination Reload. The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.This register does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
30	CFG7_L_RELOAD_SRC	R/W	0x0	Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. This field does not exist if the configuration parameter DMAC_CHx_MULTI_BLK_EN is not selected; in this case, the read-back value is always 0.
29:20	RSVD	R	-	Reserved
19	CFG7_L_SRC_HS_POL	R/W	0x0	Source Handshaking Interface Polarity. 0 = Active high 1 = Active low
18	CFG7_L_DST_HS_POL	R/W	0x0	Destination Handshaking Interface Polarity. 0 = Active high 1 = Active low For information on this, refer to “Handshaking Interface” .
17:12	RSVD	R	-	Reserved
11	CFG7_L_HS_SEL_SRC	R/W	0x1	Source Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for source requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware-initiated transaction requests are ignored. If the source peripheral is memory, then this bit is ignored.
10	CFG7_L_HS_SEL_DST	R/W	0x1	Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces – hardware or software – is active for destination requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware- initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored.
9	CFG7_L_FIFO_EMPTY	R	0x1	Indicates if there is data left in the channel FIFO. 1 = Channel FIFO empty 0 = Channel FIFO not empty
8	CFG7_L_CH_SUSP	R/W	0x0	Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx_l.INACTIVE to cleanly disable a channel without losing any data. 0 = Not suspended 1 = Suspend DMA transfer from the source. This field will be reset to 0 after “Disabling a Channel Prior to Transfer Completion” automatically by hardware.For more information, refer to “7.7 Disabling a Channel Prior to Transfer Completion” . 备注 if user not define DMAC_CH*_SUPPORT_SUSPEND, it only can be readed.
7:4	CFG7_L_CH_PRIOR	R/W	0x0	Channel priority. RTK DMAC supports three kinds of channel priority now, fixed priority, round robin priority and programmable priority. The default way is fixed priority to reduce area, and channel0 has the highest priority, channel15 has the lowest priority. Changing the definition of parameter FIX_PRIORITY or Programmable_PRIORITY can change priority way. If RTK DMAC is configured to support Programmable priority, this field will be used to set priority between channels. CH_PRIOR’s legal value is 0 ~ (DMAC_NUM_CHANNELS-1), and 0 is the highest priority value, (DMAC_NUM_CHANNELS-1) is the lowest priroty value. If more than one channel are set with the same priroty value, the channel with small channel number index has higher priority. If DMAC is configured to support fix priority or round-robin priority, this field is not exist. 备注 if user not define ProgrammablePriority, it only can be readed.
3	RSVD	R	-	Reserved
2	CFG7_L_DST_PCTL_OVER	R	0x1	DMA destination bus protocol finish, indicating the current write command has finished.
1	CFG7_L_SRC_PCTL_OVER	R	0x1	DMA Source bus protocol finish, indicating the current read command has finished.
0	CFG7_L_INACTIVE	R	0x1	Indicates if the channel is inactive. Can be used in conjunction with CFGx_L.CH_SUSP to cleanly disable a channel when destination is peripheral. For more information, refer to “Disabling a Channel Prior to Transfer Completion” . 1 = Channel Inactive for axi interface 0 = Channel not Inactive for axi interface

REG_CFG7_H

• Name: Channel 7 high-32 bits Configuration Register

• Size: 32

• Address offset: 2ACh

• Read/write access: R/W

Configuration register high for DMA channel x, configures additional transfer parameters

Bit	Symbol	Access	INI	Description
31:17	RSVD	R	-	Reserved
16	CFG7_H_EXTENDED_DEST_PER1	R/W	0x0	The extened 4th bit of DEST_PER when hardware handshake interfaces number is configured to 32.
15	CFG7_H_EXTENDED_SRC_PER1	R/W	0x0	The extened 4th bit of SRC_PER when hardware handshake interfaces number is configured to 32.
14:11	CFG7_H_DEST_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the destination of channel x if the FGx.HS_SEL_DST field is 0; otherwise, this field is ignored. The channel can then communicate with the destinationperipheral connected to that interface through the assignedhardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (sourceor destination) should be assigned to the same handshaking interface NOTE2: This field does not exist if the configuration parameterDMAC_NUM_HS_INT is set to 0.
10:7	CFG7_H_SRC_PER	R/W	0x0	Assigns a hardware handshaking interface(0 – DMAC_NUM_HS_INT-1) to the source of channel x if the CFGx.HS_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct RTK_DMAC operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. NOTE2: This field does not exist if the configuration parameter DMAC_NUM_HS_INT is set to 0.
6:4	RSVD	R	-	Reserved
3	CFG7_H_PROTCTL	R/W	0x1	Protection Control.Set the bit 35 to 0 will enable the channel secure DMA transfer. Set the bit 35 to 1 will enable the channel non-secure DMAC transfer. 备注 if user not define DMAC_SECURE_MODE, it only can be readed.
2:1	RSVD	R	-	Reserved
0	CFG7_H_FCMODE	R/W	0x0	Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are servied when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs. Data pre-fetching is disabled. 备注 Please keep this bit 0 when Transfer Type and Flow Control is not ”destination peripheral is the flow controller and transfer type is peripheral to peripheral” (TT_FC!=7).

REG_RAWTFR_L

• Name: Raw Status for IntTfr Interrupt

• Size: 32

• Address offset: 2C0h

• Read/write access: R

Raw transfer complete interrupt status register, shows unmasked transfer complete interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	RAWTFR_L_RAW_TFR	R	0x0	Raw interrupt status for chn0-chn15

REG_RAWBLOCK_L

• Name: Raw Status for IntBlock Interrupt

• Size: 32

• Address offset: 2C8h

• Read/write access: R

Raw block transfer complete interrupt status register, shows unmasked block transfer complete

interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	RAWBLOCK_L_RAW_BLOCK	R	0x0	Raw interrupt status for chn0-chn15

REG_RAWERR_L

• Name: Raw Status for IntErr Interrupt(protocol error)

• Size: 32

• Address offset: 2E0h

• Read/write access: R

Raw error interrupt status register low, shows unmasked protocol error interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	RAWERR_L_RAW_ERR	R	0x0	Raw interrupt status for chn0-chn15. (Protocol error)

REG_RAWERR_H

• Name: Raw Status for non-secure access secure register error if defined

• Size: 32

• Address offset: 2E4h

• Read/write access: R

Raw error interrupt status register high, shows unmasked secure error interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	RAWERR_H_RAW_ERR	R	0x0	Raw interrupt status. (Non-secure access secure register error) if DMAC_SECURE_MODE has been defined; else it is reserved.

REG_STATUSTFR_L

• Name: Status for IntTfr Interrupt

• Size: 32

• Address offset: 2E8h

• Read/write access: R

Transfer complete interrupt status register, shows masked transfer complete interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	STATUSTFR_L_STATUS_TFR	R	0x0	Interrupt status for chn0-chn15

REG_STATUSBLOCK_L

• Name: Status for IntBlock Interrupt

• Size: 32

• Address offset: 2F0h

• Read/write access: R

Block transfer complete interrupt status register, shows masked block transfer complete interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	STATUSBLOCK_L_STATUS_BLOCK	R	0x0	Interrupt status for chn0-chn15

REG_STATUSERR_L

• Name: Status for IntErr Interrupt

• Size: 32

• Address offset: 308h

• Read/write access: R

Error interrupt status register low, shows masked protocol error interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	STATUSERR_L_STATUS_ERR	R	0x0	Interrupt status for chn0-chn15. (Protocol error)

REG_STATUSERR_H

• Name: Status for non-secure access secure register error if defined

• Size: 32

• Address offset: 30Ch

• Read/write access: R

Error interrupt status register high, shows masked secure error interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	STATUSERR_H_STATUS_ERR	R	0x0	Interrupt status. (Non-secure access secure register error, Sec Error) if DMAC_SECURE_MODE has been defined; else it is reserved.

REG_MASKTFR_L

• Name: Mask for IntTfr Interrupt (chn0-7)

• Size: 32

• Address offset: 310h

• Read/write access: R/W

Transfer complete interrupt mask register, enables or disables transfer complete interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:8	MASKTFR_L_INT_MASK_WE	R/W	0x0	Interrupt Mask Write Enable(chn0-chn7) 0 = write disabled 1 = write enabled
7:0	MASKTFR_L_INT_MASK	R/W	0x0	Interrupt Mask(chn0-chn7) 0 = masked 1 = unmasked

REG_MASKBLOCK_L

• Name: Mask for IntBlock Interrupt

• Size: 32

• Address offset: 318h

• Read/write access: R/W

Block transfer complete interrupt mask register, enables or disables block transfer complete

interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:8	MASKBLOCK_L_INT_MASK_WE	R/W	0x0	Interrupt Mask Write Enable(chn0-chn7) 0 = write disabled 1 = write enabled
7:0	MASKBLOCK_L_INT_MASK	R/W	0x0	Interrupt Mask(chn0-chn7) 0 = masked 1 = unmasked

REG_MASKERR_L

• Name: Mask for IntErr Interrupt

• Size: 32

• Address offset: 330h

• Read/write access: R/W

Error interrupt mask register low, enables or disables protocol error interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:8	MASKERR_L_INT_MASK_WE	R/W	0x0	Interrupt Mask Write Enable(chn0-chn7) 0 = write disabled 1 = write enabled
7:0	MASKERR_L_INT_MASK	R/W	0x0	Interrupt Mask(chn0-chn7) 0 = masked 1 = unmasked

REG_MASKERR_H

• Name: Mask for non-secure access secure register error if defined

• Size: 32

• Address offset: 334h

• Read/write access: R/W

Error interrupt mask register high, enables or disables secure error interrupts

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:8	MASKERR_H_INT_MASK_WE	R/W	0x0	Interrupt Mask Write Enable(chn0-chn7) 0 = write disabled 1 = write enabled These bits only exist when DMAC_ SECURE_MODE has beed defined
7:0	MASKERR_H_INT_MASK	R/W	0x0	Interrupt Mask(chn0-chn7) 0 = masked 1 = unmasked These bits only exist when DMAC_ SECURE_MODE has beed defined

REG_CLEARTFR_L

• Name: Clear for IntTfr Interrupt

• Size: 32

• Address offset: 338h

• Read/write access: R/W

Transfer complete interrupt clear register, clears transfer complete interrupt status

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	CLEARTFR_L_CLEAR_TFR	R/W	0x0	Interrupt clear for chn0-chn15 0 = no effect 1= clear interrupt

REG_CLEARBLOCK_L

• Name: Clear for IntBlock Interrupt

• Size: 32

• Address offset: 340h

• Read/write access: R/W

Block transfer complete interrupt clear register, clears block transfer complete interrupt status

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	CLEARBLOCK_L_CLEAR_BLOCK	R/W	0x0	Interrupt clear for chn0-chn15

REG_CLEARERR_L

• Name: Clear for IntErr Interrupt

• Size: 32

• Address offset: 358h

• Read/write access: R/W

Error interrupt clear register low, clears protocol error interrupt status

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	CLEARERR_L_CLEAR_PROTOCOL_ERROR	R/W	0x0	Interrupt clear for chn0-chn15. (Protocol error)

REG_CLEARERR_H

• Name: Clear for non-secure access secure register error if defined

• Size: 32

• Address offset: 35Ch

• Read/write access: R/W

Error interrupt clear register high, clears secure error interrupt status

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	CLEARERR_H_CLEAR_SEC_ERROR	R/W	0x0	Interrupt clear for chn0-chn15 (Non-secure access secure register error, Sec Error) when DMAC_SECURE_MODE has beed defined, else it is reserved;

REG_STATUSINT_L

• Name: Combined Interrupt Sataus Register

• Size: 32

• Address offset: 360h

• Read/write access: R

Interrupt status register low, shows combined interrupt status

Bit	Symbol	Access	INI	Description
31:5	RSVD	R	-	Reserved
4	STATUSINT_L_ERROR	R	0x0	OR of the contents of StatusErr register.
3:2	RSVD	R	-	Reserved
1	STATUSINT_L_BLOCK	R	0x0	OR of the contents of StatusBlock register.
0	STATUSINT_L_TFR	R	0x0	OR of the contents of StatusTfr register.

REG_STATUSINT_H

• Name: Combined Interrupt Sataus Register

• Size: 32

• Address offset: 364h

• Read/write access: R

Interrupt status register high, shows combined interrupt status

Bit	Symbol	Access	INI	Description
31:0	RSVD	R	-	Reserved

REG_DMACFGREG_L

• Name: DMA low-32 bits Configuration Register

• Size: 32

• Address offset: 398h

• Read/write access: R/W

DMA configuration register, configures global DMA controller settings

Bit	Symbol	Access	INI	Description
31:1	RSVD	R	-	Reserved
0	DMACFGREG_L_DMA_EN	R/W	0x1	RTK_DMAC Enable bit. 0 = RTK_DMAC Disabled 1 = RTK_DMAC Enabled

REG_CHENREG_L_1

• Name: DMA low-32 bits Channel Enable Register if configed chn number is less than or equal to 8

• Size: 32

• Address offset: 3A0h

• Read/write access: R/W

Channel enable register, enables or disables DMA channels

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:8	CHENREG_L_1_CH_EN_WE	R/W	0x0	Channel enable write enable.
7:0	CHENREG_L_1_CH_EN	R/W	0x0	Enables/Disables the channel. Setting this bit enables a channel; clearing this bit disables the channel. 0 = Disable the Channel 1 = Enable the Channel The CHENREG_L.CH_EN bit is automatically cleared by hardware to disable the channel after the last AXI transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

REG_DMAIDREG_L

• Name: DMA low-32 bits ID Register

• Size: 32

• Address offset: 3A8h

• Read/write access: R

DMA ID register, Hardcoded RTK_DMAC peripheral ID

Bit	Symbol	Access	INI	Description
31:0	DMAIDREG_L_DMA_ID	R	32'h22101416	Hardcoded RTK_DMAC Peripheral ID

REG_DMA_COMP_PARAMS_6_L

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3C8h

• Read/write access: R

DMA component parameters register 6 low, contains component identification information

Bit	Symbol	Access	INI	Description
31:24	CH7_MAX_BLK_SIZE	R	0x10	The value of this register is derived from the DMAC_CH7_MAX_BLK_SIZE from config_form.vh CH7_MAX_BLK_SIZE = log2(DMAC_CH7_MAX_BLK_SIZE) + 1
23:16	CH6_MAX_BLK_SIZE	R	0x10	The value of this register is derived from the DMAC_CH6_MAX_BLK_SIZE from config_form.vh CH6_MAX_BLK_SIZE = log2(DMAC_CH6_MAX_BLK_SIZE) + 1
15:8	CH5_MAX_BLK_SIZE	R	0x10	The value of this register is derived from the DMAC_CH5_MAX_BLK_SIZE from config_form.vh CH5_MAX_BLK_SIZE = log2(DMAC_CH5_MAX_BLK_SIZE) + 1
7:0	CH4_MAX_BLK_SIZE	R	0x10	The value of this register is derived from the DMAC_CH4_MAX_BLK_SIZE from config_form.vh CH4_MAX_BLK_SIZE = log2(DMAC_CH4_MAX_BLK_SIZE) + 1

REG_DMA_COMP_PARAMS_6_H

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3CCh

• Read/write access: R

DMA component parameters register 6 high, contains component identification information

Bit	Symbol	Access	INI	Description
31	RSVD	R	-	Reserved
30:28	CH7_FIFO_DEPTH	R	0x2	The value of this register is derived from the DMAC_CH7_FIFO_DEPTH parameter. Default value is 0x0. CH7_FIFO_DEPTH = log2(DMAC_CH7_FIFO_DEPTH/8) 0x0 = 8 bytes 0x1 = 16 0x2 = 32 0x3 = 64 0x4 = 128 0x5 = Reserved 0x6 = Reserved 0x7 = Reserved
27:19	RSVD	R	-	Reserved
18:16	CH7_MAX_MULT_SIZE	R	0x3	The value of this register is derived from the DMAC_CH7_MULT_SIZE parameter. Maxium burst transaction size. CH7_MAX_MULT_SIZE = log2(256/DMAC_DATA_WIDTH) 0x3 = 32 bits 0x2 = 64 bits 0x1 = 128 bits
15:14	CH7_FC	R	0x3	The value of this register is derived from the DMAC_CH7_FC parameter. 0x0 = DMA 0x1 = SRC 0x2 = DST 0x3 = ANY
13	CH7_HC_LLP	R	0x0	The value of this register is derived from the DMAC_CH7_HC_LLP parameter. 0x0 = FALSE 0x1 = TRUE
12	CH7_CTL_WB_EN	R	0x0	The value of this register is derived from the DMAC_CH7_CTL_WB_EN parameter. 0x0 = FALSE 0x1 = TRUE
11	CH7_MULTI_BLK_EN	R	0x1	The value of this register is derived from the DMAC_CH7_CTL_WB_EN parameter. 0x0 = FALSE 0x1 = TRUE
10	CH7_LOCK_EN	R	0x0	The value of this register is derived from the DMAC_CH7_LOCK_EN parameter. 0x0 = FALSE 0x1 = TRUE
9	CH7_SRC_GAT_EN	R	0x0	The value of this register is derived from the DMAC_CH7_SRC_GAT_EN parameter. For a description of this parameter, refer to page 112. 0x0 = FALSE 0x1 = TRUE
8	CH7_DST_SCA_EN	R	0x0	The value of this register is derived from the DMAC_CH7_DST_SCA_EN parameter. 0x0 = FALSE 0x1 = TRUE
7	CH7_STAT_SRC	R	0x0	The value of this register is derived from the DMAC_CH7_STAT_SRC parameter. 0x0 = FALSE 0x1 = TRUE
6	CH7_STAT_DST	R	0x0	The value of this register is derived from the DMAC_CH7_STAT_DST parameter. 0x0 = FALSE 0x1 = TRUE
5:3	CH7_STW	R	0x3	The value of this register is derived from the DMAC_CH7_STW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved
2:0	CH7_DTW	R	0x3	The value of this register is derived from the DMAC_CH7_DTW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved

REG_DMA_COMP_PARAMS_5_L

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3D0h

• Read/write access: R

DMA component parameters register 5 low, contains component identification information

Bit	Symbol	Access	INI	Description
31	RSVD	R	-	Reserved
30:28	CH6_FIFO_DEPTH	R	0x2	The value of this register is derived from the DMAC_CH6_FIFO_DEPTH parameter. Default value is 0x0. 0x0 = 8 bytes 0x1 = 16 0x2 = 32 0x3 = 64 0x4 = 128 0x5 = Reserved 0x6 = Reserved 0x7 = Reserved
27:19	RSVD	R	-	Reserved
18:16	CH6_MAX_MULT_SIZE	R	0x3	The value of this register is derived from the DMAC_CH6_MULT_SIZE parameter. Maxium burst transaction size. CH6_MAX_MULT_SIZE = log2(256/DMAC_DATA_WIDTH) 0x3 = 32 bits 0x2 = 64 bits 0x1 = 128 bits
15:14	CH6_FC	R	0x3	The value of this register is derived from the DMAC_CH6_FC parameter. 0x0 = DMA 0x1 = SRC 0x2 = DST 0x3 = ANY
13	CH6_HC_LLP	R	0x0	The value of this register is derived from the DMAC_CH6_HC_LLP parameter. 0x0 = FALSE 0x1 = TRUE
12	CH6_CTL_WB_EN	R	0x0	The value of this register is derived from the DMAC_CH6_CTL_WB_EN parameter. 0x0 = FALSE 0x1 = TRUE
11	CH6_MULTI_BLK_EN	R	0x1	The value of this register is derived from the DMAC_CH6_MULTI_BLK_EN parameter. 0x0 = FALSE 0x1 = TRUE
10	CH6_LOCK_EN	R	0x0	The value of this register is derived from the DMAC_CH6_LOCK_EN parameter. 0x0 = FALSE 0x1 = TRUE
9	CH6_SRC_GAT_EN	R	0x0	The value of this register is derived from the DMAC_CH6_SRC_GAT_EN parameter. 0x0 = FALSE 0x1 = TRUE
8	CH6_DST_SCA_EN	R	0x0	The value of this register is derived from the DMAC_CH6_DST_SCA_EN parameter. 0x0 = FALSE 0x1 = TRUE
7	CH6_STAT_SRC	R	0x0	The value of this register is derived from the DMAC_CH6_STAT_SRC parameter. 0x0 = FALSE 0x1 = TRUE
6	CH6_STAT_DST	R	0x0	The value of this register is derived from the DMAC_CH6_STAT_DST parameter. 0x0 = FALSE 0x1 = TRUE
5:3	CH6_STW	R	0x3	The value of this register is derived from the DMAC_CH6_STW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved
2:0	CH6_DTW	R	0x3	The value of this register is derived from the DMAC_CH6_DTW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved

REG_DMA_COMP_PARAMS_5_H

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3D4h

• Read/write access: R

DMA component parameters register 5 high, contains component identification information

Bit	Symbol	Access	INI	Description
31	RSVD	R	-	Reserved
30:28	CH5_FIFO_DEPTH	R	0x2	The value of this register is derived from the DMAC_CH5_FIFO_DEPTH parameter. Default value is 0x0. 0x0 = 8 bytes 0x1 = 16 0x2 = 32 0x3 = 64 0x4 = 128 0x5 = Reserved 0x6 = Reserved 0x7 = Reserved
27:19	RSVD	R	-	Reserved
18:16	CH5_MAX_MULT_SIZE	R	0x3	The value of this register is derived from the DMAC_CH5_MULT_SIZE parameter. Maxium burst transaction size. CH5_MAX_MULT_SIZE = log2(256/DMAC_DATA_WIDTH) 0x3 = 32 bits 0x2 = 64 bits 0x1 = 128 bits
15:14	CH5_FC	R	0x3	The value of this register is derived from the DMAC_CH5_FC parameter. 0x0 = DMA 0x1 = SRC 0x2 = DST 0x3 = ANY
13	CH5_HC_LLP	R	0x0	The value of this register is derived from the DMAC_CH5_HC_LLP parameter. 0x0 = FALSE 0x1 = TRUE
12	CH5_CTL_WB_EN	R	0x0	The value of this register is derived from the DMAC_CH5_CTL_WB_EN parameter. 0x0 = FALSE 0x1 = TRUE
11	CH5_MULTI_BLK_EN	R	0x1	The value of this register is derived from the DMAC_CH5_MULTI_BLK_EN parameter. 0x0 = FALSE 0x1 = TRUE
10	CH5_LOCK_EN	R	0x0	The value of this register is derived from the DMAC_CH5_LOCK_EN parameter. 0x0 = FALSE 0x1 = TRUE
9	CH5_SRC_GAT_EN	R	0x0	The value of this register is derived from the DMAC_CH5_SRC_GAT_EN parameter. For a description of this parameter, refer to page 112. 0x0 = FALSE 0x1 = TRUE
8	CH5_DST_SCA_EN	R	0x0	The value of this register is derived from the DMAC_CH5_DST_SCA_EN parameter. 0x0 = FALSE 0x1 = TRUE
7	CH5_STAT_SRC	R	0x0	The value of this register is derived from the DMAC_CH5_STAT_SRC parameter. 0x0 = FALSE 0x1 = TRUE
6	CH5_STAT_DST	R	0x0	The value of this register is derived from the DMAC_CH5_STAT_DST parameter. 0x0 = FALSE 0x1 = TRUE
5:3	CH5_STW	R	0x3	The value of this register is derived from the DMAC_CH5_STW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved
2:0	CH5_DTW	R	0x3	The value of this register is derived from the DMAC_CH5_DTW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved

REG_DMA_COMP_PARAMS_4_L

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3D8h

• Read/write access: R

DMA component parameters register 4 low, contains component identification information

Bit	Symbol	Access	INI	Description
31	RSVD	R	-	Reserved
30:28	CH4_FIFO_DEPTH	R	0x2	The value of this register is derived from the DMAC_CH4_FIFO_DEPTH parameter. Default value is 0x0. 0x0 = 8 bytes 0x1 = 16 0x2 = 32 0x3 = 64 0x4 = 128 0x5 = Reserved 0x6 = Reserved 0x7 = Reserved
27:19	RSVD	R	-	Reserved
18:16	CH4_MAX_MULT_SIZE	R	0x3	The value of this register is derived from the DMAC_CH4_MULT_SIZE parameter. Maxium burst transaction size. CH4_MAX_MULT_SIZE = log2(256/DMAC_DATA_WIDTH) 0x3 = 32 bits 0x2 = 64 bits 0x1 = 128 bits
15:14	CH4_FC	R	0x3	The value of this register is derived from the DMAC_CH4_FC parameter. 0x0 = DMA 0x1 = SRC 0x2 = DST 0x3 = ANY
13	CH4_HC_LLP	R	0x0	The value of this register is derived from the DMAC_CH4_HC_LLP parameter. 0x0 = FALSE 0x1 = TRUE
12	CH4_CTL_WB_EN	R	0x0	The value of this register is derived from the DMAC_CH4_CTL_WB_EN parameter. 0x0 = FALSE 0x1 = TRUE
11	CH4_MULTI_BLK_EN	R	0x1	The value of this register is derived from the DMAC_CH4_MULTI_BLK_EN parameter. 0x0 = FALSE 0x1 = TRUE
10	CH4_LOCK_EN	R	0x0	The value of this register is derived from the DMAC_CH4_LOCK_EN parameter. 0x0 = FALSE 0x1 = TRUE
9	CH4_SRC_GAT_EN	R	0x0	The value of this register is derived from the DMAC_CH4_SRC_GAT_EN parameter. For a description of this parameter, refer to page 112.0x0 = FALSE 0x1 = TRUE
8	CH4_DST_SCA_EN	R	0x0	The value of this register is derived from the DMAC_CH4_DST_SCA_EN parameter. 0x0 = FALSE 0x1 = TRUE
7	CH4_STAT_SRC	R	0x0	The value of this register is derived from the DMAC_CH4_STAT_SRC parameter. 0x0 = FALSE 0x1 = TRUE
6	CH4_STAT_DST	R	0x0	The value of this register is derived from the DMAC_CH4_STAT_DST parameter. 0x0 = FALSE 0x1 = TRUE
5:3	CH4_STW	R	0x3	The value of this register is derived from the DMAC_CH4_STW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved
2:0	CH4_DTW	R	0x3	The value of this register is derived from the DMAC_CH4_DTW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved

REG_DMA_COMP_PARAMS_4_H

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3DCh

• Read/write access: R

DMA component parameters register 4 high, contains component identification information

Bit	Symbol	Access	INI	Description
31	RSVD	R	-	Reserved
30:28	CH3_FIFO_DEPTH	R	0x2	The value of this register is derived from the DMAC_CH3_FIFO_DEPTH parameter. Default value is 0x0. 0x0 = 8 bytes 0x1 = 16 0x2 = 32 0x3 = 64 0x4 = 128 0x5 = Reserved 0x6 = Reserved 0x7 = Reserved
27:19	RSVD	R	-	Reserved
18:16	CH3_MAX_MULT_SIZE	R	0x3	The value of this register is derived from the DMAC_CH3_MULT_SIZE parameter. Maxium burst transaction size. CH3_MAX_MULT_SIZE = log2(256/DMAC_DATA_WIDTH) 0x3 = 32 bits 0x2 = 64 bits 0x1 = 128 bits
15:14	CH3_FC	R	0x3	The value of this register is derived from the DMAC_CH3_FC parameter. 0x0 = DMA 0x1 = SRC 0x2 = DST 0x3 = ANY
13	CH3_HC_LLP	R	0x0	The value of this register is derived from the DMAC_CH3_HC_LLP parameter. 0x0 = FALSE 0x1 = TRUE
12	CH3_CTL_WB_EN	R	0x0	The value of this register is derived from the DMAC_CH3_CTL_WB_EN parameter. 0x0 = FALSE 0x1 = TRUE
11	CH3_MULTI_BLK_EN	R	0x1	The value of this register is derived from the DMAC_CH3_MULTI_BLK_EN parameter. 0x0 = FALSE 0x1 = TRUE
10	CH3_LOCK_EN	R	0x0	The value of this register is derived from the DMAC_CH3_LOCK_EN parameter. 0x0 = FALSE 0x1 = TRUE
9	CH3_SRC_GAT_EN	R	0x0	The value of this register is derived from the DMAC_CH3_SRC_GAT_EN parameter. 0x0 = FALSE 0x1 = TRUE
8	CH3_DST_SCA_EN	R	0x0	The value of this register is derived from the DMAC_CH3_DST_SCA_EN parameter. 0x0 = FALSE 0x1 = TRUE
7	CH3_STAT_SRC	R	0x0	The value of this register is derived from the DMAC_CH3_STAT_SRC parameter. 0x0 = FALSE 0x1 = TRUE
6	CH3_STAT_DST	R	0x0	The value of this register is derived from the DMAC_CH3_STAT_DST parameter. 0x0 = FALSE 0x1 = TRUE
5:3	CH3_STW	R	0x3	The value of this register is derived from the DMAC_CH3_STW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved
2:0	CH3_DTW	R	0x3	The value of this register is derived from the DMAC_CH3_DTW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved

REG_DMA_COMP_PARAMS_3_L

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3E0h

• Read/write access: R

DMA component parameters register 3 low, contains component identification information

Bit	Symbol	Access	INI	Description
31	RSVD	R	-	Reserved
30:28	CH2_FIFO_DEPTH	R	0x2	The value of this register is derived from the DMAC_CH2_FIFO_DEPTH parameter. Default value is 0x0. 0x0 = 8 bytes 0x1 = 16 0x2 = 32 0x3 = 64 0x4 = 128 0x5 = Reserved 0x6 = Reserved 0x7 = Reserved
27:19	RSVD	R	-	Reserved
18:16	CH2_MAX_MULT_SIZE	R	0x3	The value of this register is derived from the DMAC_CH2_MULT_SIZE parameter. Maxium burst transaction size. CH2_MAX_MULT_SIZE = log2(256/DMAC_DATA_WIDTH) 0x3 = 32 bits 0x2 = 64 bits 0x1 = 128 bits
15:14	CH2_FC	R	0x3	The value of this register is derived from the DMAC_CH2_FC parameter. 0x0 = DMA 0x1 = SRC 0x2 = DST 0x3 = ANY
13	CH2_HC_LLP	R	0x0	The value of this register is derived from the DMAC_CH2_HC_LLP parameter. 0x0 = FALSE 0x1 = TRUE
12	CH2_CTL_WB_EN	R	0x0	The value of this register is derived from the DMAC_CH2_CTL_WB_EN parameter. 0x0 = FALSE 0x1 = TRUE
11	CH2_MULTI_BLK_EN	R	0x1	The value of this register is derived from the DMAC_CH2_MULTI_BLK_EN parameter. 0x0 = FALSE 0x1 = TRUE
10	CH2_LOCK_EN	R	0x0	The value of this register is derived from the DMAC_CH2_LOCK_EN parameter. 0x0 = FALSE 0x1 = TRUE
9	CH2_SRC_GAT_EN	R	0x0	The value of this register is derived from the DMAC_CH2_SRC_GAT_EN parameter. For a description of this parameter, refer to page 112. 0x0 = FALSE 0x1 = TRUE
8	CH2_DST_SCA_EN	R	0x0	The value of this register is derived from the DMAC_CH2_DST_SCA_EN parameter. 0x0 = FALSE 0x1 = TRUE
7	CH2_STAT_SRC	R	0x0	The value of this register is derived from the DMAC_CH2_STAT_SRC parameter. 0x0 = FALSE 0x1 = TRUE
6	CH2_STAT_DST	R	0x0	The value of this register is derived from the DMAC_CH2_STAT_DST parameter. 0x0 = FALSE 0x1 = TRUE
5:3	CH2_STW	R	0x3	The value of this register is derived from the DMAC_CH2_STW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved
2:0	CH2_DTW	R	0x3	The value of this register is derived from the DMAC_CH2_DTW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved

REG_DMA_COMP_PARAMS_3_H

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3E4h

• Read/write access: R

DMA component parameters register 3 high, contains component identification information

Bit	Symbol	Access	INI	Description
31	RSVD	R	-	Reserved
30:28	CH1_FIFO_DEPTH	R	0x4	The value of this register is derived from the DMAC_CH1_FIFO_DEPTH parameter. Default value is 0x0. 0x0 = 8 bytes 0x1 = 16 0x2 = 32 0x3 = 64 0x4 = 128 0x5 = Reserved 0x6 = Reserved 0x7 = Reserved
27:19	RSVD	R	-	Reserved
18:16	CH1_MAX_MULT_SIZE	R	0x3	The value of this register is derived from the DMAC_CH1_MULT_SIZE parameter. Maxium burst transaction size. CH1_MAX_MULT_SIZE = log2(256/DMAC_DATA_WIDTH) 0x3 = 32 bits 0x2 = 64 bits 0x1 = 128 bits
15:14	CH1_FC	R	0x3	The value of this register is derived from the DMAC_CH1_FC parameter. 0x0 = DMA 0x1 = SRC 0x2 = DST 0x3 = ANY
13	CH1_HC_LLP	R	0x0	The value of this register is derived from the DMAC_CH1_HC_LLP parameter. 0x0 = FALSE 0x1 = TRUE
12	CH1_CTL_WB_EN	R	0x0	The value of this register is derived from the DMAC_CH1_CTL_WB_EN parameter. 0x0 = FALSE 0x1 = TRUE
11	CH1_MULTI_BLK_EN	R	0x1	The value of this register is derived from the DMAC_CH1_MULTI_BLK_EN parameter. 0x0 = FALSE 0x1 = TRUE
10	CH1_LOCK_EN	R	0x0	The value of this register is derived from the DMAC_CH1_LOCK_EN parameter. 0x0 = FALSE 0x1 = TRUE
9	CH1_SRC_GAT_EN	R	0x0	The value of this register is derived from the DMAC_CH1_SRC_GAT_EN parameter. 0x0 = FALSE 0x1 = TRUE
8	CH1_DST_SCA_EN	R	0x0	The value of this register is derived from the DMAC_CH1_DST_SCA_EN parameter. 0x0 = FALSE 0x1 = TRUE
7	CH1_STAT_SRC	R	0x0	The value of this register is derived from the DMAC_CH1_STAT_SRC parameter. 0x0 = FALSE 0x1 = TRUE
6	CH1_STAT_DST	R	0x0	The value of this register is derived from the DMAC_CH1_STAT_DST parameter. 0x0 = FALSE 0x1 = TRUE
5:3	CH1_STW	R	0x3	The value of this register is derived from the DMAC_CH1_STW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved
2:0	CH1_DTW	R	0x3	The value of this register is derived from the DMAC_CH1_DTW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved

REG_DMA_COMP_PARAMS_2_L

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3E8h

• Read/write access: R

DMA component parameters register 2 low, contains component identification information

Bit	Symbol	Access	INI	Description
31	RSVD	R	-	Reserved
30:28	CH0_FIFO_DEPTH	R	0x4	The value of this register is derived from the DMAC_CH0_FIFO_DEPTH parameter. Default value is 0x0. 0x0 = 8 bytes 0x1 = 16 0x2 = 32 0x3 = 64 0x4 = 128 0x5 = Reserved 0x6 = Reserved 0x7 = Reserved
27:19	RSVD	R	-	Reserved
18:16	CH0_MAX_MULT_SIZE	R	0x3	The value of this register is derived from the DMAC_CH0_MULT_SIZE parameter. Maxium burst transaction size. CH0_MAX_MULT_SIZE = log2(256/DMAC_DATA_WIDTH) 0x3 = 32 bits 0x2 = 64 bits 0x1 = 128 bits
15:14	CH0_FC	R	0x3	The value of this register is derived from the DMAC_CH0_FC parameter. 0x0 = DMA 0x1 = SRC 0x2 = DST 0x3 = ANY
13	CH0_HC_LLP	R	0x0	The value of this register is derived from the DMAC_CH0_HC_LLP parameter. 0x0 = FALSE 0x1 = TRUE
12	CH0_CTL_WB_EN	R	0x0	The value of this register is derived from the DMAC_CH0_CTL_WB_EN parameter. 0x0 = FALSE 0x1 = TRUE
11	CH0_MULTI_BLK_EN	R	0x1	The value of this register is derived from the DMAC_CH0_MULTI_BLK_EN parameter. 0x0 = FALSE 0x1 = TRUE
10	CH0_LOCK_EN	R	0x0	The value of this register is derived from the DMAC_CH0_LOCK_EN parameter. 0x0 = FALSE 0x1 = TRUE
9	CH0_SRC_GAT_EN	R	0x0	The value of this register is derived from the DMAC_CH0_SRC_GAT_EN parameter. For a description of this parameter, refer to page 112. 0x0 = FALSE 0x1 = TRUE
8	CH0_DST_SCA_EN	R	0x0	The value of this register is derived from the DMAC_CH0_DST_SCA_EN parameter. 0x0 = FALSE 0x1 = TRUE
7	CH0_STAT_SRC	R	0x0	The value of this register is derived from the DMAC_CH0_STAT_SRC parameter. 0x0 = FALSE 0x1 = TRUE
6	CH0_STAT_DST	R	0x0	The value of this register is derived from the DMAC_CH0_STAT_DST parameter. 0x0 = FALSE 0x1 = TRUE
5:3	CH0_STW	R	0x3	The value of this register is derived from the DMAC_CH0_STW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved
2:0	CH0_DTW	R	0x3	The value of this register is derived from the DMAC_CH0_DTW parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved

REG_DMA_COMP_PARAMS_2_H

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3ECh

• Read/write access: R

DMA component parameters register 2 high, contains component identification information

Bit	Symbol	Access	INI	Description
31:28	CH7_MULTI_BLK_TYPE	R	0x0	The values of these bit fields are derived from the DMAC_CHx_MULTI_BLK_TYPE parameter. 0x0 = NO_HARDCODE 0x1 = CONT_RELOAD 0x2 = RELOAD_CONT 0x3 = RELOAD_RELOAD 0x4 = CONT_LLP 0x5 = RELOAD_LLP 0x6 = LLP_CONT 0x7 = LLP_RELOAD 0x8 = LLP_LLP
27:24	CH6_MULTI_BLK_TYPE	R	0x0	The values of these bit fields are derived from the DMAC_CHx_MULTI_BLK_TYPE parameter. 0x0 = NO_HARDCODE 0x1 = CONT_RELOAD 0x2 = RELOAD_CONT 0x3 = RELOAD_RELOAD 0x4 = CONT_LLP 0x5 = RELOAD_LLP 0x6 = LLP_CONT 0x7 = LLP_RELOAD 0x8 = LLP_LLP
23:20	CH5_MULTI_BLK_TYPE	R	0x0	The values of these bit fields are derived from the DMAC_CHx_MULTI_BLK_TYPE parameter. 0x0 = NO_HARDCODE 0x1 = CONT_RELOAD 0x2 = RELOAD_CONT 0x3 = RELOAD_RELOAD 0x4 = CONT_LLP 0x5 = RELOAD_LLP 0x6 = LLP_CONT 0x7 = LLP_RELOAD 0x8 = LLP_LLP
19:16	CH4_MULTI_BLK_TYPE	R	0x0	The values of these bit fields are derived from the DMAC_CHx_MULTI_BLK_TYPE parameter. 0x0 = NO_HARDCODE 0x1 = CONT_RELOAD 0x2 = RELOAD_CONT 0x3 = RELOAD_RELOAD 0x4 = CONT_LLP 0x5 = RELOAD_LLP 0x6 = LLP_CONT 0x7 = LLP_RELOAD 0x8 = LLP_LLP
15:12	CH3_MULTI_BLK_TYPE	R	0x0	The values of these bit fields are derived from the DMAC_CHx_MULTI_BLK_TYPE parameter. 0x0 = NO_HARDCODE 0x1 = CONT_RELOAD 0x2 = RELOAD_CONT 0x3 = RELOAD_RELOAD 0x4 = CONT_LLP 0x5 = RELOAD_LLP 0x6 = LLP_CONT 0x7 = LLP_RELOAD 0x8 = LLP_LLP
11:8	CH2_MULTI_BLK_TYPE	R	0x0	The values of these bit fields are derived from the DMAC_CHx_MULTI_BLK_TYPE parameter. 0x0 = NO_HARDCODE 0x1 = CONT_RELOAD 0x2 = RELOAD_CONT 0x3 = RELOAD_RELOAD 0x4 = CONT_LLP 0x5 = RELOAD_LLP 0x6 = LLP_CONT 0x7 = LLP_RELOAD 0x8 = LLP_LLP
7:4	CH1_MULTI_BLK_TYPE	R	0x0	The values of these bit fields are derived from the DMAC_CHx_MULTI_BLK_TYPE parameter. 0x0 = NO_HARDCODE 0x1 = CONT_RELOAD 0x2 = RELOAD_CONT 0x3 = RELOAD_RELOAD 0x4 = CONT_LLP 0x5 = RELOAD_LLP 0x6 = LLP_CONT 0x7 = LLP_RELOAD 0x8 = LLP_LLP
3:0	CH0_MULTI_BLK_TYPE	R	0x0	The values of these bit fields are derived from the DMAC_CHx_MULTI_BLK_TYPE parameter. 0x0 = NO_HARDCODE 0x1 = CONT_RELOAD 0x2 = RELOAD_CONT 0x3 = RELOAD_RELOAD 0x4 = CONT_LLP 0x5 = RELOAD_LLP 0x6 = LLP_CONT 0x7 = LLP_RELOAD 0x8 = LLP_LLP

REG_DMA_COMP_PARAMS_1_L

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3F0h

• Read/write access: R

DMA component parameters register 1 low, contains component identification information

Bit	Symbol	Access	INI	Description
31:24	CH3_MAX_BLK_SIZE	R	0x10	The value of this register is derived from the DMAC_CH3_MAX_BLK_SIZE from config_form.vh CH3_MAX_BLK_SIZE = log2(DMAC_CH3_MAX_BLK_SIZE) + 1
23:16	CH2_MAX_BLK_SIZE	R	0x10	The value of this register is derived from the DMAC_CH2_MAX_BLK_SIZE from config_form.vh CH2_MAX_BLK_SIZE = log2(DMAC_CH2_MAX_BLK_SIZE) + 1
15:8	CH1_MAX_BLK_SIZE	R	0x10	The value of this register is derived from the DMAC_CH1_MAX_BLK_SIZE from config_form.vh CH1_MAX_BLK_SIZE = log2(DMAC_CH1_MAX_BLK_SIZE) + 1
7:0	CH0_MAX_BLK_SIZE	R	0x10	The value of this register is derived from the DMAC_CH0_MAX_BLK_SIZE from config_form.vh CH0_MAX_BLK_SIZE = log2(DMAC_CH0_MAX_BLK_SIZE) + 1

REG_DMA_COMP_PARAMS_1_H

• Name: Refer to the bit table in the description for it

• Size: 32

• Address offset: 3F4h

• Read/write access: R

DMA component parameters register 1 high, contains component identification information

Bit	Symbol	Access	INI	Description
31	HIGH_BIT_NUM_HS_INT3	R	0x0	Number of hardware handshake interfaces. If it is 128, this bit read value is 1.
30	HIGH_BIT_NUM_HS_INT2	R	0x0	Number of hardware handshake interfaces. If it is greater than 63 and less than 128, this bit read value is 1.
29	HIGH_BIT_NUM_HS_INT1	R	0x0	Number of hardware handshake interfaces. If it is greater than 31 and less than 64, this bit read value is 1.
28	STATIC_ENDIAN_SELECT	R	0	The value of this register is derived from the DMAC_STATIC_ENDIAN_SELECT parameter. 0 = FALSE (dynamic endian fixed) 1 = TRUE (not supported)
27	ADD_ENCODED_PARAMS	R	1	The value of this register is derived from the DMAC_ADD_ENCODED_PARAMS parameter. 0 = FALSE 1 = TRUE
26:22	NUM_HS_INT	R	0x1E	Number of hardware handshake interfaces. The value of this register is derived from the DMAC_NUM_HS_INT parameter. NUM_HAS_INT = DMAC_NUM_HS_INT[4:0] 0x00 = 0 … 0x10 = 16
21:18	RSVD	R	-	Reserved
17:16	M2_DATA_WIDTH	R	0x0	AXI Master2 data width. The value of this register is derived from the DMAC_M2_DATA_WIDTH parameter. Master2 data width should be equal to that of Master 1. M2_DATA_WIDTH = log2(DMAC_DATA_WIDTH/32) 0x0 = 32 bits 0x1 = 64 bits 0x2 = 128 bits 0x3 = Reserved
15:14	M1_DATA_WIDTH	R	0x0	AXI Master1 data width. The value of this register is derived from the DMAC_M1_DATA_WIDTH parameter. Master1 data width should be equal to that of Master 2. M1_DATA_WIDTH = log2(DMAC_DATA_WIDTH/32) 0x0 = 32 bits 0x1 = 64 bits 0x2 = 128 bits 0x3 = Reserved
13:12	S_DATA_WIDTH	R	0x0	APB slave interface data width.The value of this register is derived from the DMAC_S_DATA_WIDTH parameter. The width is fixed to 32 bits for now. S_DATA_WIDTH = log2(DMAC_DATA_WIDTH/32) 0x0 = 32 bits 0x1 = Reserved 0x2 = Reserved 0x3 = Reserved
11:10	NUM_MASTER_INT	R	0x1	Number of master interface. The value of this register is derived from the DMAC_NUM_MASTER_INT parameter. This value is fixed to 1 (only 2 AXI masters supported now.) 0x0 = Reserved 0x1 = 2 0x2 = Reserved 0x3 = Reserved
9:6	NUM_CHANNELS	R	0x7	Number of channels. The value of this register is derived from the DMAC_NUM_CHASNNELS parameter. NUM_CHANNELS = DMAC_NUM_CHASNNELS -1 0x0 = 1 … 0xf = 16
5:2	RSVD	R	-	Reserved
1:0	INTR_IO	R	0x0	Interrupt output format.The value of this register is derived from the DMAC_INTR_IO parameter. 0x0 = ALL 0x1 = TYPE 0x2 = COMBINED 0x3 = reserved

REG_DMA_COMPONENT_ID_REGS_L

• Name: DMAC ID

• Size: 32

• Address offset: 3F8h

• Read/write access: R

DMA component ID register low, identifies the DMA controller release date

Bit	Symbol	Access	INI	Description
31:0	DMA_COMPONENT_ID	R	32'h22101416	DMAC ID (release_date_. Configure it in config form.

REG_DMA_COMPONENT_ID_REGS_H

• Name: It is obtained from the high 32 bits from git logs in git server.

• Size: 32

• Address offset: 3FCh

• Read/write access: R

DMA component ID register high, identifies the DMA controller rtl version

Bit	Symbol	Access	INI	Description
31:0	RTL_GIT_VER	R	32'h00201028	It is obtained from the high 32 bits from git logs in git server.