调试定时器
简介
调试定时器是一个高精度回绕定时器,该定时器在芯片上电完成之后便会自动启动,开始持续计时,能够为片上所有处理器提供统一的高精度时间基准,保障多核场景下的时间同步性。除此之外,该调试定时器还额外搭载了一个软件触发的计数器,专门用于解决多核之间的竞争问题,辅助排查多核运行时的时序冲突、资源抢占等调试难题,是芯片多核调试、时序校准的关键组件。
特性
高精度
{{IC_PARAM_DEBUG_TIMER_WIDTH}}回绕定时器1 μs 计时精度,计数器计数值每递增 1,对应计时时长为 1 微秒
上电后自动启动,无需软件配置使能
一个软件触发计数器
高精度
{{IC_PARAM_DEBUG_TIMER_WIDTH}}回绕定时器1 μs 计时精度,计数器计数值每递增 1,对应计时时长为 1 微秒
上电后自动启动,无需软件配置使能
一个软件触发计数器
高精度
{{IC_PARAM_DEBUG_TIMER_WIDTH}}回绕定时器1 μs 计时精度,计数器计数值每递增 1,对应计时时长为 1 微秒
上电后自动启动,无需软件配置使能
一个软件触发计数器
高精度
{{IC_PARAM_DEBUG_TIMER_WIDTH}}回绕定时器1 μs 计时精度,计数器计数值每递增 1,对应计时时长为 1 微秒
上电后自动启动,无需软件配置使能
一个软件触发计数器
高精度
{{IC_PARAM_DEBUG_TIMER_WIDTH}}回绕定时器1 μs 计时精度,计数器计数值每递增 1,对应计时时长为 1 微秒
上电后自动启动,无需软件配置使能
一个软件触发计数器
高精度
{{IC_PARAM_DEBUG_TIMER_WIDTH}}回绕定时器1 μs 计时精度,计数器计数值每递增 1,对应计时时长为 1 微秒
上电后自动启动,无需软件配置使能
一个软件触发计数器
高精度
{{IC_PARAM_DEBUG_TIMER_WIDTH}}回绕定时器1 μs 计时精度,计数器计数值每递增 1,对应计时时长为 1 微秒
上电后自动启动,无需软件配置使能
一个软件触发计数器
高精度
{{IC_PARAM_DEBUG_TIMER_WIDTH}}回绕定时器1 μs 计时精度,计数器计数值每递增 1,对应计时时长为 1 微秒
上电后自动启动,无需软件配置使能
一个软件触发计数器
功能描述
该高精度回绕定时器支持两种时钟输入源:外部晶振(XTAL)或芯片内部 32K 时钟,两种时钟源可根据系统运行状态智能切换。当系统正常运行时,可依托高精度晶振保障计时精准度;当系统进入睡眠模式时,定时器会自动切换时钟源。无论使用何种时钟源,该计数器均每 1 μs 自动加 1。
当高精度回绕定时器的计数值达到其支持的最大位宽上限时,会自动回绕至 0,重新开始新一轮计数,实现循环计时的效果,无需手动复位。需要注意的是,系统在进入、退出睡眠模式的过程中,时钟源切换操作会对计时操作造成一定的时间误差,因此在实际使用该定时器时,若涉及睡眠模式的切换场景,必须提前考虑该误差带来的影响。
高精度回绕定时器还支持配置功能,软件可以根据需要配置计数起始值,配置后该计数器将从配置的起始值开始递增计数。
软件触发计数器主要用于调试多核 SoC 芯片中的各类时序问题,精准定位多核运行时的时序偏差、资源仲裁异常等故障,通过软件触发的方式,在总线级别实现了高效的仲裁管控,优化多核竞争调度逻辑。
该计数器设有两个独立的读取窗口,不同的读取地址对应不同的计数规则:如果从 DBGT_ATOM_INC 地址进行读取操作,软件触发计数器的数值会自动加一;如果从 DBGT_ATOM 地址进行读取操作,计数器数值保持不变,不会发生递增,可通过区分读取地址,灵活控制计数触发逻辑,适配不同的多核调试场景。
寄存器
Base Address: 0x41015000
Name |
Address offset |
Access |
Description |
|---|---|---|---|
000h |
R/W |
This register contains the configuration of debug timer's clock and enable signal. |
|
004h |
R/W |
||
008h |
R |
Atom count adds 1. |
|
00Ch |
R/W |
||
010h |
R/W |
This register is user-defined. |
|
014h |
R/W |
REG_DBGT_CTRL
Name: Debug Timer control register
Size: 32
Address offset: 000h
Read/write access: R/W
This register contains the configuration of debug timer's clock and enable signal.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
- |
Reserved |
0 |
ENABLE |
R/W |
1h |
Debug timer enable.
|
REG_DBGT_CRV
Name: Debug Timer count register
Size: 32
Address offset: 004h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_CRV |
R/W |
0h |
Continue to count from 0 once it's reached 32'hFFFFFFFF. |
REG_DBGT_ATOM_INC
Name: Debug Timer atom read increase register
Size: 32
Address offset: 008h
Read/write access: R
Atom count adds 1.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_ATOM_INC |
R |
0h |
Each read will increase 1 and return to the increased value to bus. |
REG_DBGT_ATOM
Name: Debug Timer atom register
Size: 32
Address offset: 00Ch
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_ATOM |
R/W |
0h |
Return the last increased value of atom counter. |
REG_DBGT_SCRATCH
Name: Debug Timer scratch register
Size: 32
Address offset: 010h
Read/write access: R/W
This register is user-defined.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_SCRATCH |
R/W |
0h |
Reserved |
REG_DBGTIM_DUMMY
Name: Debug Timer Dummy Register
Size: 32
Address offset: 014h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DUMMY |
R/W |
ffffh |
Dummy register |
Base Address: 0x4011E000
Name |
Address offset |
Access |
Description |
|---|---|---|---|
000h |
R/W |
This register contains the configuration of debugtimer's clock and enable signal. |
|
004h |
R/W |
Timestamp count |
|
008h |
R |
Atom count adds 1. |
|
00Ch |
R/W |
Atom count value |
|
010h |
R/W |
User-defined register |
|
014h |
R/W |
REG_DBGT_CTRL
Name: debugtimer control register
Size: 32
Address offset: 000h
Read/write access: R/W
This register contains the configuration of debugtimer's clock and enable signal.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
- |
Reserved |
15:4 |
DIV |
R/W |
28h |
The default value can used to divide 40M XTAL to 1M |
3:1 |
CLKSEL |
R/W |
0h |
Clock source selection
|
0 |
ENABLE |
R/W |
1h |
Debug timer enable
|
REG_DBGT_CRV
Name: debugtimer count register
Size: 32
Address offset: 004h
Read/write access: R/W
Timestamp count
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_CRV |
R/W |
0h |
Continue to count from 0 once it's reached 32'hFFFFFFFF |
REG_DBGT_ATOM_INC
Name: debugtimer atom read increase register
Size: 32
Address offset: 008h
Read/write access: R
Atom count adds 1.
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_ATOM_INC |
R |
0h |
Each read will increase 1 and return to the increased value to bus. |
REG_DBGT_ATOM
Name: debugtimer atom register
Size: 32
Address offset: 00Ch
Read/write access: R/W
Atom count value
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_ATOM |
R/W |
0h |
Return the last increased value of atom counter |
REG_DBGT_SCRATCH
Name: debugtimer scratch register
Size: 32
Address offset: 010h
Read/write access: R/W
User-defined register
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_SCRATCH |
R/W |
0h |
Reserved for users |
REG_DBGTIM_DUMMY
Name: Debug Timer Dummy Register
Size: 32
Address offset: 014h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DUMMY |
R/W |
ffffh |
Dummy register |
REGISTER_CONTENTS=RTL8720E
REGISTER_CONTENTS=RTL8720E
REGISTER_CONTENTS=RTL8720E
Base Address: 0x42009000
Name |
Address offset |
Access |
Description |
|---|---|---|---|
000h |
R/W |
||
004h |
R/W |
||
008h |
R |
||
00Ch |
R/W |
||
010h |
R/W |
REG_DBGT_CTRL
Name: debugtimer control register
Size: 32
Address offset: 000h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
- |
Reserved |
15:4 |
DIV |
R/W |
28h |
The default value can used to divide 40M Xtal to 1M |
3:1 |
CLKSEL |
R/W |
0h |
Clock source select
|
0 |
ENABLE |
R/W |
1h |
Debug timer enable.
|
REG_DBGT_CRV
Name: debugtimer count register
Size: 32
Address offset: 004h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_CRV |
R/W |
0h |
Continuing to count from 0 once it's reached 32'hFFFFFFFF |
REG_DBGT_ATOM_INC
Name: debugtimer atom read increase
Size: 32
Address offset: 008h
Read/write access: R
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_ATOM_INC |
R |
0h |
Each read will increase 1 and return to the increased value to bus. |
REG_DBGT_ATOM
Name: debugtimer atom
Size: 32
Address offset: 00Ch
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_ATOM |
R/W |
0h |
Return the last increased value of atom counter |
REG_DBGT_SCRATCH
Name: debugtimer scratch
Size: 32
Address offset: 010h
Read/write access: R/W
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_SCRATCH |
R/W |
0h |
Reserved for user use |
Base Address: 0x40817000
Name |
Address offset |
Access |
Description |
|---|---|---|---|
000h |
R/W |
This register contains the configuration of debugtimer's clock and enable signal |
|
004h |
R/W |
Timestamp count |
|
008h |
R/W |
Timestamp count |
|
00Ch |
R |
Atom count add 1 |
|
010h |
R/W |
Atom count value |
|
014h |
R/W |
User defined register |
|
018h |
R/W |
Dummy register |
REG_DBGT_CTRL
Name: debugtimer control register
Size: 32
Address offset: 000h
Read/write access: R/W
This register contains the configuration of debugtimer's clock and enable signal
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:2 |
RSVD |
R |
- |
Reserved |
1 |
DBGT_CRV_SET |
R/W |
0h |
Set dbgt_crv0/1 to dbgtcnt |
0 |
ENABLE |
R/W |
1h |
Debug timer enable.
|
REG_DBGT_CRV0
Name: debugtimer count register
Size: 32
Address offset: 004h
Read/write access: R/W
Timestamp count
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_CRV0 |
R/W |
0h |
Dbgtcnt[31:0].Continuing to count from 0 once it's reached 32'Hffffffff |
REG_DBGT_CRV1
Name: debugtimer count register
Size: 32
Address offset: 008h
Read/write access: R/W
Timestamp count
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_CRV1 |
R/W |
0h |
Dbgtcnt[63:32].Continuing to count from 0 once it's reached 32'hFFFFFFFF |
REG_DBGT_ATOM_INC
Name: debugtimer atom read increase
Size: 32
Address offset: 00Ch
Read/write access: R
Atom count add 1
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_ATOM_INC |
R |
0h |
Each read will increase 1 and return to the increased value to bus. |
REG_DBGT_ATOM
Name: debugtimer atom
Size: 32
Address offset: 010h
Read/write access: R/W
Atom count value
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_ATOM |
R/W |
0h |
Return the last increased value of atom counter |
REG_DBGT_SCRATCH
Name: debugtimer scratch
Size: 32
Address offset: 014h
Read/write access: R/W
User defined register
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_SCRATCH |
R/W |
0h |
Reserved for user use |
REG_DBGTIM_DUMMY
Name: Debug TimerDummy Register
Size: 32
Address offset: 018h
Read/write access: R/W
Dummy register
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DUMMY |
R/W |
ffffh |
Dummy register |
Base Address: 0x40806000
Name |
Address offset |
Access |
Description |
|---|---|---|---|
000h |
R/W |
This register contains the configuration of debugtimer's clock and enable signal |
|
004h |
R/W |
Timestamp count |
|
008h |
R/W |
Timestamp count |
|
00Ch |
R |
Atom count add 1 |
|
010h |
R/W |
Atom count value |
|
014h |
R/W |
User defined register |
|
018h |
R/W |
Dummy register |
REG_DBGT_CTRL
Name: debugtimer control register
Size: 32
Address offset: 000h
Read/write access: R/W
This register contains the configuration of debugtimer's clock and enable signal
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:2 |
RSVD |
R |
- |
Reserved |
1 |
DBGT_CRV_SET |
R/W |
0h |
Set dbgt_crv0/1 to dbgtcnt |
0 |
ENABLE |
R/W |
1h |
Debug timer enable.
|
REG_DBGT_CRV0
Name: debugtimer count register
Size: 32
Address offset: 004h
Read/write access: R/W
Timestamp count
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_CRV0 |
R/W |
0h |
Dbgtcnt[31:0].Continuing to count from 0 once it's reached 32'Hffffffff |
REG_DBGT_CRV1
Name: debugtimer count register
Size: 32
Address offset: 008h
Read/write access: R/W
Timestamp count
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_CRV1 |
R/W |
0h |
Dbgtcnt[63:32].Continuing to count from 0 once it's reached 32'hFFFFFFFF |
REG_DBGT_ATOM_INC
Name: debugtimer atom read increase
Size: 32
Address offset: 00Ch
Read/write access: R
Atom count add 1
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_ATOM_INC |
R |
0h |
Each read will increase 1 and return to the increased value to bus. |
REG_DBGT_ATOM
Name: debugtimer atom
Size: 32
Address offset: 010h
Read/write access: R/W
Atom count value
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_ATOM |
R/W |
0h |
Return the last increased value of atom counter |
REG_DBGT_SCRATCH
Name: debugtimer scratch
Size: 32
Address offset: 014h
Read/write access: R/W
User defined register
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DBGT_SCRATCH |
R/W |
0h |
Reserved for user use |
REG_DBGTIM_DUMMY
Name: Debug TimerDummy Register
Size: 32
Address offset: 018h
Read/write access: R/W
Dummy register
Bit |
Symbol |
Access |
INI |
Description |
|---|---|---|---|---|
31:0 |
DUMMY |
R/W |
ffffh |
Dummy register |