Inter-Processor Communication

Introduction

There are multiple processors integrated into the chip. The Inter-Processor Communication (IPC) hardware establishes dedicated communication channels between every two processors.

The IPC provides a set of registers for each processor and realizes inter-processor communication via interrupts. Additionally, interrupts can be independently masked by each processor to support polled-mode operation.

The IPC communication data must be located in a common memory, which is not part of the IPC block.

Features

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• {{IC_PARAM_IPC_CH}} TRx channels between every two processors

• Independent trx channels

• Channel-independent interrupt control

• Support Rx channel full interrupt

• Support Tx channel empty interrupt

• Shared memory

Block Diagram

The IPC provides simple communication between every two processors. It can use shared SRAM to transmit information to other CPU(s). The system block diagram of IPC is shown in the following figure.

The IPC submodule structure of each processor is the same. The following figure summarizes the submodule’s structure of IPC_CPUm.

Between every two processors, one processor has 2 sets of communication channels, 1 set for transmitting data (Tx) to the other processor by writing Tx Data Register, and the other set for receiving data (Rx) from the other processor by checking Rx Data Register.

In addition to data registers, there are also interrupt-related registers:

• Interrupt Status Register (ISR) is used to present current channel Tx empty or Rx full status change.

• Interrupt Mask Register (IMR) is used to enable interrupts for Tx empty or Rx full.

• Interrupt Clear Register (ICR) is used to clear the corresponding interrupt status.

The following figure demonstrates message transmission from CPUn to CPUm.

Functional Description

Message Transmit

Between every two processors, one processor has 2 sets of channels to communicate with the other processor. Channel index of Tx channels and the corresponding Rx channels are one-to-one mapping.

IPC message transmitting mapping shows the IPC transmit mapping from CPUn to CPUm, and IPC message receiving mapping shows the IPC mapping from CPUm to CPUn after receiving data.

IPC message transmitting mapping

IPC message receiving mapping

• REG_TX_DATA of CPUn is used by CPUn to transmit data to CPUm, once 1 is written to the channel x (x could be 0 ~ M, where M means max channel index), the corresponding bit in REG_RX_DATA of CPUm will be set. The Rx full bit of channel x in REG_ISR of CPUm will be set at the same time.

• Writing 1 to channel x in REG_ISR of CPUm clears the Rx full interrupt of channel x, the corresponding channel x Tx empty interrupt bit in REG_ISR of CPUn will be set automatically.

IPC without Handshake

As there are Rx full and Tx empty interrupts for each processor, these functions can be used to realize message transmission and handshake.

IPC message transmission flow without handshake shows the interrupt messaging protocol of IPC without waiting for a handshake from receiver, and steps are summarized in IPC message transmission steps without handshake. It takes the message transmission from CPUn to CPUm for example.

IPC message transmission flow without handshake

IPC message transmission steps without handshake

Step	Description
1	Check the Tx data status of the channel 0 in CPUn IPC Tx Data Register
2	CPUn writes data to the Common Memory
3	Write 1 to idle channel 0 in IPC Tx Data Register
4	The CPUn IPC Tx Data Register write operation Map to CPUm IPC Rx Data Register Clear the Tx empty interrupt bit in the CPUn Interrupt Status Register Set the Rx full interrupt bit in the CPUm Interrupt Status Register
5	If the Rx full interrupt mask is enabled in CPUm Interrupt Mask Register, a Rx full interrupt request will be generated to CPUm.
6	After checking Rx full channel, CPUm performs a data read from the corresponding Common Memory
7	After finishing the interrupt handler, CPUm writes 1 to CPUm Interrupt Status Register to clear the Rx full interrupt
8	The CPUm Interrupt Status Register write operation Clear the Rx full interrupt status bit in the CPUm Status Register Set Tx empty interrupt status bit in the CPUn Status Register
9	Clear the channel 0 bit in CPUm IPC Rx Data Register and CPUn IPC Tx Data Register automatically

IPC with Handshake

IPC message transmission flow with handshake shows the interrupt messaging protocol of IPC with waiting for a handshake from receiver, and steps are summarized in IPC message transmission steps with handshake. It takes the message transmission from CPUn to CPUm for example.

IPC message transmission flow with handshake

IPC message transmission steps with handshake

Step	Description
1	Check the Tx data status of the channel 0 in CPUn IPC Tx Data Register
2	CPUn writes data to the Common Memory
3	Write 1 to idle channel 0 in IPC Tx Data Register.
4	The CPUn IPC Tx Data Register write operation Map to CPUm IPC Rx Data Register Set the Rx full interrupt bit in the CPUm Interrupt Status Register
5	If the Rx full interrupt mask is enabled in CPUm Interrupt Mask Register, a Rx full interrupt request will be generated to CPUm.
6	After checking Rx full channel, CPUm performs a data read from the corresponding Common Memory
7	After finishing the interrupt handler, CPUm write 1 to CPUm Interrupt Status Register to clear the Rx full interrupt
8	The IPC Interrupt Status Register write operation Clear the Rx full interrupt status bit in the CPUm Status Register Set Tx empty interrupt status bit in the CPUn Status Register
9	Clear the channel 0 bit in CPUm IPC Rx Data Register and CPUn IPC Tx Data Register automatically
10	If Tx empty mask is enabled in CPUn Interrupt Mask Register, the setting of the Tx empty bit in the CPUn Status Register generates a Tx Empty interrupt to CPUn
11	CPUn writes 1 to CPUn Interrupt Status Register to clear the Tx empty interrupt

Hardware Semaphore

Overview

The hardware semaphore is used for a mutual exclusion mechanism. It can be accessed by the cores in an atomic operation.

Traditionally, the software takes three steps to use the semaphore: read -> write -> read.

1. The first read operation of the CPU is to poll the current semaphore to check whether it is occupied or not.

2. If this semaphore is free, the CPU will compete it by writing.

3. The last read operation is to check whether the CPU has already occupied this semaphore because maybe several CPUs or threads write to compete the same semaphore.

The above flow executed by software is offloaded to hardware. The following figure illustrates the hardware semaphore mechanism.

• The address mapping is responsible for mapping the N bit semaphore status to N x 4 address space, where N represents the total number of hardware semaphore.

• The read set logic is responsible for determining the status of the semaphore to be read after receiving the read request. If the corresponding semaphore register is 0, the read set logic will set the semaphore register first, then return 0 to the read request.

• The write clear logic is responsible for clearing the status of the semaphore to 0 after receiving write request.

• The semaphore register has N bits, and each bit in the register represents a semaphore. This register can be read directly, or read/written through the address mapped register.

  • If the semaphore register is read through the address mapped register, the status of only one bit can be read at a time, and this bit will be set synchronously when it is 0.

  • If the semaphore register is read directly, the read does not change the status of the semaphore, and all the N bits can be read at a time.

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N equals {{IC_PARAM_IPC_SEMA}}.

Address Mapping

If the bit[0] of the semaphore register can be acquired and released through the base address of address mapping, the bit[1] can be acquired and released through (base address + 4) accordingly. Thus the address of the entire access window ranges from 0 to ( N x 4 - 1), where N is the total number of hardware semaphore.

Acquire Flow

If the software wants to require the semaphore 0, it can directly read the base address of the access window register.

• If the bit is 0 when the hardware receives the read request, the hardware will set this bit and return 0 synchronously. At this time, the acquire flow will be regarded as successful by software.

• If the bit is 1 when the hardware receives the read request, the hardware will directly return 1. At this time, the acquire flow will be regarded as failed by software.

Release Flow

If the software wants to release the semaphore 0, it can directly write the base address of the access window register. The hardware will clear this bit after receiving the write command.

Inquire Flow

If the software wants to inquire the semaphore status, it can directly read the semaphore registers (without address mapping). This operation only returns the semaphore status, but does not change it.

Registers

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Base Address:

• IPC0_REG : 0x41014000

• IPC1_REG : 0x41014080

Name	Address offset	Access	Description
REG_IPC_DATA	000h	R/W	Take NP's IPC as an example to describe the function of IPC's internal registers. The REG_TX_DATA is used to transmit message from NP to AP. (The logic cannot be generated automatically.)
REG_IPC_ISR	004h	R/W	This register is used to record Tx empty.
REG_IPC_IMR	008h	R/W
REG_IPC_ICR	00Ch	R/W	This register can ensure that the software can manually clear the Tx register in an emergency.
REG_IPC_SEM_0	010h	R
REG_IPC_SEM_1	014h	R
REG_IPC_DUMMY	018h	R/W

REG_IPC_DATA

• Name: Tx_Rx Register

• Size: 32

• Address offset: 000h

• Read/write access: R/W

Take NP's IPC as an example to describe the function of IPC's internal registers. The REG_TX_DATA is

used to transmit message from NP to AP. (The logic cannot be generated automatically.)

Bit	Symbol	Access	INI	Description
31:16	TX0_DATA	R/W	0x0	After preparing descriptor, data and corresponding memory. 1: Writing 1 to the Tx data register (tx0_data) channel x bit, and the data will be mapped to the CPU0's RX data register (rx0_data) channel x bit. And the corresponding Rx full status bit in REG_ISR_CPU0 will be set. 0: Writing 0 has no effect. If the corresponding Rx full status bit in REG_ISR_CPU0 (e.g. isr_rx0_full_status6) is cleared, the corresponding bit in tx0_data will be cleaned automatically.
15:0	RX0_DATA	R	0x0	Rx data automatically maps data from tx0_data of CPU0

REG_IPC_ISR

• Name: Interrupt Empty Full Status Register

• Size: 32

• Address offset: 004h

• Read/write access: R/W

This register is used to record Tx empty.

Bit	Symbol	Access	INI	Description
31	ISR_TX0_EMPTY_STATUS15	R/W	0x0	Refer to the description of isr_tx0_empty_status0
30	ISR_TX0_EMPTY_STATUS14	R/W	0x0	Refer to the description of isr_tx0_empty_status0
29	ISR_TX0_EMPTY_STATUS13	R/W	0x0	Refer to the description of isr_tx0_empty_status0
28	ISR_TX0_EMPTY_STATUS12	R/W	0x0	Refer to the description of isr_tx0_empty_status0
27	ISR_TX0_EMPTY_STATUS11	R/W	0x0	Refer to the description of isr_tx0_empty_status0
26	ISR_TX0_EMPTY_STATUS10	R/W	0x0	Refer to the description of isr_tx0_empty_status0
25	ISR_TX0_EMPTY_STATUS9	R/W	0x0	Refer to the description of isr_tx0_empty_status0
24	ISR_TX0_EMPTY_STATUS8	R/W	0x0	Refer to the description of isr_tx0_empty_status0
23	ISR_TX0_EMPTY_STATUS7	R/W	0x0	Refer to the description of isr_tx0_empty_status0
22	ISR_TX0_EMPTY_STATUS6	R/W	0x0	Refer to the description of isr_tx0_empty_status0
21	ISR_TX0_EMPTY_STATUS5	R/W	0x0	Refer to the description of isr_tx0_empty_status0
20	ISR_TX0_EMPTY_STATUS4	R/W	0x0	Refer to the description of isr_tx0_empty_status0
19	ISR_TX0_EMPTY_STATUS3	R/W	0x0	Refer to the description of isr_tx0_empty_status0
18	ISR_TX0_EMPTY_STATUS2	R/W	0x0	Refer to the description of isr_tx0_empty_status0
17	ISR_TX0_EMPTY_STATUS1	R/W	0x0	Refer to the description of isr_tx0_empty_status0
16	ISR_TX0_EMPTY_STATUS0	R/W	0x0	Tx channel 0 empty interrupt status of CPU1 transmit to CPU0. If the corresponding Rx full status bit in REG_ISR_CPU0 (e.g. isr_rx0_full_status0) is cleared, the corresponding Tx empty status bit will be set automatically. It will be cleared by software writing 1.
15	ISR_RX0_FULL_STATUS15	R/W	0x0	Refer to the description of isr_rx0_full_status0
14	ISR_RX0_FULL_STATUS14	R/W	0x0	Refer to the description of isr_rx0_full_status0
13	ISR_RX0_FULL_STATUS13	R/W	0x0	Refer to the description of isr_rx0_full_status0
12	ISR_RX0_FULL_STATUS12	R/W	0x0	Refer to the description of isr_rx0_full_status0
11	ISR_RX0_FULL_STATUS11	R/W	0x0	Refer to the description of isr_rx0_full_status0
10	ISR_RX0_FULL_STATUS10	R/W	0x0	Refer to the description of isr_rx0_full_status0
9	ISR_RX0_FULL_STATUS9	R/W	0x0	Refer to the description of isr_rx0_full_status0
8	ISR_RX0_FULL_STATUS8	R/W	0x0	Refer to the description of isr_rx0_full_status0
7	ISR_RX0_FULL_STATUS7	R/W	0x0	Refer to the description of isr_rx0_full_status0
6	ISR_RX0_FULL_STATUS6	R/W	0x0	Refer to the description of isr_rx0_full_status0
5	ISR_RX0_FULL_STATUS5	R/W	0x0	Refer to the description of isr_rx0_full_status0
4	ISR_RX0_FULL_STATUS4	R/W	0x0	Refer to the description of isr_rx0_full_status0
3	ISR_RX0_FULL_STATUS3	R/W	0x0	Refer to the description of isr_rx0_full_status0
2	ISR_RX0_FULL_STATUS2	R/W	0x0	Refer to the description of isr_rx0_full_status0
1	ISR_RX0_FULL_STATUS1	R/W	0x0	Refer to the description of isr_rx0_full_status0
0	ISR_RX0_FULL_STATUS0	R/W	0x0	Rx channel 0 full interrupt status of CPU1. The corresponding Rx full status bit will be set by CPU0's Tx data register (tx0_data) channel 0. It will be cleared by software writing 1.

REG_IPC_IMR

• Name: Interrupt Empty Full Mask Register

• Size: 32

• Address offset: 008h

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31:16	IMR_TX0_EMPTY_MASK	R/W	0x0	0: Mask Tx Channel x empty interrupt of CPU1 transmit to CPU0 1: Unmask Tx Channel x empty interrupt of CPU1 transmit to CPU0
15:0	IMR_RX0_FULL_MASK	R/W	0x0	0: Mask Rx Channel x full interrupt of CPU1 received from CPU0 1: Unmask Rx Channel x full interrupt of CPU1 received from CPU0

REG_IPC_ICR

• Name: Clear Tx Register

• Size: 32

• Address offset: 00Ch

• Read/write access: R/W

This register can ensure that the software can manually clear the Tx register in an emergency.

Bit	Symbol	Access	INI	Description
31	ICR_TX0_DATA_CLEAR15	R/W	0x0	Refer to the description of icr_tx0_data_clear0
30	ICR_TX0_DATA_CLEAR14	R/W	0x0	Refer to the description of icr_tx0_data_clear0
29	ICR_TX0_DATA_CLEAR13	R/W	0x0	Refer to the description of icr_tx0_data_clear0
28	ICR_TX0_DATA_CLEAR12	R/W	0x0	Refer to the description of icr_tx0_data_clear0
27	ICR_TX0_DATA_CLEAR11	R/W	0x0	Refer to the description of icr_tx0_data_clear0
26	ICR_TX0_DATA_CLEAR10	R/W	0x0	Refer to the description of icr_tx0_data_clear0
25	ICR_TX0_DATA_CLEAR9	R/W	0x0	Refer to the description of icr_tx0_data_clear0
24	ICR_TX0_DATA_CLEAR8	R/W	0x0	Refer to the description of icr_tx0_data_clear0
23	ICR_TX0_DATA_CLEAR7	R/W	0x0	Refer to the description of icr_tx0_data_clear0
22	ICR_TX0_DATA_CLEAR6	R/W	0x0	Refer to the description of icr_tx0_data_clear0
21	ICR_TX0_DATA_CLEAR5	R/W	0x0	Refer to the description of icr_tx0_data_clear0
20	ICR_TX0_DATA_CLEAR4	R/W	0x0	Refer to the description of icr_tx0_data_clear0
19	ICR_TX0_DATA_CLEAR3	R/W	0x0	Refer to the description of icr_tx0_data_clear0
18	ICR_TX0_DATA_CLEAR2	R/W	0x0	Refer to the description of icr_tx0_data_clear0
17	ICR_TX0_DATA_CLEAR1	R/W	0x0	Refer to the description of icr_tx0_data_clear0
16	ICR_TX0_DATA_CLEAR0	R/W	0x0	0: Writing 0 has no effect. 1: Clear the Tx data register (tx0_data) channel 0 bit.
15:0	RSVD0	R/W	0x0

REG_IPC_SEM_0

• Size: 32

• Address offset: 010h

• Read/write access: R

Bit	Symbol	Access	INI	Description
31:0	SEM_0_DATA	R	0x0	It is used to indicate whether this semaphore is occupied. 0: Not occupied; 1: Occupied.

REG_IPC_SEM_1

• Size: 32

• Address offset: 014h

• Read/write access: R

Bit	Symbol	Access	INI	Description
31:0	SEM_1_DATA	R	0x0	It is used to indicate whether this semaphore is occupied. 0: Not occupied; 1: Occupied.

REG_IPC_DUMMY

• Name: Dummy Register

• Size: 32

• Address offset: 018h

• Read/write access: R/W

Bit	Symbol	Access	INI	Description
31:16	RSVD	R	-	Reserved
15:0	DUMMY	R/W	0x0	Dummy register