System Memory

Introduction

System memory shared with BT, wlmac and iqdump.

Features

TBD

Block Diagram

TBD

Design Implementation

sram0: wrap_hram0_sys

memory size: 64KB*8

memory data width = 64bit

system/iqdump access data width = 64bit

base address: 0x2000_0000

Address	Control register	Description	Clock domain
0x2000_0000~0x2006_FFFF	Only use as system memory	Only use as system memory	clk_sram: 200MHz
0x2006_0000~0x2007_FFFF	r_iqdata_dump: 0x4000_07C0[1]	1: Share to wifi iq data dump for debug	clk_sram clk_iqdump

sram2: wrap_hram_shr

BT memory size: DMEM: 56KB; BF MEM: 64KB

DMEM data width = 32bit; BF MEM data width = 64bit

system access memory data width: 32bit

base address: 0x2008_0000

r_HSYS_SHARE_BT_MEM = 1 : BT memory share to system sram2; 4100_8230[19]

system memory clk: clk_sram, 200MHz

wifi memory: clk_wlmac, 40MHz

wrap_lram_ret

Retention memory: 512byte

Address: 0x4100_8E00~0x4100_8FFF, access by ls_syson

clk_lpon: 4MHz

HW bug

sram2 share to system read data error

Corner case

When bt memory stop share to system, system read enable signal bt_rd_en will be latch to 1.

When wifi memory share to system, system read data sram_dout will be infect.

Workaround

System read sram2 RSVD address before r_HSYS_SHARE_WL_MEM = 0, clear read enable signal bt_rd_en = 0.

Register

TBD

Operation Flow

TBD