Power-on Latch

This chapter aims to describe the terms of power-on latch. Power-on latch means reading some GPIOs’ status on the very beginning of power-on, and using the latched value to decide boot branch or configure boot settings.

Power-on Latch Pins

There are eight power-on latch pins, classified to five types.

• UART download pin: x1

• IBoot selection pin: x1

• Test mode pin: x1

• OTP bypass pin: x1

• ICFG pin: x4

Power-on Logic

Power on latch 的pin在功能上可以分为高电平有效的和低电平有效的，对于高电平有效的power on latch pin，在pinmux中命名上不添加任何后缀，对于低电平有效的power on latch pin，命名上会添加_DIS后缀。同时power on latch的值会被放到寄存器中，对于高电平有效latch pin，寄存器当中的值反应latch瞬间的电平值，对于低电平有效的latch pin，寄存器的值是latch pin电平的取反。用图标表示如下：

命名	功能	寄存器值
XXX_DIS	低电平有效	Latch的值为pin上电平反逻辑
XXX	高电平有效	Latch的值为pin上电平正逻辑

AmebaDPlus上，对应power on latch逻辑关系如下：

Pin	功能	寄存器
TM_DIS	低电平进入test mode	0x41008228[17] 1: test mode 0: normal mode
OTP_DIS	低电平进入otp bypass mode	0x41008228[16] 1: bypass mode 0: normal mode, success autoload
UD_DIS	低电平进入uart download mode	0x41008228[19] 1: uart download mode 0: normal mode
IBOOT	内部包的是flash或是psram	0x41008228[18] 0: psram 1: flash
ICFG	Test mode code	0x41008228[23:20] 0: normal mode 其余: 各test mode

Power-on Latch Time

Only CHIP_EN reset and POR reset will latch the GPIO’s status, and will keep the autoload value in always on (AON) area. Other exception reset will neither reset the autoload value nor reload it again.

Reset type	CHIP_EN	POR	WDG	SYS_RST	BOR	Deep-sleep
Latch	Yes	Yes	No	No	No	No

Default Status

The pins used for power-on latch may have an initial pull resistor, it can be found in the following table. Also the external pull means how the customer should handle these pins when they design the schematics.

Pins	UART download	Test mode	OTP bypass	ICFG
Internal pull	UP	UP	UP	NA
External pull	UP or NC	UP or NC	NA	NA
PAD power domain	SYSON	AON	AON	SYSON

Note

• NA: no need to pay attention

• NC: no need to connect

• CD: customer decides according to HW

• Users do not need to concern the row of power domain, it is only used for Realtek internal reference

Functional Description

UART Download

The UART download pin is used by software to determine whether traps to UART download mode. Before latching the value, HW will add a pull-up resistor to this pin.

If a high level is trapped from this pin, it means that the software boots normally; otherwise, it means that software will wait for a programming handshake from LOGUART.

For security issues, you may want to turn off the UART download function after PVT, so an otp bit is also involved to control the UART download mode. If the otp is programmed to disable UART download mode, the chip can never enter UART download mode by the trap pin.

UART trap flow

IBoot Selection

IBOOT selection pin用来选择内部包的是flash还是psram, 0 是 psram, 1 是 flash。

IBOOT pin在chip内部会直接bond 到GND 或者是power，为了防止误设成output导致pad烧毁，设计上保证在normal 使用时IBOOT pad是input only。

Test Mode

Test mode is only used for IC testing in Realtek factory, the pin must keep high during boot in the customer’s design. OTP bypass and ICFG are used to select test subsets of testing mode, and they only work when test mode is trapped low. So as far as putting a pull-up resistor on the test mode pin, the OTP bypass and ICFG pins won’t influence the boot flow.

Test Mode

ICFG pad and OTP bypass autoload pad will not have any influence on boot process when the test mode pad is active. Thus, the designer should select the test mode pin carefully.

When test mode latches the inactive status, hardware PMC will bypass OTP autoload according to the status of the OTP bypass pad, and then boot to the selected test mode (depending on ICFG).

Note

Audio pad can be used as power-on latch pin, because it did have power during the initial boot.

OTP Bypass

目前因为OTP bypass仅仅在内部使用，且PAD的power domain需要在AON区域（AON PMC boot时就要确定是否要bypass otp autoload）。受限于AON pin数量较少，放到input pin上会有不良影响。因此我们将Bypass看成一种test mode，仅仅在Test mode为低的时候才可以生效，在normal mode不会进行otp bypass。

Note

In the test mode, KM0 cannot boot up, because the control of LP platform is switched to SIC.