LOGUART

Introduction

BT and Wi-Fi have different mechanism for log print. In chip, there are two UARTs for log print, one UART is for BT and the other is for Wi-Fi. The background is illustrated below.

This specification will design a multi-port UART IP, so that multi-core or multi-function can share the same UART IP/PIN. For example, AP, NP and BT SoC (MCM) can send log concurrently by the same UART IP.

Features

• Five Tx ports for multi-core or multi-function share the same UARTLOG IP/PIN.

• Five Tx ports can send UART data concurrently, hardware arbitration can be used.

• Tx AGG supported, hardware adds AGG header automatically.

• Up to 3Mbps baud rate for fast log printing.

• Use XTAL40MHz and OSC2M as the source clock, can wake up system when clock source is open during sleep mode.

• RX DMA transfer and Tx DMA for Tx PATH2.

Functional Description

In chip, path1 ~ 4 receives logs from AP, NP, BT low stack and BT up stack respectively. Relay path receives BT FW logs from BT SoC 3081.

Block Diagram

The block diagram of LOGUART is shown in the following figure. LOGUART consists of several modules, which provide the following functions:

• log_fifo of path 1 ~ 4

  • Asynchronous FIFO (pclk and clk_xtal domain)

  • 8bit*12

• TAA (Tx AGG and Arbitration) (clk_xtal domain)

  • AGG header includes AGG sync pattern, path number, AGG length and checksum

  • Payload: AGG length+1 indicates payload number of bytes

  • Arbitration: adopt round-robin mechanism to poll the status of each path’s log fifo

• tx_fifo

  • Synchronous FIFO (clk_xtal domain)

  • 8bit*50

• uart_tx (clk_xtal domain)

  • Shift register

  • Generate UART format data

  • Support fractional baud rate

• log_fifo of internal relay path

  • Synchronous FIFO (clk_xtal domain)

  • 11bit*12

• rx_fifo

  • Asynchronous FIFO (sclk and pclk domain)

  • 11bit*16

• uart_rx0 (sclk domain)

  • Receive UART format data

  • Error detection

  • Interrupt control

  • Support fractional baud rate

  • OSC clock for low power

  • Monitor and eliminate Rx baud rate error and own frequency drift

• uart_rx1 (clk_xtal domain)

  • Receive UART format data

  • Error detection

  • Interrupt control

  • Support fractional baud rate

• apb_slv_wrap

  • APB3 bus interface

• regmngs

  • Register control unit

Clock Source

There are two clock sources optional for LOGUART: XTAL40M and OSC2M.

• When XTAL40M is chosen, both Rx and Tx use XTAL40M as clock source.

• When OSC2M is chosen, both Rx and Tx use it as clock source. When OSC2M is used as clock source, Rx monitor function can be enabled.

Tx AGG Format

The Tx AGG format is illustrated in the following figure. If Tx AGG function is enabled, every packet will be send from UART Tx module with AGG header, which is used for trace tool to split multi-path data into different log console.

• AGG header

  • AGG synchronous pattern: start of AGG packet

  • Path number: 1~5

  • AGG length: the length of the payload, number 0~7 represents 1~8 bytes of the payload

  • Checksum: checksum of AGG header

    • Bit[1] is XOR of sync pattern.

    • Bit[0] is XOR of path number and AGG length.

• Payload: log data accessed from log FIFO of each path

AGG header is added automatically by Tx AGG and Arbitration (TAA) module. TAA uses AGG threshold and AGG timeout to select one path and attaches the two-byte AGG header and transfers the packet from log FIFO of each path to tx_fifo. Then packets in tx_fifo are transferred to UART Tx module.

• AGG threshold (AGG_TH): data should be sent from log FIFO to tx_fifo if data number ≥ AGG threshold.

• AGG timeout (AGG_TO): data should be sent from log FIFO to tx_fifo if idle time > AGG timeout, even if there is just only one byte in log FIFO of the path.

Due to the format of AGG header, only 8-bit data format is supported when AGG is enabled. Both 7-bit and 8-bit data format is supported when AGG is disabled.

Arbitration Mechanism

Arbitration Mechanism (AGG_EN =0, default)

If Tx AGG function is disabled by default, log FIFO of all Tx paths will be checked one by one. If one Tx path FIFO is not empty, data from the path will be sent to tx_fifo continuously until LF(0xA) is detected or path FIFO has been empty for long time. The next path will be checked so that every path can have the chance to send their data. The flow chart of the detailed arbitration mechanism is shown in the following figure.

Each Tx path has an independent idle timer. Once one path is being checked and its log FIFO is not empty, idle timer of this path will start from 0 each time 1-byte data is sent from the log FIFO to tx_fifo. If the sent byte is LF(0xA), which means log from the current path has reached line end, the idle timer will be cleared and the next path will be checked subsequently. After all the data has been sent from the current Tx path and no new data comes, it will switch to the next path when idle time reaches AGG_TO.

Note

Idle timer counts based on XTAL40M clock when AGG_EN is 0.

Arbitration Mechanism (AGG_EN =1)

If Tx AGG function is enabled, TAA checks log FIFO of all Tx paths one by one, and sends only one packet or no packet to tx_fifo each time for one Tx path, so that every path can have the chance to send their data. The flow chart of the detailed arbitration mechanism is shown in the following figure.

The idle time of each channel is cleared and counted independently. Idle time of one path starts to counting when TAA switches to this path and confirms that there is at least one-byte log data in the log FIFO but the number of log is below AGG_TH, also the idle time of this path has been cleared in the previous loop. Idle time of one path is cleared before one packet of the path is sent, which means the idle time has reached AGG_TO or the number of log data in log FIFO has reached AGG_TH.

When TAA switches to one path, if the idle time of one path has reached AGG_TO and there are N bytes in its path FIFO at that time, TAA will begin to send log data of this path. However, one corner case is that log data is written into this path FIFO continuously so M bytes (N < M) are in its path FIFO just before TAA attached header and transferred log data into tx_fifo. TAA will send M bytes in this packet if M ≤ 8, or send 8 bytes if M > 8.

When plenty of log data needs to be printed and the left space of tx_fifo is less than 10 bytes, TAA will not transfer log data from any path to tx_fifo until the remaining space of tx_fifo is at least 10 bytes.

It’s recommended to set the baud rate to at least 1.5Mbps, if all 4 channel is enabled.

Note

Idle timer counts based on bit time when AGG_EN is 1.

Relay Path

The relay path is designed for receiving log from another MCM SoC 3081. Although there is no flow control between LOGUART and 3081, relay path FIFO won’t overflow in the worst cases under default configurations.

By default, Tx baud rate of the relay path is 115200bps and the baud rate of LOGUART is 1.5Mbps. One UART frame includes 1 start bit, 8-bit data and 1 stop bit. When 7 bytes are transferred into relay path FIFO and the idle time of relay path has not reached AGG_TO, TAA will switch to path1. In the worst case, when log data from relay path is continuously received into bt_log_fifo2 but TAA needs to send a packet from path 1, 2, 3, 4 before switching to relay path.

Total number of log data from path 1, 2, 3, 4 is (8B+2B)*4 = 40B, which is 320 bits. Total number of UART data is 400 bits including 1 start bit and 1 stop bit of each UART frame. Total time is 400bit/1.5Mbps = 266.67us.

The time period that relay path receives one-byte log data is 10bit/115200bps = 86.8us.

During TAA sends log data from path 1~4, 266.67 / 86.8 = 3 bytes data is received from 3081 to relay path FIFO.

After TAA switches to relay path, there is 3 + 7 = 10 bytes data in relay path FIFO, which is smaller than 12 bytes. TAA can handle relay path in time so that bt_log_fifo2 will not overflow in the worst case under the default baud rate setting. The baud rate of relay path won’t normally change, it’s not suggested to lower LOGUART’s Tx baud rate when all five paths are enabled in case of relay path overflow.

Path Enable and AGG Enable

Cases under different configurations of Tx path enable (PATHx_EN, x=1, 2, 3, 4, 5) and Tx AGG function enable (AGG_EN) are listed in the following table. When Tx path is disabled, log will not be stored in its log FIFO.

Value	Disable all paths	Enable only one path	Enable some or all paths
AGG_EN = 0	No log	Log of this path show normally, no AGG header (recommended)	Disordered log may show
AGG_EN = 1		Log of this path show normally, with AGG header	Log of enabled path show normally

Note

If AGG is disabled and multiple paths are enabled, a disordered log is shown when more than one path is sending log data.

It’s recommended to re-initialize LOGUART after changing AGG_EN. Enable bit of each path can be changed on-the-fly if needed, but the disordered log may occur for a short time.

Path enable and disable need sync time, the correct steps are as follows:

1. Enable path

2. Delay 1us

3. Write to Tx path fifo

4. Check until Tx fifo is empty

5. Disable path

6. Delay 1us

Because of synchronization time of register, the settings are still as before until it takes effect. For example, some log can still be put into path fifo during synchronization time after disable path.

The baud rate of LOGUART should not be changed unless you have to. The steps of changing baud rate are as follows:

1. Wait until all the log data are transmitted out of Tx FIFO.

2. Disable all the enabled paths.

3. Re-configurate baudrate.

4. Enabled needed paths.

Interrupt Control

This section describes different interrupt types:

• Receiver Line Status Interrupt

• Receiver Data Available or Trigger Level Reached Interrupt

• Timeout Interrupt

• Tx FIFO Empty Interrupt

• Monitor Interrupt

Receiver Line Status Interrupt

• Source: Parity, overrun or framing errors or break interrupt

• Event flag: in LSR

  • RXFIFO_ERR for all

  • PARITY_ERR for parity error

  • OVERRUN_ERR for overrun

  • FRAMING_ERR for framing error

  • BREAK_ERR_INT for break

• Enable control: controller by ELSI bit in IER

• Reset control: controller by RLSICF bit in ICR

• Remark:

  • If some of the events happen, its separate flag and RXFIFO_ERR are all set.

    • For example, PARITY_ERR and RXFIFO_ERR is set if parity error happens.

  • RLSICF clears all the event flags.

Receiver Data Available or Trigger Level Reached Interrupt

• Source: FIFO trigger level reached or Rx FIFO full interrupt

• Event flag: in LSR

  • RXFIFO_INT

• Enable control: controller by ERBI bit in IER

• Reset control: FIFO drops below trigger level

• Remark: RXFIFO_INT is used only as interrupt flag, not as status flag.

Timeout Interrupt

• Source: Parity, overrun or framing errors or break interrupt

• Event flag: in LSR

  • TIMEOUT_INT

• Enable control: controller by ETOI bit in IER

• Reset control: controller by TOICF bit in ICR

• Remark: TIMEOUT_INT is used only as interrupt flag, not as status flag.

Tx FIFO Empty Interrupt

• Source: Tx FIFO Empty interrupt

• Event flag: in LSR

  • TXFIFO_EMPTY for path1

  • TXFIFO_EMPTY for path2

  • TXFIFO_EMPTY for path3

  • TXFIFO_EMPTY for path4

• Enable control: controller by ETPFEI bit in IER

• Reset control: writing to the Tx FIFO of path

• Remark: Tx FIFO empty interrupt is shared by path 1~4, but only one path can enable this interrupt at most at one time. It is decided by ETPFEI bit in IER.

Monitor Interrupt

• Source: Rx path monitor done interrupt

• Event flag: in LSR

  • MONITOR_DONE_IN

• Enable control: controller by EMDI bit in IER

• Reset control: controller by MDICF bit in ICR

Core Mask Interrupt

When interrupt switches between cores, it need to notify the other core to close the interrupt. To solve this problem, core mask interrupts are added. Core can mask interrupt independently. It is shown in the following figure.

• Source: Core mask interrupt

• Mask control: controller by km4_loguart_intr_mask bit and km0_loguart_intr_mask bit in IMR.

Registers

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Base Address: 0x4100F000

Name	Address offset	Access	Description
REG_UART_DLL	000h	R/W	The low 8 bits of divisor coefficient only valid when the DLAB bit of LCR bit [7] = 1
REG_UART_IER	004h	R/W	Generate enable and disable interrupt by the UART, only valid when the DLAB bit of LCR bit [7] = 0
REG_UART_IIR	008h	R	Interrupt source indication
REG_UART_LCR	00Ch	R/W	Set the general communication parameters
REG_UART_MCR	010h	R/W	It is used to perform handshaking actions with the attached device
REG_UART_LSR	014h	R	Indicate the current state of communication and errors
REG_UART_MSR	018h	R	It contains information about the four incoming modem control lines on the device
REG_UART_SCR	01Ch	R/W	It is used to store information of Tx
REG_UART_STSR	020h	R/W	Indicate the information of Tx baud rate
REG_UART_RBR	024h	R	The buffers of received data
REG_UART_MISCR	028h	R/W	Provide DMA and IrDA related information
REG_UART_REG_SIR_TX_PWC0	02Ch	R/W	Indicates the shift value of SIR Tx pulse
REG_UART_REG_SIR_RX_PFC	030h	R/W	Indicates the threshold of SIR Rx pulse
REG_UART_REG_BAUD_MON	034h	R/W	Monitor the baud rate of Rx pulse
REG_UART_REG_DBG	03Ch	R	Debug
REG_UART_REG_RX_PATH_CTRL	040h	R/W	Monitor the Rx baud rate error and Rx baudrate factor setting
REG_UART_REG_MON_BAUD_CTRL	044h	R/W	Monitor the baud rate of Rx path
REG_UART_REG_MON_BAUD_STS	048h	R/W	Status of monitor the baud rate of Rx path
REG_UART_REG_MON_CYC_NUM	04Ch	R	Monitored clock cycle number of Rx path
REG_UART_REG_RX_BYTE_CNT	050h	R/W	Count the number of data read from rxfifo (byte)
REG_UART_FCR	054h	R/W	FIFO control
REG_UART_AGGC	058h	R/W	Set the general communication parameters
REG_UART_THR0	05Ch	R/W
REG_UART_THR1	060h	R/W
REG_UART_THR2	064h	R/W
REG_UART_THR3	068h	R/W
REG_UART_RP_LCR	06Ch	R/W	Set the general communication parameters
REG_UART_RP_RX_PATH_CTRL	070h	R/W	Rx baudrate factor setting of relay path
REG_UART_ICR	074h	R/W	Interrupt clear register
REG_LOGUART_INTERRUPT_MASK	078h	R/W
REG_LOGUART_DUMMY	0F0h	R

REG_UART_DLL

• Name : UART divisor length register

• Size : 32

• Address offset : 000h

• Read/write access : R/W

The low 8 bits of divisor coefficient only valid when the DLAB bit of LCR bit [7] = 1

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7:0	BAUD	R/W	0x0	The low 8 bits of divisor coefficient (not used)

REG_UART_IER

• Name : UART interrupt enable register

• Size : 32

• Address offset : 004h

• Read/write access : R/W

Generate enable and disable interrupt by the UART, only valid when the DLAB bit of LCR bit [7] = 0

Bit	Symbol	Access	Reset	Description
31:11	RSVD	R	-	Reserved
10:8	ETPFEI	R/W	0x0	Tx Path FIFO Empty interrupt (ETPFEI) (Tx Path FIFO empty) e nable control 000: All Tx Path FIFO empty interrupt disabled 001: Tx Path1 FIFO Empty interrupt enabled 010: Tx Path2 FIFO Empty interrupt enabled 011: Tx Path3 FIFO Empty interrupt enabled 100: Tx Path4 FIFO Empty interrupt enabled Others: Reserved
7:6	RSVD	R	-	Reserved
5	ETOI	R/W	0x0	Rx timeout interrupt (ETOI) enable
4	EMDI	R/W	0x0	Rx path monitor done interrupt (EMDI) enable
3	EDSSI	R/W	0x0	Modem Status Interrupt (EDSSI) (modem status transition) ena ble
2	ELSI	R/W	0x0	Receiver Line Status Interrupt (ELSI) (receiver line status) enable
1	RSVD	R	-	Reserved
0	ERBI	R/W	0x0	Received Data Available Interrupt (ERBFI) (Rx trigger) enabl e

REG_UART_IIR

• Name : UART interrupt identification register

• Size : 32

• Address offset : 008h

• Read/write access : R

Interrupt source indication

Bit	Symbol	Access	Reset	Description
31:1	RSVD	R	-	Reserved
0	INT_PEND	R	0x1	Indicate if the interrupt is pending. 0: Pending, and the IIR contents may be used as a pointer to the appropriate interrupt service routine. 1: No interrupt is pending.

REG_UART_LCR

• Name : UART line control register

• Size : 32

• Address offset : 00Ch

• Read/write access : R/W

Set the general communication parameters

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7	DLAB	R/W	0x0	Divisor Latch Access bit, and control the accessibility of t he DLL, DLM and IER registers 0: The divisor latches not accessible; IER accessible 1: The divisor latches accessible; DLL and DLM accessible Note THR/RBR don’t care the value of dlab bit
6	BRCTL	R/W	0x0	Break Control bit 0: break signal disable 1: break signal enable (logic ‘0’)
5	STKP	R/W	0x0	Stick Parity bit 0: Not stick parity, the parity type is ODD or EVEN (depen ding on eps) 1: Stick parity, eps=1: low parity (1’b0); eps=0: high par ity (1’b1)
4	EPS	R/W	0x0	Even Parity select 0: Odd parity, the number of Logic “1” is odd. 1: Even parity, the number of Logic “1” is even.
3	PEN	R/W	0x0	Parity Enable 0: No parity bit 1: Parity bit is generated on each outgoing character and is checked on each incoming one
2	STB	R/W	0x0	Stop bits length selection 0: 1 stop bit 1: 2 stop bits Note The receiver always checks the first stop bit only.
1	RSVD	R	-	Reserved
0	WLS0	R/W	0x1	Word length selection 0: 7 bits data 1: 8 bits data

REG_UART_MCR

• Name : UART modem control register

• Size : 32

• Address offset : 010h

• Read/write access : R/W

It is used to perform handshaking actions with the attached device

Bit	Symbol	Access	Reset	Description
31:6	RSVD	R	-	Reserved
5	AFE	R/W	0x0	Auto flow control enable
4	LOOP_EN	R/W	0x0	LoopBack mode 0: Normal operation mode 1: Loopback mode
3	OUT2	R/W	0x0	Auxiliary output 2 Bit[3] affects the OUT2_ output in a manner identical to tha t described above set to 0 In loopback mode, connected to Data Carrier Detect (DCD)
2	OUT1	R/W	0x0	Auxiliary output 1 Bit3 affects the OUT1_ output in a manner identical to that described above set to 0 In loopback mode, connected to Ring Indicator (RI)
1	RTS	R/W	0x0	Request to Send (RTS) signal control 0: RTS is logic 1. 1: RTS is logic 0. This bit controls the RTS_ output, Bit 1 affects the RTS_ ou tput in a manner identical to that described above set to 0.
0	DTR	R/W	0x0	Data Terminal Ready (DTR) signal control 0: DTR is logic 1. 1: DTR is logic 0. This bit controls the DTR output.

REG_UART_LSR

• Name : UART line status register

• Size : 32

• Address offset : 014h

• Read/write access : R

Indicate the current state of communication and errors

Bit	Symbol	Access	Reset	Description
31:24	RX_FIFO_PTR	R		Data bytes count in the receive FIFO: the value of rx_fifo_p tr[7:0] indicates the data bytes number received in the FIFO .
23	TP4F_NOT_FULL	R		Tx Path4 FIFO not full indicator
22	TP3F_NOT_FULL	R		Tx Path3 FIFO not full indicator
21	TP2F_NOT_FULL	R		Tx Path2 FIFO not full indicator
20	TP1F_NOT_FULL	R		Tx Path1 FIFO not full indicator
19	TP4F_EMPTY	R		Tx Path4 FIFO empty indicator
18	TP3F_EMPTY	R		Tx Path3 FIFO empty indicator
17	TP2F_EMPTY	R		Tx Path2 FIFO empty indicator
16	TP1F_EMPTY	R		Tx Path1 FIFO empty indicator
15	RP_RXFIFO_ERR	R		Relay Path rx_error,only valid when the FCR[12] set to 1 0: Clear when the CPU reads the LSR, if there are no subse quent errors in the relay path FIFO 1: Parity error, framing error or break indication in the relay path FIFO
14	TIMEOUT_INT	R		This bit is only set when Rx Timeout interrupt is enabled(ET OI is set) 1: at least one character in the FIFO but no character has been input to the FIFO or reading from it for the time dur ation, which depends on the value in register REG_RX_PATH_ CTRL[31:16]
13	RXFIFO_INT	R		This bit is only set when Received Data Available Interrupt interrupt is enabled(ERBI is set) 1: FIFO Trigger level reached or Rx FIFO full
12	RP_FRM_ERR	R		Relay Path Framing Error (FE) indicator 0: No framing error in the current character 1: The received character does not have a valid stop bit
11	RP_PAR_ERR	R		Relay Path Parity Error (PE) indicator 0: No parity error in current character 1: The received character does not have the correct parity bit
10	RPF_OVR_ERR	R		Relay Path FIFO Overrun Error (OE) indicator 0: No Overrun state 1: The transmission is continue although the Relay FIFO is full
9	RPF_NOT_FULL	R	0x1	Relay Path FIFO Not FULL (NF) indicator 0: Relay path FIFO is full 1: Relay path FIFO is not full
8	RPF_DRDY	R		Relay Path FIFO Data Ready (DR) indicator 0: No characters in the Relay Receiver FIFO 1: At least one character has been received and transferre d into the Relay path FIFO
7	RXFIFO_ERR	R		Uart_rx_error, only valid when the FCR bit [0] set to 1 0: Clear when the CPU reads the LSR, if there are no subse quent errors in the FIFO 1: Parity error, overrun error,framing error or break indi cation in the FIFO
6	TX_EMPTY	R		TX fifo empty indicator
5	MONITOR_DONE_INT	R	0	This bit is only set when Rx Path Monitor Done interrupt is enabled(EMDI is set) 1: Rx path monitor done
4	BREAK_INT	R		Break Interrupt (BI) indicator 0: No break condition in the current character 1: The received data input held in the Spacing ( logic 0) state is longer than a full word transmission time
3	FRM_ERR	R		Framing Error (FE) indicator 0: No framing error in the current character 1: The received character does not have a valid stop bit
2	PAR_ERR	R		Parity Error (PE) indicator 0: No parity error in current character 1: The received character does not have the correct parity bit
1	OVR_ERR	R		Overrun Error (OE) indicator 0: No Overrun state 1: The transmission is continue although the Rx FIFO is fu ll
0	DRDY	R		Data Ready (DR) indicator 0: No characters in the Receiver FIFO 1: At least one character has been received and transferre d into the FIFO

REG_UART_MSR

• Name : UART modem status register

• Size : 32

• Address offset : 018h

• Read/write access : R

It contains information about the four incoming modem control lines on the device

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7	R_DCD	R	0x0	Complement of the DCD input or equals to Out2 in loopback mo de.
6	R_RI	R	0x0	Complement of the RI input or equals to Out1 in loopback mod e.
5	R_DSR	R	0x0	Complement of the DSR input or equals to DTR in loopback mod e.
4	R_CTS	R	0x0	Complement of the CTS input or equals to RTS in loopback mod e.
3	D_DCD	R		Delta Data Carrier Detect (DDCD) indicator 0: Otherwise 1: The DCD line has changed its state
2	TERI	R		Trailing Edge of Ring Indicator (TERI) detector 0: Otherwise 1: The RI line has changed its state from low to high stat e
1	D_DSR	R		Delta Data Set Ready (DDSR) indicator 0: Otherwise 1: The DSR line has changed its state
0	D_CTS	R		Delta Clear to Send (DCTS) indicator 0: Otherwise 1: The CTS line has changed its state

REG_UART_SCR

• Name : UART scratch pad register

• Size : 32

• Address offset : 01Ch

• Read/write access : R/W

It is used to store information of Tx

Bit	Symbol	Access	Reset	Description
31:27	RSVD	R	-	Reserved
26:16	XFACTOR_ADJ	R/W	0x0	One factor of Baud rate calculation for Tx path
15:12	RSVD	R	-	Reserved
11:8	DBG_SEL	R/W	0x0	Debug port selection
7	SCRATCH_7	R/W	0x0	Clear Rx break signal interrupt status
6:0	SCRATCH_6_0	R/W	0x30	Bit[6]: Rx break signal interrupt enable Bit[5]: fl_set_bi_err Bit[4]: fl_frame_err Bit[3]: pin_lb_test Bit[2:0]: reserved

REG_UART_STSR

• Name : UART STS register

• Size : 32

• Address offset : 020h

• Read/write access : R/W

Indicate the information of Tx baud rate

Bit	Symbol	Access	Reset	Description
31:24	RSVD	R	-	Reserved
23:4	XFACTOR	R/W	0x1047	Factor of Baud rate calculation for Tx path
3:0	RSVD	R	-	Reserved

REG_UART_RBR

• Name : UART receiver buffer register

• Size : 32

• Address offset : 024h

• Read/write access : R

The buffers of received data

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7:0	RXDATABIT	R	0x0	Tx data bit 0~7 Note Bit[0] is the least significant bit. It is the first bit serially received/transmitted.

REG_UART_MISCR

• Name : UART MISC control register

• Size : 32

• Address offset : 028h

• Read/write access : R/W

Provide DMA and IrDA related information

Bit	Symbol	Access	Reset	Description
31:25	RSVD	R	-	Reserved
24	CLR_DUMMY_FLAG	R/W	0x0	Indicate the clearing of dummy data
23:16	DUMMY_DATA	R/W	0x0	Store dummy data, when UART is DMA flow controller, dummy da ta is padded for last RXDMA burst request
15	RXDMA_OWNER	R/W	0x0	Indicate the DMA flow controller for UART Rx DMA1 0: GDMA 1: UART, interrupt enable signal other than erpd should be masked
14	IRDA_RX_INV	R/W	0x0	Irda_rx_i reverse input enable
13	IRDA_TX_INV	R/W	0x0	Irda_tx_o reverse output enable
12:8	RXDMA_BURSTSIZE	R/W	0x4	RXDMA burstsize, maximum value is 16
7:3	TXDMA_BURSTSIZE	R/W	0x4	TXDMA burstsize, maximum value is 16
2	RXDMA_EN	R/W	0x0	RXDMA enable, valid when dma_mode in FCR is 1’b1
1	TXDMA_EN	R/W	0x0	TXDMA enable, valid when dma_mode in FCR is 1’b1
0	IRDA_ENABLE	R/W	0x0	IrDA SIR mode enable 0: UART mode only 1: UART is co-work with IRDA SIR mode

REG_UART_REG_SIR_TX_PWC0

• Name : UART IRDA SIR Tx pulse width control 0 register

• Size : 32

• Address offset : 02Ch

• Read/write access : R/W

Indicates the shift value of SIR Tx pulse

Bit	Symbol	Access	Reset	Description
31	UPPERBOUND_SHIFTRIGHT	R/W	0x0	Indicate the shift type of SIR Tx pulse’s right edge 0: Shift left, minus offset value of upperbound_shiftval 1: Shift right, plus offset value of upperbound_shiftval
30:16	UPPERBOUND_SHIFTVAL	R/W	0x0	The shift value of SIR Tx pulse’s right edge
15	LOWBOUND_SHIFTRIGHT	R/W	0x0	Indicate the shift type of SIR Tx pulse’s left edge 0: Shift left, minus offset value of lowbound_shiftval 1: Shift right, plus offset value of lowbound_shiftval
14:0	LOWBOUND_SHIFTVAL	R/W	0x0	The shift value of SIR Tx pulse’s left edge

REG_UART_REG_SIR_RX_PFC

• Name : UART IRDA SIR Rx pulse filter control register

• Size : 32

• Address offset : 030h

• Read/write access : R/W

Indicates the threshold of SIR Rx pulse

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:1	R_SIR_RX_FILTER_THRS	R/W	0x0	The threshold of SIR Rx filter. Rx pulse is valid only when Rx pulse width is larger than the threshold.
0	R_SIR_RX_FILTER_EN	R/W	0x0	IrDA SIR Rx filter enable

REG_UART_REG_BAUD_MON

• Name : UART baud monitor register

• Size : 32

• Address offset : 034h

• Read/write access : R/W

Monitor the baud rate of Rx pulse

Bit	Symbol	Access	Reset	Description
31	TOGGLE_MON_EN	R/W	0x0	Toggle monitor enable
30	MON_DATA_VLD	R		Indicate valid monitoring data
29:24	FALLING_THRESH	R/W	0x7	Indicate the threshold of Rx data rising edge
23:12	MIN_LOW_PERIOD	R		Minimum space of consecutive logic “0” of Rx data
11:0	MIN_FALL_SPACE	R		Minimum space of adjacent falling edge of Rx data

REG_UART_REG_DBG

• Name : UART debug register

• Size : 32

• Address offset : 03Ch

• Read/write access : R

Debug

Bit	Symbol	Access	Reset	Description
31:0	DBG_UART	R		The output value of debug port, depend on dbg_sel value in S CR[2:0]

REG_UART_REG_RX_PATH_CTRL

• Name : UART Rx path control register

• Size : 32

• Address offset : 040h

• Read/write access : R/W

Monitor the Rx baud rate error and Rx baudrate factor setting

Bit	Symbol	Access	Reset	Description
31:16	R_RXTO_THRS	R/W	0x40	Indicate the timeout threshold of Rx path, unit in one-bit time
15:14	RSVD	R	-	Reserved
13:3	RXBAUD_ADJ_10_0	R/W	0x0	One factor of Baud rate calculation for Rx path, similar wit h xfactor_adj
2	R_RST_NEWRX_N	R/W	0x0	Reset new Rx path, low active
1:0	RSVD	R	-	Reserved

REG_UART_REG_MON_BAUD_CTRL

• Name : UART monitor baud rate control register

• Size : 32

• Address offset : 044h

• Read/write access : R/W

Monitor the baud rate of Rx path

Bit	Symbol	Access	Reset	Description
31:30	RSVD	R	-	Reserved
29	R_UPD_OSC_IN_XTAL	R/W	0x0	Update parameter r_cycnum_perbit_osc(during the update of pa rameter r_cycnum_perbit_xtal) enable
28:9	R_CYCNUM_PERBIT_OSC	R/W	0x0	Indicate the average OSC clock cycle number of one bit, for Rx path OSC clock Note Sortware sets the initial value; hardware updates it depe nding on the monitor result.
8:1	R_BIT_NUM_THRES	R/W	0x0	Indicate the bit number threshold of one monitor period, max value is 127.
0	R_MON_BAUD_EN	R/W	0x0	Monitor Rx baud enable

REG_UART_REG_MON_BAUD_STS

• Name : UART monitor baud rate status register

• Size : 32

• Address offset : 048h

• Read/write access : R/W

Status of monitor the baud rate of Rx path

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:21	RO_MON_TOTAL_BIT	R	0x0	Indicate the number of bits actually monitored
20	RO_MON_RDY	R	0x0	Indicate the finish of calculation of actual cycle number pe r bit. It’s cleared when r_mon_baud_en is 0.
19:0	R_CYCNUM_PERBIT_XTAL	R/W	0x0	Indicate the fractional xtal clock cycle number of one bit, for Rx path xtal clk Note Sortware sets the initial value; hardware updates it depe nding on the monitor result.

REG_UART_REG_MON_CYC_NUM

• Name : UART monitored cycle number register

• Size : 32

• Address offset : 04Ch

• Read/write access : R

Monitored clock cycle number of Rx path

Bit	Symbol	Access	Reset	Description
31:28	RSVD	R	-	Reserved
27:0	RO_MON_TOTAL_CYCLE	R		Indicate the number of clock cycle actually monitored

REG_UART_REG_RX_BYTE_CNT

• Name : UART Rx data byte count register

• Size : 32

• Address offset : 050h

• Read/write access : R/W

Count the number of data read from rxfifo (byte)

Bit	Symbol	Access	Reset	Description
31:17	RSVD	R	-	Reserved
16	CLR_RX_BYTE_CNT	R/W	0x0	Write 1 to clear ro_rx_byte_cnt
15:0	RO_RX_BYTE_CNT	R		Count the byte number of data read from rxfifo

REG_UART_FCR

• Name : UART FIFO control register

• Size : 32

• Address offset : 054h

• Read/write access : R/W

FIFO control

Bit	Symbol	Access	Reset	Description
31:14	RSVD	R	-	Reserved
13	RP_RECV_CLR	R/W	0x0	Clear Relay Path receiving
12	RP_FIFO_EN	R/W	0x1	Error report of Relay Path RCVR FIFO field enable,
11:8	RSVD	R	-	Reserved
7:6	RECVTRG	R/W	0x3	Define the 16-entry Receiver FIFO Interrupt trigger level ( 0~15 bytes) 00: 1 byte 01: FIFO_DEPTH/4 10: FIFO_DEPTH/2 11: FIFO_DEPTH-2
5:4	RSVD	R	-	Reserved
3	DMA_MODE	R/W	0x0	Support DMA mode (cooperating with DW DDMA in the data path)
2	RSVD	R	-	Reserved
1	RECV_CLR	R/W	0x0	Clear receiving
0	FIFO_EN	R/W	0x1	Error report of RCVR FIFO field enable

REG_UART_AGGC

• Name : UART AGG control register

• Size : 32

• Address offset : 058h

• Read/write access : R/W

Set the general communication parameters

Bit	Symbol	Access	Reset	Description
31	RP_EN	R/W	0x0	Relay Rx Path enable 0: Disable 1: Enable
30	TP4_EN	R/W	0x0	Tx Path4 enable 0: Disable 1: Enable
29	TP3_EN	R/W	0x0	Tx Path3 enable 0: Disable 1: Enable
28	TP2_EN	R/W	0x0	Tx Path2 enable 0: Disable 1: Enable
27	TP1_EN	R/W	0x0	Tx Path1 enable 0: Disable 1: Enable
26	AGG_EN	R/W	0x0	Tx AGG function enable
25:12	AGG_TO	R/W	0xBB8	AGG timeout Unit is one baudrate period of loguart Tx, default is 1ms if Tx baudrate is 3Mbps. Data should be sent from log FIFO to tx_fifo if idle time > AGG timeout, even if there is just only one byte in log FIFO of the path.
11:8	AGG_TH	R/W	0x7	AGG threshold 4’0000: 1 4’0111: 8 Numbers above 4’0111 are reserved.
7:0	AGG_SYNC_PAT	R/W	0xFF	AGG packet Start

REG_UART_THRx

• Name : UART transmitter holding register x

• Size : 32

• Address offset : 05Ch + 04h * x (x=0, 1, 2, 3)

• Read/write access : R/W

The buffer of transmitted data

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7:0	TXxDATABIT	R/W	0x0	Tx data bit 0~7 Note Bit 0 is the least significant bit. It is the first bit s erially received/transmitted

REG_UART_RP_LCR

• Name : UART Relay Rx Path line control register

• Size : 32

• Address offset : 06Ch

• Read/write access : R/W

Set the general communication parameters

Bit	Symbol	Access	Reset	Description
31:12	RP_RXBAUD_19_0	R/W	0x0	Factor of Baud rate calculation for Relay path
11:8	RSVD	R	-	Reserved
7	RP_DLAB	R/W	0x0	Divisor Latch Access bit, and control the accessibility of t he DLL, DLM and IER registers 0: The divisor latches not accessible; IER accessible 1: The divisor latches accessible; DLL and DLM accessible Note THR/RBR don not care the value of dlab bit.
6	RSVD	R	-	Reserved
5	RP_STKP	R/W	0x0	Stick Parity bit 0: Not stick parity, the parity type is ODD or EVEN (depen d on eps) 1: Stick parity, eps=1: low parity (1’b0); eps=0: high par ity (1’b1)
4	RP_EPS	R/W	0x0	Even Parity select 0: Odd parity, the number of Logic “1” is odd. 1: Even parity, the number of Logic “1” is even.
3	RP_PEN	R/W	0x0	Parity Enable 0: No parity bit 1: Parity bit is generated on each outgoing character and is checked on each incoming one.
2	RP_STB	R/W	0x0	Stop bits length selection 0: 1 stop bit 1: 2 stop bits Note the receiver always checks the first stop bit only.
1	RSVD	R	-	Reserved
0	RP_WLS0	R/W	0x1	Word length selection 0: 7 bits data 1: 8 bits data

REG_UART_RP_RX_PATH_CTRL

• Name : UART Relay Rx path control register

• Size : 32

• Address offset : 070h

• Read/write access : R/W

Rx baudrate factor setting of relay path

Bit	Symbol	Access	Reset	Description
31:14	RSVD	R	-	Reserved
13:3	RP_RXBAUD_ADJ_10_0	R/W	0x0	One factor of Baud rate calculation for Relay path, similar with xfactor_adj
2	R_RST_RP_RX_N	R/W	0x0	Reset Relay Rx path, low active
1:0	RSVD	R	-	Reserved

REG_UART_ICR

• Name : UART interrupt clear register

• Size : 32

• Address offset : 074h

• Read/write access : R/W

Interrupt clear register

Bit	Symbol	Access	Reset	Description
31:4	RSVD	R	-	Reserved
3	RPRLSICF	R/W	0x0	Relay Path Receiver Line Statue Interrupt Clear Flag Writing 1 to this bit clears relay path’s PARITY_ERR, OVERRU N_ERR, FRAMING_ERR and RXFIFO_ERR in the USART_LSR register .
2	MDICF	R/W	0x0	Monitor done clear flag
1	TOICF	R/W	0x0	Timeout Interrupt Clear Flag
0	RLSICF	R/W	0x0	Receiver Line Statue Interrupt Clear Flag Writing 1 to this bit clears PARITY_ERR, OVERRUN_ERR, FRAMIN G_ERR, BREAK_ERR_INT and RXFIFO_ERR in the USART_LSR regist er.

REG_LOGUART_INTERRUPT_MASK

• Name : loguart interrupt mask Register

• Size : 32

• Address offset : 078h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:2	RSVD	R	-	Reserved
1	LOGUART_INTR_MASK_KM4	R/W	0x1	Mask loguart interrupt to km4 1:unmask 0:mask
0	LOGUART_INTR_MASK_KM0	R/W	0x1	Mask loguart interrupt to km0 1:unmask 0:mask

REG_LOGUART_DUMMY

• Name : Loguart Dummy Register

• Size : 32

• Address offset : 0F0h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	DUMMY	R	0x0	Rsvd for hw

Top Level Interface

The interface signals are shown in the following table.

Port name	I/O	Description
I/F signals	I/F signals	I/F signals
pclk	I	APB3 bus clock
presetn	I	Reset signal in bus clock domain, low active
clk_xtal	I	XTAL clock, for UART Tx path
xresetn	I	Reset signal in XTAL clock domain, low active
sclk	I	Mux clock of XTAL clock, fractional XTAL clock and OSC clock, for UART Rx path
sclk_sel	I	1: OSC clock 0: XTAL clock
sresetn	I	Reset signal in mux clock domain, low active
scan_mode	I	Scan test signal
paddr	I	APB3 bus signal
pwrite	I	APB3 bus signal
psel	I	APB3 bus signal
penable	I	APB3 bus signal
pwdata	I	APB3 bus signal
prdata	I	APB3 bus signal
pready	I	APB3 bus signal
pslverr	I	APB3 bus signal
rx_dma_single	O	DMA single request signal to GDMA for Rx path
rx_dma_req	O	DMA request signal to GDMA for Rx path
rx_dma_last	O	Indicate DMA the last data in Rx FIFO been read when UART configured as DMA flow controller
rx_dma_ack	I	DMA response signal from GDMA for Rx path
utxd	O	UART Tx data
urts_	O	Auto flow control signal
urxd	I	UART Rx data
urxd1	I	UART Rx data for relay path
ucts_	I	Auto flow control signal
uart_int	O	Interrupt signal of UART module
dbg_uart	O	Debug signal of UART module

Design Implementation

Arbitration Mechanism (AGG_EN =0, LOG_FULL_EN = 0)

To avoid errors caused by new design – Arbitration Mechanism (AGG_EN =0, default), it is necessary to back up the older design by adding bit LOG_FULL_EN, which can help to switch to the older design. By default, AGG_EN is set to 0 and LOG_FULL_EN is set to 1. When AGG_EN and LOG_FULL_EN are both set to 0, the older arbitration mechanism will be applied during LOGUART Tx. In this case, log FIFO of all Tx paths will be checked one by one. The next path will not be checked until all the data from the current path has been sent. If log data is written into one path FIFO continuously, log from other paths may not be printed on time or log from the different paths will be mixed up.

Note

If AGG_EN is set to 1, applied arbitration mechanism will be the same as described in Arbitration Mechanism (AGG_EN =1) no matter what LOG_FULL_EN is.

If AGG_EN and LOG_FULL_EN are both set to 0 and multiple paths are enabled, a disordered log may show up when more than one path is sending log data.

TAA Mechanism

Refer tofor detailed mechanism.

• Poll Tx Path by Round robin:

TAA checks log FIFO of all Tx paths one by one, and TAA sends no packet or only one packet to tx_fifo each time for one Tx path, so that every path can have the chance to send their data. When all Tx path is disabled, TAA FSM will stay in IDLE.

When plenty of log data needs to be printed and the left space of tx_fifo is less than 10byte, TAA FSM will not poll any more until remaining space of tx_fifo is at least 10 bytes. The data in the path FIFO which has already been polled will be load to Tx FIFO. Then TAA FSM stays to wait for polling next path before remaining space of tx_fifo is at least 10 bytes.

• Idle time mechanism:

Idle time of each channel is cleared and counted independently.

Idle time of one path starts to count when TAA switches to this path and confirms that there is at least 1 byte log data in the log FIFO but the number of log is below AGG_TH, also idle time of this path has been cleared in previous loop.

Idle time of one path is cleared before one packet of the path is sent, which means idle time has reached AGG_TO or number of log data in log FIFO has reached AGG_TH.

• Corner Case:

When TAA switched to one path, if idle time of one path has reached AGG_TO and there is N byte in its path FIFO at that time. However, log data is written into this path FIFO continuously so M byte (N < M) is in its path FIFO just before TAA attached header and transfer log data into tx_fifo. TAA will send M byte in this packet if M ≤ 8, or send 8 byte if M > 8.

TAA FSM

TAA FSM is illustrated below.

LOGUART transaction control FSM state description is illustrated below.

State name	Description
IDLE	IDLE state. The initial state after reset.
POLL_TP1	Poll transmit path 1
POLL_TP2	Poll transmit path 2
POLL_TP3	Poll transmit path 3
POLL_TP4	Poll transmit path 4
POLL_RP	Poll relay path
POLL_TP_FSM	Poll FSM for every path
START_TP	Start poll on the path
TP_LD_START	Start to load data to Tx FIFO
TP_LD_SYNC_PAT	Load Sync pattern
TP_LD_PATH_ID	Load path number and checksum
TP_LD_PAYLOAD	Load payload from current transmit path
TP_LD_END	Load end for current transmit path
END_TP	End poll on the current path

LOGUART FSM state machine transition is illustrated below.

From State	To State	Condition of transition
TAA_MAIN_FSM	TAA_MAIN_FSM	TAA_MAIN_FSM
IDLE	POLL_TP1	FSM reset released, and at least 1 log path is enabled, and Tx FIFO has more than 10 bytes left space.
POLL_TP1	POLL_TP2	Transmit path 1 is disabled
POLL_TP1	POLL_TP_FSM	Transmit path 1 is enabled and Tx FIFO has more than 10 bytes left space.
POLL_TP2	POLL_TP3	Transmit path 2 is disabled
POLL_TP2	POLL_TP_FSM	Transmit path 2 is enabled and Tx FIFO has more than 10 bytes left space.
POLL_TP3	POLL_TP4	Transmit path 3 is disabled
POLL_TP3	POLL_TP_FSM	Transmit path 3 is enabled and Tx FIFO has more than 10 bytes left space.
POLL_TP4	POLL_RP	Transmit path 4 is disabled
POLL_TP4	POLL_TP_FSM	Transmit path 4 is enabled and Tx FIFO has more than 10 bytes left space.
POLL_RP	POLL_TP1	Relay path is disabled
POLL_RP	POLL_TP_FSM	Relay path is enabled and Tx FIFO has more than 10 bytes left space.
POLL_TP_FSM	POLL_TP1	Relay path polling has finished
POLL_TP_FSM	POLL_TP2	Transmit path 1 polling has finished
POLL_TP_FSM	POLL_TP3	Transmit path 2 polling has finished
POLL_TP_FSM	POLL_TP4	Transmit path 3 polling has finished
POLL_TP_FSM	POLL_RP	Transmit path 4 polling has finished
POLL_TP_FSM	POLL_TP_FSM	POLL_TP_FSM
START_TP	END_TP	The current path FIFO is empty or The bytes in the path FIFO is below the threshold and still not time out.
START_TP	TP_LD_START	Time out or the bytes in the path FIFO is above the threshold.
TP_LD_START	TP_LD_SYNC_PAT	Tx AGG is enabled
TP_LD_START	TP_LD_PAYLOAD	Tx AGG is disabled
TP_LD_SYNC_PAT	TP_LD_PATH_ID	No condition
TP_LD_PATH_ID	TP_LD_PAYLOAD	No condition
TP_LD_PAYLOAD	TP_LD_END	Payload load to Tx FIFO completed(Load counter has reached the top value).
TP_LD_END	END_TP	No condition

The following table gives the IO port description of TAA circuit.

Port name	I/O	Description
pclk	I	APB3 bus clock
clk_xtal	I	XTAL clock, for UART Tx, 40MHz
xresetn	I	UART reset signal synced with clk_xtal, low active
rp_en	I	Relay RX path enable 0: disable 1: enabled
tp4_en	I	Tx path4 enable 0: disable 1: enabled
tp3_en	I	Tx path3 enable 0: disable 1: enabled
tp2_en	I	Tx path2 enable 0: disable 1: enabled
tp1_en	I	Tx path1 enable 0: disable 1: enabled
agg_en	I	Tx AGG function enable
agg_to[13:0]	I	AGG timeout Unit is one baud rate period of LOGUART Tx, default is 1ms if Tx baud rate is 3Mbps. Data should be sent from log FIFO to tx_fifo if idle time > AGG timeout, even if there is just only one byte in log FIFO of the path.
agg_th[3:0]	I	AGG threshold 4’0000: represents 1 4’0111: represents 8 Number above 4’0111: reserved
agg_sync_pat[7:0]	I	AGG threshold 4’0000: represents 1 4’0111: represents 8 Number above 4’0111: reserved
tp1f_bytenum[3:0]	I	Tx path1 FIFO valid data byte number indicator
tp2f_bytenum[3:0]	I	Tx path2 FIFO valid data byte number indicator
tp3f_bytenum[3:0]	I	Tx path3 FIFO valid data byte number indicator
tp4f_bytenum[3:0]	I	Tx path4 FIFO valid data byte number indicator
rpf_bytenum[3:0]	I	Relay Rx path FIFO valid data byte number indicator
txf_unoccupied_bytenum[5:0]	I	Tx FIFO indicator
tp1f_rdata[7:0]	I	Tx path1 FIFO read data
tp2f_rdata[7:0]	I	Tx path2 FIFO read data
tp3f_rdata[7:0]	I	Tx path3 FIFO read data
tp4f_rdata[7:0]	I	Tx path4 FIFO read data
rpf_rdata[7:0]	I	Relay Rx path FIFO read data
tx_baud_pulse	I	Tx baudrate clock pulse
tp1f_rd	O	Tx path1 FIFO read
tp2f_rd	O	Tx path2 FIFO read
tp3f_rd	O	Tx path3 FIFO read
tp4f_rd	O	Tx path4 FIFO read
rpf_rd	O	Relay Rx path FIFO read
txf_wdata[7:0]	O	Tx FIFO write data
txf_wr	O	Tx FIFO write

Clk Structure of Rx Path

• Rx 0 path: use sclk as base clock, keep the same as general purpose UART

• Rx 1 path: use clk_xtal as base clock (do not support low power application).

Rx Path

• Rx 0 path: keep the same as general purpose UART

• Rx 1 path: no baudrate monitor feature

Interrupt Control

The following table gives the description of different interrupt.

ID	Priority	Type	Source	Reset control
3’b011	1st	Receiver Line Status	Parity, overrun or Framing errors or break interrupt	Read the Line Status Register
3’b010	2nd	Receiver Data Available	RX FIFO Trigger level reached or rxfifo full	FIFO drops below trigger level
3’b110	2nd	Timeout Indication	at least 1 character in the FIFO but no character has been input to the FIFO or read from it for the last 4 characters times	Read Receiver Buffer Register or Clearing rxfifo
3’b001	3rd	Tx path FIFO empty	Tx path FIFO empty	Writing to the Tx path FIFO or read IIR
3’b000	4th	Modem Status	CTS, DSR, RI, or DCD	Read the Modem status register
3’b100	5th	Monitor Baud Status	new Rx path monitor done interrupt	Read the monitor baud rate status register (REG_MON_BAUD_STS)

Corner Case and Exception

When TAA switched to one path, if idle time of one path has reached AGG_TO and there is N byte in its path FIFO at that time. However, log data is written into this path FIFO continuously so M byte (N < M) is in its path FIFO just before TAA attached header and transfer log data into tx_fifo. TAA will send M byte in this packet if M ≤ 8, or send 8 byte if M > 8.

When plenty of log data needs to be printed and the left space of tx_fifo is less than 10byte, TAA will not transfer log data from any path to tx_fifo until remaining space of tx_fifo is at least 10 byte.

Assuming Tx baud rate of relay path is 115200bps and baud rate of LOGUART is 3Mbps. One UART frame is 1 start bit, 8 bit data and 1 stop bit. If 7 byte is transferred into bt_log_fifo2 and idle time of relay path hasn’t reached AGG_TO, TAA will switch to path1. In corner case when log data from relay path is continuously received into bt_log_fifo2 but TAA needs to send packet of all the path 1, 2, 3, 4 before switches to relay path.

Total number of log data from path 1,2,3,4 is (8B+2B)*4 = 40B, which is 320bit. Total number of UART data is 400bit. Total time is 400bit / 3Mbps = 133.33us

The time period that relay path receive one byte log data is 10bit / 115200bps = 86.8us

TAA can handle relay path in time so bt_log_fifo2 will not overflow in the worst case.

Design Flow Notes