PSRAM AXI Clutch

Introduction

Check if psram controller has axi access, start idle counter when there’s no axi access. Once the idle counter reaching the preset idle value, shutdown DQ pads’ rx path by asserting high to DQ pads’ PD pin and axi access will be blocked. If there is axi access to psram controller afterwards, DQ pads will resume first and this resume process takes tens of nanoseconds(50ns at worst corner). Axi acess will still be blocked until the resume counter reaching the preset resume value

Some information from pad designer:

• PAD的PD pin只對自己的Rx有作用, PWDPAD15N=0 是關掉DDR domain的level shifter, 包括REF, ZQ…等.

• 從DQ PAD Rx的角度出發, 兩個的效果是一樣的, 但是對DDR PAD domain的leakage有些微的差異

There are two options to power down DDR pads as shown below:

PWDPAD15N(3.3V)	PD	Tx	Rx
0	1/0	Power down	Power down
0	0	Power down	Power down
1	1	Controlled by E/TE pin	Power down
1	0	Controlled by E/TE pin	Power on

Using pwdpad15n to shutdown both DQ pads’ tx and rx path can minimize DQ pads’ power consumption. However, pwdpad15n signal must raise its voltage to 3.3V by going through level shift(regu) whose delay is more than 100ns at typical case. This can impact ddr performance since we must wait enough time to bypass this level shift delay every time we resume pads from power down state.

Using PD to shutdown DQ pads’ rx path will result in the power consumption slightly more than the case using pwdpad15n, while PD signal can come directly from AMEBACORE power domain. dq_se[15:0] (connecting to E pin) and dq_ie[15:0] (connecting to TE pin) are all being kept low at idle state or self-refresh state.

Besides, DQ pads need some time(50ns at worst case) when resuming from power down state. Thus we will only use PD pin to power down DQ pads’ rx path in this design.

Power consumption of DDR pads at different cases is listed below.

	PWDPAD15	PD	Core电流	IO 电流
DQ区	0	N/A	55.7uA	593.2uA
DQ区	3.3	1 (with E=0 & TE=0)	+70uA(TC corner), compared with PWDPAD15=0	+70uA(TC corner), compared with PWDPAD15=0
DQ区	3.3	0	34.6uA	35.6mA

Features

Unit of idle counter: 1us

Max idle value: 512us, configured by register

Functional Description

Block Diagram

psram_axi_clutch block diagram is shown below.

psram_pad_pwd connection is shown below.

(Optional) Clock Diagram

Xtal_ck1m which comes from hs_timer xtal_peri_div40 is used by idle counter. Axi access is used as the reset signal to clear idle counter, thus there will be a margin of error (0 ~ +1us).

Registers

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Operation Flow

Shutdown DQ pads’ rx path when idle

The flow of dynamically shutdown DQ pads’ rx path is shown below.

Power down DQ pads and disable psram_phy

The flow of power down DQ pads and disable psram_phy is shown below.

Top Level Interface

The psram_axi_clutch interface is listed below.

Port Name	I/O	Description
Global Signals	Global Signals	Global Signals
clk		Psram axi clock
rst_n		Rstn generated at psram_clk domain
xtal_peri		Xtal 40M clock
xtal_ck1m		Xtal 1M clock, from hs_timer xtal_div40
Register	Register	Register
rw_pwdpad_dq_en	I	high active, enable to shutdown DQ pads when idle
rw_pwdpad_idle_val[8:0]	I	idle counter setting, unit: 1us
rw_pwdpad_resume_val[4:0]	I	dq pads resume counter setting, unit: psram_clk period
AXI Signals	AXI Signals	AXI Signals
…
Control Signals	Control Signals	Control Signals
psram_pad_pwd	O	High active, control DQ pads’ PD input

Design Implementation

Idle counter

We use xtal_peri (40M) instead of xtal_ck1m for idle_rst releasing, xtal_ck1m is the generated clock from xtal_peri and STA will check the paths between these two clocks.

idle counter control logic

FSM

psram_axi_clutch state machine

psram_axi_clutch FSM state description is shown below.

State Name	Description
IDLE	Check whether psram_auto_axi has access, axi signals go-through
ACTIVE	Psram_auto_axi has access, axi signals go-through
STOP	Shutdown psram DQ pads after idle counter reaching rw_pwdpad_idle_val
RESUME	Delay enough cycles for DQ pads resuming

Waveform

psram_axi_clutch entering STOP state

psram_axi_clutch resume

Corner Case and Exception

Design Flow Notes

Negedge clock.

Internal clock or reset.

Clock mux or clock gate.

False path or multcycle path.

Items to pay attention to in FPGA flow.