LS_SDM

Introduction

SDM is a module to generate a high precision 32.768kHz clock output. The frequency of SDM’s source clock should be about 4 times of the frequency of output clock. The frequency of source clock cannot be precise at 4 times of 32.768kHz, SDM will calculate the error of source clock and calibrate the output clock. The principle of SDM calibration is that the module calculates the source clock error and compensates the error on the output clock. However, the SDM guarantees the output clock’s precision only after the calibration and source clock do not change anymore. If the source clock changes after calibration, the output clock will change accordingly, and error will be induced to the output clock.

Features

• Precise 32.768kHz output, less than 11.6ppm error rate

• Input clock precision tolerance

• Always do calibration function supported

• Timer-trigger calibration works when long time no calibration done event in active mode

• Timer-trigger calibration can also work in sleep mode and deep-sleep mode

• Always calibration can work together with timer-trigger calibration

Functional Description

Block Diagram

The block diagram of SDM is illustrated below.

The SDM module is designed for 32.768kHz clock generation. It includes the following sub-modules:

• Register interface

  • Used for SDM configuration

  • Can set the timer-trigger calibration

  • Timer-trigger calibration and always calibration can be enabled at the same time.

• Calibration

  • Uses XTAL clock as the precise clock

  • Samples 131k source clock for a period of time

  • Calculates source clock error compared to 131.072kHz

  • Generates calibration done event and cps_loss for 32.768k generation module

  • If the XTAL is power off and timer-trigger calibration triggers, SDM will request to power on XTAL and do calibration.

  • Each time calibration done event will clear the timer.

• cps32k_gen

  • Four divided source clock

  • Uses cps_loss and high_128k signal to compensate output clock to 32.768kHz

  • Accumulates cps_loss when the sum of error is greater than one clock cycle and adds/masks one clock cycle to compensate the error, the add or mask is decided by high_128k.

  • If the source clock equals to 131.072kHz, the output clock is four divided.

The block diagrams of sub-modules of calibration is summaried below.

The block diagrams of sub-modules of cps32K_gen is summaried below.

Registers

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730E

Base Address: 0x41009000

Name	Address offset	Access	Description
REG_SDM_CTRL0	000h	R/W	Config SDM mode select and calibration mode
REG_SDM_CTRL1	004h	R/W	Config sample 128k cycles,when use user define mode
REG_SDM_CTRL2	008h	R/W	Set XTAL clock reference counter value register,when use user define mode
REG_SDM_CTRL3	00Ch	R/W	Config XTAL clock period,when use user define mode
REG_SDM_CTRL4	010h	R/W	SDM debug register
REG_SDM_CTRL5	014h	R/W	Set 32k clock cycle error,when use user define mode,time loss can be config,this reg config time los s,
REG_SDM_TIMEOUT	01Ch	R/W	Timer trigger counter value,when timeout wakeup XTAL clock
REG_SDM_DUMMY	020h	R/W	Dummy register

REG_SDM_CTRL0

• Name : SDM Control Register

• Size : 32

• Address offset : 000h

• Read/write access : R/W

Config SDM mode select and calibration mode

Bit	Symbol	Access	Reset	Description
31	SDM_EN	R/W	0	Enable SDM
30	SDM_RST	R/W	0	0: Reset SDM
29	SDM_BYPASSS_MOD_EN	R/W	0	Bypass mode enable
28	SDM_MOD_SEL	R/W	0	0: Default mode 1: User-defined parameter mode
27	CAL_DONE	R	0
26	RSVD	R	-	Reserved
25	TIME_LOSS_SET	R/W	0	Time loss set 1: User-defined
24	TIME_LOSS_HIGH	R/W	0	Decide 32k output compensation direction 1: Mask 0: Add
23:19	RSVD	R	-	Reserved
18	ALWAYS_CAL_EN	R/W	0	1: Enable always_cal
17	TIMER_CAL_EN	R/W	0	1: Enable timer_cal
16:12	RSVD	R	-	Reserved
11:8	XTAL_SEL	R/W	0	XTAL frequency select, default 40M 4’h0: XTAL40M 4’h1: XTAL25M 4’h4: XTAL20M 4’h5: XTAL26M 4’hD: XTAL27M 4’hE: XTAL24M
7:0	RSVD	R	-	Reserved

REG_SDM_CTRL1

• Name : Config observed 128K cycle

• Size : 32

• Address offset : 004h

• Read/write access : R/W

Config sample 128k cycles,when use user define mode

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	SDM_OBS_CYC	R/W	0	Set observed 128k cycle, default 1024 128k cycles

REG_SDM_CTRL2

• Name : Set ref counter value

• Size : 32

• Address offset : 008h

• Read/write access : R/W

Set XTAL clock reference counter value register,when use user define mode

Bit	Symbol	Access	Reset	Description
31:0	SDM_OBS_REF_CYC	R/W	0	Set in observed cycles, refer to counters value, default 312 500 XTAL cycles

REG_SDM_CTRL3

• Name : Set XTAL period

• Size : 32

• Address offset : 00Ch

• Read/write access : R/W

Config XTAL clock period,when use user define mode

Bit	Symbol	Access	Reset	Description
31:0	XTAL_PERIOD	R/W	0	Set reference xtal period (ns)

REG_SDM_CTRL4

• Name : SDM Debug Register

• Size : 32

• Address offset : 010h

• Read/write access : R/W

SDM debug register

Bit	Symbol	Access	Reset	Description
31:4	RSVD	R	-	Reserved
3	SDM_DBG_EN	R/W	0	1: Enable SDM debug
2:0	SDM_DBG_SEL	R/W	0	Set in observed cycles, refer to counters value

REG_SDM_CTRL5

• Name : Time loss Set

• Size : 32

• Address offset : 014h

• Read/write access : R/W

Set 32k clock cycle error,when use user define mode,time loss can be config,this reg config time los

s,

Bit	Symbol	Access	Reset	Description
31:0	TIME_LOSS_REG	R/W	0	Source clock time loss every cycle

REG_SDM_TIMEOUT

• Name : Set Timer Trigger Counter Value

• Size : 32

• Address offset : 01Ch

• Read/write access : R/W

Timer trigger counter value,when timeout wakeup XTAL clock

Bit	Symbol	Access	Reset	Description
31:0	TIMEOUT_CNT	R/W	2000000h	Set SDM timer trigger calibration timeout value

REG_SDM_DUMMY

• Name : SDM Dummy Register

• Size : 32

• Address offset : 020h

• Read/write access : R/W

Dummy register

Bit	Symbol	Access	Reset	Description
31:0	DUMMY	R/W	ffffh	Dummy register

Top Level

SDM top module important interface are:

• Register access interface

• RTC interface

SDM Interface

The interface for SDM top is shown below.

The SDM interface is listed below.

Port name	Width	I/O	Clock domain	Description
clk	1 bit	I		System register clock
rst_n	1 bit	I	clk	System register reset
reg_addr	6 bits	I	clk	Address for internal register interface
reg_wdata	32 bits	I	clk	Data for internal register interface
reg_rdata	32 bits	O	clk	Data output for internal register interface
reg_we	32 bits	I	clk
reg_wr	1 bit	I	clk
reg_rd	1 bit	I	clk
reg_rdy	1 bit	I	clk
hs_wdg_fen	1 bit	I	clk_128k_src	watchdog fen signal
sdm_cal_done	1 bit	O	clk_128k_src	SDM calibration done
Xtal_valid	1 bit	I	async	Crystal clock is valid to use
Xtal_req	1 bit	O	clk_128k_src	Request for resume crystal clock
Xtal_valid_ack	1 bit	O	clk_128k_src	xtal_valid ack signal
Xtal_clk	1 bit	I		Crystal clock
clk_128k_src	1 bit	I		Source clock
rstn_128k_src	1 bit	I
clk_32k	1 bit	O		32.768k Output clock
dbg_ls_sdm	32 bits	O	clk_128k_src	Debug port
SCAN_MODE	1 bit	I		Scan mode
SCAN_EN	1 bit	I		Scan enable

The debug interface is listed below.

Sdm_dbg_sel_i	Bit field	dbg_o function
3’h0	[5:0]	Addr
3’h0	[6]	Rstn
3’h0	[7]	Clk_d
3’h0	[11:8]	write
3’h0	[12]	Xtal_clk_d
3’h0	[13]	Xtal_valid_reg
3’h0	[14]	Xtal_valid
3’h1	[31:0]	data_in
3’h2	[31:0]	data_out
3’h3	[0]	dbg_cps_cycle
3’h3	[2:1]	dbg_clk_128k_cnt
3’h3	[3]	div_go_pos_p
3’h3	[4]	cal_done
3’h3	[5]	obs_128k_done
3’h3	[6]	eq_128k_sync
3’h3	[7]	bypass_moode_128k
3’h3	[8]	rstn_128k
3’h3	[9]	ctal_rstn_reg
3’h3	[10]	clk_32k
3’h3	[11]	clk_128k_src_d
3’h3	[15:12]	ctal_sel_internal
3’h3	[31:16]	obs_cycle
3’h4	[31:0]	xtal_period
3’h5	[31:0]	obs_ref_cnt
3’h6	[0]	re_calibration
3’h6	[1]	xtal_valid_reg
3’h6	[2]	xtal_req_reg
3’h6	[10]	timer_cal_en_reg
3’h6	[13]	sdm_cal_done
3’h6	[14]	power_latch_en
3’h6	[15]	cal_done_pl
3’h6	[16]	eq_128k_pl
3’h6	[17]	xtal_rstn
3’h6	[18]	eq_128k_pl

Design Implementation

Clock Domain

Reg Interface

Write timing:

Read timing:

Calibration Principle

Calibration is using sigma-delta method to compensate output 32.768kHz clock. There is one counter in source clock domain count in nearly 131.072kHz, another in XTAL clock count in XTAL clock frequency. as shown in formula:

\[\mathrm{src\_{clk}}_{period} \times \mathrm{obs\_{cycles}\_{ref}} = \mathrm{xtal\_{clk}}_{period} \times \mathrm{obs\_{ref}\_{cnt}}\]

Design have set parameter for that if the source clock is equal to 131.072kHz, the XTAL clock counter will equal the set parameter when source clock counter finished. If the source clock is not equal to 131.072kHz, when source clock counter finished, XTAL clock will be different to parameter, so the difference between the XTAL clock counter and parameter will be the source clock error. Formula is as follows:

\[\mathrm{source\_{clk}\ error} = \sum_{0}^{N - \mathrm{obs\_{ref}\_{cnt}}} \mathrm{xtal\_{clk}}_{\mathrm{period}}\]

In the formula, N is the obs_ref_cnt calculated when source clock is 131.072k. Use this error we can get cycle error of 32k output clock.

\[\mathrm{32k\_{cycle}\_{error}} = \frac{\mathrm{source\ clock\ error}}{\mathrm{obs\_{cycles}\_{ref}}} \times 4\]

Accumulate the error every output cycle,

\[\mathrm{acc\_{error}} = \sum \mathrm{32k\_{cycle}\_{error}}\]

when the accumulated acc_error is greater than one source clock cycle, then compensate one source clock cycle. If source clock is greater than 131.072kHz, then compensate should be mask one clock cycle, on the contrary, the compensate will add one cycle. The 32K output flow is as shown below.

The calibration time formula is as follows:

\[\mathrm{cal\_{time}} = \left( \frac{1000000000}{131072} \right) \times \mathrm{obs\_{cycles}\_{ref}}\]

The example of SDM calibration time is shown below.

XTAL_FREQ (MHz)	Cal_time (ms)	Obs_cycles_ref
40	7.8125	1024
25	15.625	2048
20	7.8125	1024
26	18.55469	2432
27	18.06641	2368
24	20.50781	2688

Timer Trigger Calibration

The timer trigger function has always existed and is used in combination with ALWAYS calibration. Timer trigger counts all the time. The timer trigger counter will be cleared to zero after each calibration done. When the system is in low-power state, XTAL clock domain is clock gated, and the timer counter value is timeout, an XTAL request signal will be generate and sent to the PMC to wakeup XTAL clock, and the request signal is also used to inform the SDM itself that it is ready for calibration. When the XTAL clock is stable, the valid signal will be sent to SDM. Then one calibration will start,when the posedge of xtal_valid is active in the 32k_clk domain,clear the XTAL request signal.

Timer counter block is as shown below.

When using Timer trigger calibration function, the block diagram for SDM/PMC connection is as shown below.

Handshake signal between SDM and PMC

Always Calibration

If always calibration function is enabled, the SDM will always do calibration when previous calibration is finished. This function needs XTAL clock always not gated.

32K Output Deviation

When the output 32K cycle error accumulates greater than 131.072K cycle, a 128k source cycle is compensated for the output 32K period. Error measurement method is as follows: Sampling the 32K cycles between compensations and counting the period of output 32K, the output precision of 32K can be calculated according to the theoretical 32K period. Formula is as follows:

\[\mathrm{deviation} = \frac{4 * N - 1}{4N} * \frac{131072}{128K} - 1\]

In the formula, N is the number of cycles of 32K sampling, and 128K is the source clock.

Calibration Done Timing

Operation Flow

The following steps are operation flow of SDM.

1. Enable source 131.072K clock and XTAL clock

2. Enable SDM (SDM_EN&SDM_RST), it will do calibration when enabled

3. Set the Timer Trigger-calibration timer counter

4. Enable Always calibration and Timer Trigger-calibration

Corner Case and Exception

• Before configuring SDM, you need to open SDM clock source 131k, set 0x4800_002C[13:8]=0x21, select 131.29kHz, bit[0] enables 131k output.

• When 131K software clock after calibration, the boot process needs to do 131K calibration, and then write the result of calibration to 0x4800_002C[13:8], and set 0x4800_002C=1 enable 131k output. Then do the SDM configuration.

• Boot process SDM will make a calibration, XTAL40MHz SDM calibration once need 8ms, must ensure that the calibration is complete, can do into low power operation, try to put the SDM configuration process to the front of the boot, to avoid doing into low power operation but the first calibration is not completed.

• Timer calibration timeout is 1~2ms longer than calibration time. And the calibration almost done when system goes to sleep or deepsleep. In this case, the SDM will request Xtal very near to PMC close Xtal. This will cause PMC hang. SW should avoid configure time calibration timeout less than 10ms(usually, it will configured to more than 1minutes)