PWM 定时器
功能特性
向上计数的 16 位计数器
自动重载寄存器的值可以预加载
内部有 16 位的分频寄存器
每个通道可以独立产生 PWM 波形
可以产生的中断类型:
计数器溢出中断
软件更新事件中断
通道的计数器溢出中断
通道的捕获/比较中断
三种工作模式
PWM 模式:用于生成占空比和周期可配置的方波
输入捕获功能:用于捕获输入引脚上升沿/下降沿时计数器的数值
单脉冲模式:用于检测到输入引脚的上升沿/下降沿/边沿后,在可编程延迟后产生一个具有可编程的脉冲。
应用示例
SDK 提供了两类功能示例,帮助开发者了解和使用 PWM 定时器功能:
mbed 示例
路径:
{SDK}\example\peripheral\mbed\Timer\mbed_pwm展示如何在 mbed 环境中实现 PWM 定时器控制
raw 示例
路径:
{SDK}\example\peripheral\raw\Timer\{demo}展示如何在无抽象层的情况下直接控制 PWM 定时器
以下是对 raw 示例功能的简要说明:
raw_pwm 演示如何使用 PWM 模式。
raw_tim_capture_pwm_32k 演示如何使用 PWM 输入捕获功能。
raw_tim_pwm_one_pulse 演示如何使用 PWM 单脉冲模式。
备注
要了解示例支持的芯片,请查看示例路径下的 README.md 文件。
API
Raw API
PWMTIMER Exported Types
-
struct TIM_CCInitTypeDef
TIM Output Compare Init Structure Definition.
Public Members
-
u32 TIM_CCMode
Specifies the CC timer mode. This parameter can be a value of TIM_CCMode_PWM or TIM_CCMode_Inputcapture.
-
u32 TIM_CCPolarity
Specifies the polarity. This parameter can be TIM_CCPolarity_High/TIM_CCPolarity_Low. If CCx channel is configured as output: TIM_CCPolarity_High means OCx active high. TIM_CCPolarity_Low means OCx active low. If CCx channel is configured as input: TIM_CCPolarity_High means positive edge of TRGI is active for capture. TIM_CCPolarity_Low means negative edge of TRGI is active for capture.
-
u32 TIM_OCProtection
Output Compare value update protection. TIM_OCPreload_Enable/TIM_OCPreload_Disable. TIM_OCPreload_Enable means duty cycle will update when UEV happens if write to CCRx field in TIMx_CCRX. TIM_OCPreload_Disable means duty cycle will update immediately if write to CCRx field in TIMx_CCRX.
-
u32 TIM_OCPulse
Specifies the output pulse value to be loaded into the CCRx Register, which decides the duty cycle. This parameter can be a number between 0x0000 and 0xFFFF.
-
u32 TIM_ICPulseMode
Specifies the pulse mode of TIM with pulse capability. This parameter can be TIM_CCMode_PulseWidth or TIM_CCMode_PulseNumber.
-
u32 TIM_CCMode
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
-
struct PWM1_DevTable
PWM dev Table Definition.
Public Members
-
RTIM_TypeDef *TIMx
Pointer to TIM peripheral register base address.
-
u32 Tx_HandshakeInterface
DMA TX handshake interface number.
-
RTIM_TypeDef *TIMx
-
struct TIM_AudInitTypeDef
TIM5 audio and motor Output mode Init Structure Definition.
Public Members
-
u32 TIM_IdleLevel
Specifies the PWM init output level. This parameter can be PWM_OUTPUT_LOW/PWM_OUTPUT_HIGH.
-
u32 TIM_AudBrkLevel
Specifies the PWM brake output level. This parameter can be PWM_OUTPUT_LOW/PWM_OUTPUT_HIGH.
-
u32 TIM_AudFIFOEmptyLevel
Specifies when fifo is empty PWM Output Level. This parameter can be PWM_OUTPUT_LOW/PWM_OUTPUT_HIGH.
-
u32 TIM_AudEmgBrk
Specifies ENABLE/DISABLE emergency brake fuction. This parameter can be ENABLE/DISABLE.
-
u32 TIM_AudEmgBrkLevel
Specifies after emergency brake PWM output level. This parameter can be PWM_EMGBRK_OUTPUT_LOW/PWM_EMGBRK_OUTPUT_HIGH.
-
u32 TIM_AudEmgBrkPol
Specifies after emergency brake trig polarity. This parameter can be PWM_EMGBRK_TRI_POL_HIHG/PWM_EMGBRK_TRI_POL_LOW.
-
u32 TIM_AudCCRSourceSel
Specifies the CCR data source select. This parameter can be PWM_CCR_SOURCE_CPU/PWM_CCR_SOURCE_FIFO.
-
u32 TIM_AudPolSel
Specifies channel1/3/5 polarity, for channel0/2/4 this parameter is invalid. This parameter can be PWM_POLARITY_OPPOSITE/PWM_POLARITY_SAME.
-
u32 TIM_AudChnNum
Specifies PWM channel 0/2/4 control 1 or 2 output pad, for channel1/3/5 this parameter is invalid. This parameter can be PWM_CHANNEL_OUTPUT_ONEPAD/PWM_CHANNEL_OUTPUT_TWOPAD.
-
u32 TIM_AudDeadZoneEn
Specifies deadzone statue. This parameter can be DISABLE/ENABLE
-
u32 TIM_AudDeadZoneTim
Specifies deadzone time. This parameter can be a number between 0x000 to 0x7FF.
-
u32 TIM_AudFIFOemptyMode
Specifies when fifo is empty PWM Output mode. This parameter can be PWM_FIFO_EMPTY_MAINTAIN/PWM_FIFO_EMPTY_BRAKE.
-
u32 TIM_IdleLevel
PWMTIMER Exported Constants
TIM Capture Compare Control
/* Enable the Capture/Compare channel output. */
#define TIM_CCx_Enable ((u32)0x01000000)
/* Disable the Capture/Compare channel output. */
#define TIM_CCx_Disable ((u32)0x00000000)
/* Check if CCx enable/disable value is valid. */
#define IS_TIM_CCX (((CCX) == TIM_CCx_Enable) || ((CCX) == TIM_CCx_Disable))
/* Enable output compare preload register on CCRx. */
#define TIM_OCPreload_Enable ((u32)0x02000000)
/* Disable output compare preload register on CCRx. */
#define TIM_OCPreload_Disable ((u32)0x00000000)
/* Check if output compare preload state value is valid. */
#define IS_TIM_OCPRELOAD_STATE (((STATE) == TIM_OCPreload_Enable) || \
((STATE) == TIM_OCPreload_Disable))
/* if input is set : Positive edge of TRGI is active for capture */
#define TIM_CCPolarity_High ((u32)0x00000000)
/* if input is set : negative edge of TRGI is active for capture */
#define TIM_CCPolarity_Low ((u32)0x04000000)
/* Check if CC polarity value is valid. */
#define IS_TIM_CC_POLARITY (((POLARITY) == TIM_CCPolarity_High) || \
((POLARITY) == TIM_CCPolarity_Low))
/* CC channel configured as PWM output mode. */
#define TIM_CCMode_PWM ((u32)0x00000000)
/* CC channel configured as input capture mode. */
#define TIM_CCMode_Inputcapture ((u32)0x08000000)
/* Check if CC mode value is valid. */
#define IS_TIM_CC_MODE (((MODE) == TIM_CCMode_PWM) || \
((MODE) == TIM_CCMode_Inputcapture))
TIM CC Event Source
/* Event source: Capture/Compare channel 0 event. */
#define TIM_EventSource_CC0 ((u32)0x00000002)
/* Event source: Capture/Compare channel 1 event. */
#define TIM_EventSource_CC1 ((u32)0x00000004)
/* Event source: Capture/Compare channel 2 event. */
#define TIM_EventSource_CC2 ((u32)0x00000008)
/* Event source: Capture/Compare channel 3 event. */
#define TIM_EventSource_CC3 ((u32)0x00000010)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
/* Event source: Capture/Compare channel 6 event. */
#define TIM_EventSource_CC6 ((u32)0x00000080)
/* Event source: Capture/Compare channel 7 event. */
#define TIM_EventSource_CC7 ((u32)0x00000100)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
/* Event source: Capture/Compare channel 6 event. */
#define TIM_EventSource_CC6 ((u32)0x00000080)
/* Event source: Capture/Compare channel 7 event. */
#define TIM_EventSource_CC7 ((u32)0x00000100)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
/* Event source: Capture/Compare channel 6 event. */
#define TIM_EventSource_CC6 ((u32)0x00000080)
/* Event source: Capture/Compare channel 7 event. */
#define TIM_EventSource_CC7 ((u32)0x00000100)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
/* Event source: Capture/Compare channel 6 event. */
#define TIM_EventSource_CC6 ((u32)0x00000080)
/* Event source: Capture/Compare channel 7 event. */
#define TIM_EventSource_CC7 ((u32)0x00000100)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
/* Event source: Capture/Compare channel 6 event. */
#define TIM_EventSource_CC6 ((u32)0x00000080)
/* Event source: Capture/Compare channel 7 event. */
#define TIM_EventSource_CC7 ((u32)0x00000100)
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
Not supported.
/* Event source: Capture/Compare channel 4 event. */
#define TIM_EventSource_CC4 ((u32)0x00000020)
/* Event source: Capture/Compare channel 5 event. */
#define TIM_EventSource_CC5 ((u32)0x00000040)
TIM Channel
/* Timer channel 0 index. */
#define TIM_Channel_0 ((u16)0x0000)
/* Timer channel 1 index. */
#define TIM_Channel_1 ((u16)0x0001)
/* Timer channel 2 index. */
#define TIM_Channel_2 ((u16)0x0002)
/* Timer channel 3 index. */
#define TIM_Channel_3 ((u16)0x0003)
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Timer channel 6 index. */
#define TIM_Channel_6 ((u16)0x0006)
/* Timer channel 7 index. */
#define TIM_Channel_7 ((u16)0x0007)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Timer channel 6 index. */
#define TIM_Channel_6 ((u16)0x0006)
/* Timer channel 7 index. */
#define TIM_Channel_7 ((u16)0x0007)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Timer channel 6 index. */
#define TIM_Channel_6 ((u16)0x0006)
/* Timer channel 7 index. */
#define TIM_Channel_7 ((u16)0x0007)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Timer channel 6 index. */
#define TIM_Channel_6 ((u16)0x0006)
/* Timer channel 7 index. */
#define TIM_Channel_7 ((u16)0x0007)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Timer channel 6 index. */
#define TIM_Channel_6 ((u16)0x0006)
/* Timer channel 7 index. */
#define TIM_Channel_7 ((u16)0x0007)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5))
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3))
/* Timer channel 4 index. */
#define TIM_Channel_4 ((u16)0x0004)
/* Timer channel 5 index. */
#define TIM_Channel_5 ((u16)0x0005)
/* Check if channel index is a valid timer channel. */
#define IS_TIM_CHANNEL (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5))
TIM Default Level
/* PWM one-pulse default output level: high. */
#define TIMPWM_DefaultLevel_High ((u32)0x00000000)
/* PWM one-pulse default output level: low. */
#define TIMPWM_DefaultLevel_Low ((u32)0x00000001)
/* Check if default level value is valid. */
#define IS_TIMPWM_DefaultLevel (((LEVEL) == TIMPWM_DefaultLevel_High) || ((LEVEL) == TIMPWM_DefaultLevel_Low))
TIM Interrupt Control
/* Timer counter update interrupt flag. */
#define TIM_IT_Update ((u32)0x00000001)
/* Capture/Compare channel 0 interrupt flag. */
#define TIM_IT_CC0 ((u32)0x00000002)
/* Capture/Compare channel 1 interrupt flag. */
#define TIM_IT_CC1 ((u32)0x00000004)
/* Capture/Compare channel 2 interrupt flag. */
#define TIM_IT_CC2 ((u32)0x00000008)
/* Capture/Compare channel 3 interrupt flag. */
#define TIM_IT_CC3 ((u32)0x00000010)
/* Channel 0 update interrupt enable flag. */
#define TIM_IT_UIE0 ((u32)0x00010000)
/* Channel 1 update interrupt enable flag. */
#define TIM_IT_UIE1 ((u32)0x00020000)
/* Channel 2 update interrupt enable flag. */
#define TIM_IT_UIE2 ((u32)0x00040000)
/* Channel 3 update interrupt enable flag. */
#define TIM_IT_UIE3 ((u32)0x00080000)
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Capture/Compare channel 6 interrupt flag. */
#define TIM_IT_CC6 ((u32)0x00000080)
/* Capture/Compare channel 7 interrupt flag. */
#define TIM_IT_CC7 ((u32)0x00000100)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Channel 6 update interrupt enable flag. */
#define TIM_IT_UIE6 ((u32)0x00400000)
/* Channel 7 update interrupt enable flag. */
#define TIM_IT_UIE7 ((u32)0x00800000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFF00FE00) == 0x0000) && (((IT) & (u32)0xFF01FF) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5) || \
((IT) == TIM_IT_UIE6) || \
((IT) == TIM_IT_UIE7))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Capture/Compare channel 6 interrupt flag. */
#define TIM_IT_CC6 ((u32)0x00000080)
/* Capture/Compare channel 7 interrupt flag. */
#define TIM_IT_CC7 ((u32)0x00000100)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Channel 6 update interrupt enable flag. */
#define TIM_IT_UIE6 ((u32)0x00400000)
/* Channel 7 update interrupt enable flag. */
#define TIM_IT_UIE7 ((u32)0x00800000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFF00FE00) == 0x0000) && (((IT) & (u32)0xFF01FF) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5) || \
((IT) == TIM_IT_UIE6) || \
((IT) == TIM_IT_UIE7))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Capture/Compare channel 6 interrupt flag. */
#define TIM_IT_CC6 ((u32)0x00000080)
/* Capture/Compare channel 7 interrupt flag. */
#define TIM_IT_CC7 ((u32)0x00000100)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Channel 6 update interrupt enable flag. */
#define TIM_IT_UIE6 ((u32)0x00400000)
/* Channel 7 update interrupt enable flag. */
#define TIM_IT_UIE7 ((u32)0x00800000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFF00FE00) == 0x0000) && (((IT) & (u32)0xFF01FF) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5) || \
((IT) == TIM_IT_UIE6) || \
((IT) == TIM_IT_UIE7))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Capture/Compare channel 6 interrupt flag. */
#define TIM_IT_CC6 ((u32)0x00000080)
/* Capture/Compare channel 7 interrupt flag. */
#define TIM_IT_CC7 ((u32)0x00000100)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Channel 6 update interrupt enable flag. */
#define TIM_IT_UIE6 ((u32)0x00400000)
/* Channel 7 update interrupt enable flag. */
#define TIM_IT_UIE7 ((u32)0x00800000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFF00FE00) == 0x0000) && (((IT) & (u32)0xFF01FF) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5) || \
((IT) == TIM_IT_UIE6) || \
((IT) == TIM_IT_UIE7))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Capture/Compare channel 6 interrupt flag. */
#define TIM_IT_CC6 ((u32)0x00000080)
/* Capture/Compare channel 7 interrupt flag. */
#define TIM_IT_CC7 ((u32)0x00000100)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Channel 6 update interrupt enable flag. */
#define TIM_IT_UIE6 ((u32)0x00400000)
/* Channel 7 update interrupt enable flag. */
#define TIM_IT_UIE7 ((u32)0x00800000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFF00FE00) == 0x0000) && (((IT) & (u32)0xFF01FF) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5) || \
((IT) == TIM_IT_UIE6) || \
((IT) == TIM_IT_UIE7))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFFC0FF80) == 0x0000) && (((IT) & (u32)0x3F007F) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5))
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFFF0FFE0) == 0x0000) && (((IT) & (u32)0xF001F) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3))
/* Capture/Compare channel 4 interrupt flag. */
#define TIM_IT_CC4 ((u32)0x00000020)
/* Capture/Compare channel 5 interrupt flag. */
#define TIM_IT_CC5 ((u32)0x00000040)
/* Channel 4 update interrupt enable flag. */
#define TIM_IT_UIE4 ((u32)0x00100000)
/* Channel 5 update interrupt enable flag. */
#define TIM_IT_UIE5 ((u32)0x00200000)
/* Check if interrupt source bitmask is valid. */
#define IS_TIM_IT ((((IT) & (u32)0xFFC0FF80) == 0x0000) && (((IT) & (u32)0x3F007F) != 0x0000))
/* Check if a single interrupt source value is valid. */
#define IS_TIM_GET_IT (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_UIE0) || \
((IT) == TIM_IT_UIE1) || \
((IT) == TIM_IT_UIE2) || \
((IT) == TIM_IT_UIE3) || \
((IT) == TIM_IT_UIE4) || \
((IT) == TIM_IT_UIE5))
TIM OPM Control
/* External trigger polarity: positive edge active. */
#define TIM_OPMode_ETP_positive ((u32)0x00000000)
/* External trigger polarity: negative edge active. */
#define TIM_OPMode_ETP_negative ((u32)0x00000100)
/* External trigger polarity: both edges active. */
#define TIM_OPMode_ETP_bothedge ((u32)0x00000200)
/* Check if external trigger polarity mode is valid. */
#define IS_TIM_OPM_ETP_MODE (((MODE) == TIM_OPMode_ETP_positive) || \
((MODE) == TIM_OPMode_ETP_negative) || \
((MODE) == TIM_OPMode_ETP_bothedge))
/* One-pulse mode: counter stops at next update event. */
#define TIM_OPMode_Single ((u32)0x00000008)
/* Repetitive (PWM) mode: counter does not stop at next update event. */
#define TIM_OPMode_Repetitive ((u32)0x00000000)
/* Check if one-pulse operation mode value is valid. */
#define IS_TIM_OPM_MODE (((MODE) == TIM_OPMode_Single) || \
((MODE) == TIM_OPMode_Repetitive))
TIM Phase Sync Control
/* Phase sync direction: channel delays behind reference counter. */
#define TIMPWM_PSync_Delay ((u32)0x00000000)
/* Phase sync direction: channel leads ahead of reference counter. */
#define TIMPWM_PSync_Ahead ((u32)0x00000001)
/* Check if phase sync direction value is valid. */
#define IS_TIMPWM_PSync_Dir (((DIR) == TIMPWM_PSync_Delay) || ((DIR) == TIMPWM_PSync_Ahead))
/* Enable phase sync parameter preload register. */
#define TIMPWM_PSyncPreload_Enable ((u32)0x00000000)
/* Disable phase sync parameter preload register. */
#define TIMPWM_PSyncPreload_Disable ((u32)0x00000001)
/* Check if phase sync preload state value is valid. */
#define IS_TIMPWM_PPRELOAD_STATE (((STATE) == TIMPWM_PSyncPreload_Enable) || \
((STATE) == TIMPWM_PSyncPreload_Disable))
TIM PWM Type
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM9) || \
((PERIPH) == TIM8_S) || \
((PERIPH) == TIM9_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM8) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM8) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S) || \
((PERIPH) == TIM8_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM7) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S) || \
((PERIPH) == TIM7_S))
/* Check if peripheral is a one-pulse capable timer. */
#define IS_TIM_ONE_PULSE_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S))
/* Check if peripheral is a capture/compare mode timer. */
#define IS_TIM_CCM_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM6) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S) || \
((PERIPH) == TIM6_S))
/* Check if peripheral is a PWM output timer. */
#define IS_TIM_PWM_TIM (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIM4_S) || \
((PERIPH) == TIM5_S))
/* Check if peripheral is the audio/motor PWM timer. */
#define IS_PWM_TIM5 (((PERIPH) == TIM5) || \
((PERIPH) == TIM5_S))
PWM AUD Channel
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
/* PWM audio/motor channel 0 index. */
#define PWM_AUD_Channel_0 ((u16)0x0000)
/* PWM audio/motor channel 1 index. */
#define PWM_AUD_Channel_1 ((u16)0x0001)
/* PWM audio/motor channel 2 index. */
#define PWM_AUD_Channel_2 ((u16)0x0002)
/* PWM audio/motor channel 3 index. */
#define PWM_AUD_Channel_3 ((u16)0x0003)
/* PWM audio/motor channel 4 index. */
#define PWM_AUD_Channel_4 ((u16)0x0004)
/* PWM audio/motor channel 5 index. */
#define PWM_AUD_Channel_5 ((u16)0x0005)
/* Check if value is a valid PWM AUD channel index (0-5). */
#define IS_PWM_AUD_CHANNEL (((CHANNEL) == PWM_AUD_Channel_0) || \
((CHANNEL) == PWM_AUD_Channel_1) || \
((CHANNEL) == PWM_AUD_Channel_2) || \
((CHANNEL) == PWM_AUD_Channel_3) || \
((CHANNEL) == PWM_AUD_Channel_4) || \
((CHANNEL) == PWM_AUD_Channel_5))
PWM Audio and Motor Control
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
/* PWM idle/brake output level: low. */
#define PWM_OUTPUT_LOW ((u32)0x00000000)
/* PWM idle/brake output level: high. */
#define PWM_OUTPUT_HIGH ((u32)0x00000001)
/* Emergency brake PWM output level: low. */
#define PWM_EMGBRK_OUTPUT_LOW ((u32)0x00000000)
/* Emergency brake PWM output level: high. */
#define PWM_EMGBRK_OUTPUT_HIGH ((u32)0x00000004)
/* Emergency brake trigger polarity: high level active. */
#define PWM_EMGBRK_TRI_POL_HIHG ((u32)0x00000000)
/* Emergency brake trigger polarity: low level active. */
#define PWM_EMGBRK_TRI_POL_LOW ((u32)0x04000000)
/* CCR data source: CPU register write. */
#define PWM_CCR_SOURCE_CPU ((u32)0x00000000)
/* CCR data source: FIFO. */
#define PWM_CCR_SOURCE_FIFO ((u32)0x00000010)
/* Disable emergency brake function. */
#define PWM_EMGBRK_DISABLE ((u32)0x00000000)
/* Enable emergency brake function. */
#define PWM_EMGBRK_ENABLE ((u32)0x00000008)
/* Channel output phase: opposite to paired channel. */
#define PWM_POLARITY_OPPOSITE ((u32)0x00000000)
/* Channel output phase: same as paired channel. */
#define PWM_POLARITY_SAME ((u32)0x00000020)
/* Channel controls one output pad. */
#define PWM_CHANNEL_OUTPUT_ONEPAD ((u32)0x00000000)
/* Channel controls two output pads. */
#define PWM_CHANNEL_OUTPUT_TWOPAD ((u32)0x00000040)
/* Enable dead zone control. */
#define PWM_DeadzoneEn ((u32)0x00000080)
/* Disable dead zone control. */
#define PWM_DeadzoneDis ((u32)0x00000000)
/* FIFO empty mode: maintain last output data. */
#define PWM_FIFO_EMPTY_MAINTAIN ((u32)0x00000000)
/* FIFO empty mode: enter brake state. */
#define PWM_FIFO_EMPTY_BRAKE ((u32)0x00000100)
PWM Audio and Motor Interrupt Control
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
/* Interrupt status flag: FIFO empty event. */
#define TIM_IT_FIFO_EMPTY_FLAG ((u32)0x00000001)
/* Interrupt status flag: emergency brake release event. */
#define TIM_IT_EMG_BRK_RELEASE_FLAG ((u32)0x00000002)
/* Interrupt enable bit: FIFO empty interrupt. */
#define TIM_IT_FIFO_EMPTY ((u32)0x00000004)
/* Interrupt enable bit: emergency brake release interrupt. */
#define TIM_IT_EMG_BRK_RELEASE ((u32)0x00000008)
/* All audio/motor interrupt status flags combined. */
#define TIM_IT_AUD_ALL_FLAG (TIM_IT_FIFO_EMPTY_FLAG | TIM_IT_EMG_BRK_RELEASE_FLAG)
/* Check if value is a valid audio/motor interrupt status flag. */
#define IS_TIM_AUD_IT_FLAG (((IT) == TIM_IT_FIFO_EMPTY_FLAG) || ((IT) == TIM_IT_EMG_BRK_RELEASE_FLAG))
/* All audio/motor interrupt enable bits combined. */
#define TIM_IT_AUD_ALL (TIM_IT_FIFO_EMPTY | TIM_IT_EMG_BRK_RELEASE)
/* Check if value is a valid audio/motor interrupt enable bit. */
#define IS_TIM_AUD_IT (((IT) == TIM_IT_FIFO_EMPTY) || ((IT) == TIM_IT_EMG_BRK_RELEASE))
PWMTIMER Exported Functions
Capture Compare Management Functions
-
void RTIM_CCRxMode(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 TIM_CCMode)
Initialize the TIMx Channel CCmode.
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel -- The channel need to be set mode, which can be one of the following parameters TIM Channel.
TIM_CCMode --
CCx working mode which can be one of the following parameters:
TIM_CCMode_PWM
TIM_CCMode_Inputcapture
-
void RTIM_CCRxSet(RTIM_TypeDef *TIMx, u32 Compare, u16 TIM_Channel)
Set the TIMx Capture Compare X register value.
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
Compare -- The value specifies pulsewidth, which is in the 0x00~0xFFFF range. Duty cycle = Compare / (ARR+1).
TIM_Channel -- The channel to be set, which can be one of the following parameters TIM Channel.
备注
CCRx=0 will give 0% cycle pwm pulse.
CCRx>=TIM_Period there will be 100% pwm pulse.
-
void RTIM_CCStructInit(TIM_CCInitTypeDef *TIM_CCInitStruct)
Fill each TIM_CCInitStruct member with its default value.
- 参数:
TIM_CCInitStruct -- Pointer to a TIM_CCInitTypeDef structure which will be initialized.
-
void RTIM_CCxCmd(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 TIM_CCx)
Enable or disable the TIM Capture Compare Channel x.
- 参数:
TIMx -- The TIM peripheral with CCM capability. See IS_TIM_CCM_TIM macro.
TIM_Channel -- Specifies the TIM Channel This parameter can be one of the following values TIM Channel
TIM_CCx --
Specifies the TIM Channel CCxE bit new state. This parameter can be one of the following values:
TIM_CCx_Enable
TIM_CCx_Disable
-
void RTIM_CCxInit(RTIM_TypeDef *TIMx, TIM_CCInitTypeDef *TIM_CCInitStruct, u16 TIM_Channel)
Initialize the TIMx Channel according to the specified parameters in the TIM_CCInitStruct.
- 参数:
TIMx -- The TIM peripheral with CCM capability. See IS_TIM_CCM_TIM macro.
TIM_CCInitStruct -- Pointer to a TIM_CCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
TIM_Channel -- The channel need to be initialized, which can be one of the following parameters TIM Channel
-
void RTIM_CCxPolarityConfig(RTIM_TypeDef *TIMx, u32 TIM_OCPolarity, u16 TIM_Channel)
Configure the TIMx channel x polarity.
- 参数:
TIMx -- The TIM peripheral with CCM capability. See IS_TIM_CCM_TIM macro.
TIM_OCPolarity --
Specifies the OCx Polarity This parameter can be one of the following values:
TIM_CCPolarity_High: Output Compare active high
TIM_CCPolarity_Low: Output Compare active low
TIM_Channel -- Specifies the TIM Channel This parameter can be one of the following values TIM Channel
-
void RTIM_OCxPreloadConfig(RTIM_TypeDef *TIMx, u32 TIM_OCProtection, u16 TIM_Channel)
Enable or disable the TIMx peripheral Preload register on CCRx.
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_OCProtection --
New state of the TIMx peripheral Preload register This parameter can be one of the following values:
TIM_OCPreload_Enable: value is loaded in the active register at each update event.
TIM_OCPreload_Disable: new value is taken in account immediately
TIM_Channel -- The channel need to be set, which can be one of the following parameters TIM Channel
-
void RTIM_SetOnePulseDefaultLevel(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 DefaultLevel)
Set the TIMx's default level in one pulse mode.
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel -- The channel to be set, which can be one of the following parameters TIM Channel.
DefaultLevel --
Specifies the OPM Mode Default Level. This parameter can be one of the following values:
TIMPWM_DefaultLevel_High
TIMPWM_DefaultLevel_Low
备注
Takes effect only in PWM output mode's One-Pulse-Mode.
You must select TIM_OPMode_Single if you want to set One Pulse Mode, which makes the counter stop automatically at the next UEV.
-
void RTIM_SetOnePulseOutputMode(RTIM_TypeDef *TIMx, u32 TIM_OPMode, u32 TriggerPolarity)
Set the TIMx's One Pulse Mode (output one pulse PWM mode).
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_OPMode --
Specifies the OPM Mode to be used. This parameter can be one of the following values:
TIM_OPMode_Single
TIM_OPMode_Repetitive
TriggerPolarity --
Specifies the OPM Mode Trigger Polarity. This parameter can be one of the following values:
TIM_OPMode_ETP_positive
TIM_OPMode_ETP_negative
TIM_OPMode_ETP_bothedge
备注
You must select TIM_OPMode_Single if you want to set One Pulse Mode, which makes the counter stop automatically at the next UEV.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
-
u32 RTIM_IsChannelCaptureEnabled(RTIM_TypeDef *TIMx, u16 TIM_Channel)
Get the TIMx Channel inputcapture mode enabled or not.
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel -- Specifies the TIM Channel This parameter can be one of the following values TIM Channel
- 返回:
The capture enable status:
RTK_SUCCESS: Capture is enabled.
RTK_FAIL: Capture is not enabled.
Not supported.
Phase Sync Functions
-
u32 RTIM_GetChannelCountx(RTIM_TypeDef *TIMx, u16 TIM_Channel)
Get the TIMx Channel Counter value.
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel -- Specifies the TIM Channel This parameter can be one of the following values TIM Channel
- 返回:
Counter Register value.
-
void RTIM_PSyncxCmd(RTIM_TypeDef *TIMx, u16 TIM_Channel, u8 NewState)
Enable or disable the TIMx Phase Sync function.
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel -- Specifies the TIM Channel This parameter can be one of the following values TIM Channel
NewState -- ENABLE/DISABLE.
-
void RTIM_PSyncxDir(RTIM_TypeDef *TIMx, u16 TIM_Channel, u8 TIM_SyncDir)
Set the TIMx Phase Sync X direction.
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel -- The channel to be set, which can be one of the following parameters TIM Channel.
TIM_SyncDir -- TIMPWM_PSync_Delay/TIMPWM_PSync_Ahead
-
u32 RTIM_PSyncxGet(RTIM_TypeDef *TIMx, u16 TIM_Channel)
Get the TIMx Phase Sync X value.
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel -- The channel to be read, which can be one of the following parameters TIM Channel.
- 返回:
TIMx Phase Sync X value.
-
void RTIM_PSyncxPreloadConfig(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 TIM_PSyncProtection)
Enable or disable the preload function of TIMx phase sync register.
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel -- The channel need to be set, which can be one of the following parameters TIM Channel
TIM_PSyncProtection --
TIMPWM_PSyncPreload_Enable/TIMPWM_PSyncPreload_Disable
TIMPWM_PSyncPreload_Enable: value is loaded in the active register at each update event.
TIMPWM_PSyncPreload_Disable: new value is taken in account immediately
-
void RTIM_PSyncxSet(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 TIM_SyncPhase)
Set the TIMx Phase Sync X value.
- 参数:
TIMx -- The TIM peripheral with PWM output capability. See IS_TIM_PWM_TIM macro.
TIM_Channel -- The channel to be set, which can be one of the following parameters TIM Channel.
TIM_SyncPhase -- The phase sync value compared to CNT in TIM_CNT
备注
TIM_SyncPhase should always smaller than ARR value
Audio and Motor Functions
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
Not supported.
-
void PWM_DmaBurstSize(RTIM_TypeDef *TIMx, u32 msize)
Set DMA burstsize = 2^(n+1).
- 参数:
TIMx -- TIMx: where x only can be 5.
msize -- Burstsize = 2^(n+1) it can be one of the GDMA Msize values.
备注
PWM burstsize must be same as GDMA burstsize.
-
void PWM_DmaCmd(RTIM_TypeDef *TIMx, u32 NewState)
PWM and GDMA handshake on or off.
- 参数:
TIMx -- TIMx: where x only can be 5.
NewState -- New state of the handshake of GDMA-PWM. This parameter can be: ENABLE or DISABLE.
-
bool PWM_TXGDMA_Init(u32 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTXData, u32 Length)
Initialize GDMA peripheral.
- 参数:
Index --
GDMA_InitStruct -- Pointer to a GDMA_InitTypeDef structure that contains the configuration information for the GDMA peripheral.
CallbackData -- GDMA callback data.
CallbackFunc -- GDMA callback function.
pTXData -- TX Buffer.
Length -- TX Count.
- 返回:
The initialization result:
TRUE: Initialize successfully.
FALSE: Initialize failed.
-
void RTIM_AudStructInit(TIM_AudInitTypeDef *TIM_AudInitStruct)
Fill each TIM_AudInitStruct member with its default value.
- 参数:
TIM_AudInitStruct -- Pointer to a TIM_AudInitTypeDef structure which will be initialized.
-
void RTIM_AudioandMotorINTClear(RTIM_TypeDef *TIMx)
Clear the TIM5's audio and motor interrupt bits.
- 参数:
TIMx -- Where x only can be 5.
-
void RTIM_AudioandMotorINTConfig(RTIM_TypeDef *TIMx, u32 TIM_IT, u32 NewState)
ENABLE/DISABLE the TIM5's audio and motor interrupt bits.
- 参数:
TIMx -- Where x only can be 5.
TIM_IT --
Specifies the interrupt bit to configure. This parameter can be any combination of the following values:
TIM_IT_EMG_BRK_RELEASE: emergency brake release.
TIM_IT_FIFO_EMPTY: FIFO empty intr.
NewState -- ENABLE or DISABLE
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void RTIM_AudioandMotorSetBrakeLevel(RTIM_TypeDef *TIMx, u32 BRAKE_LEVEL, u16 TIM_Channel)
Set the TIM5's brake status.
- 参数:
TIMx -- Where x only can be 5.
BRAKE_LEVEL --
Specifies the channel brake level. This parameter can be any of the following values:
PWM_OUTPUT_LOW
PWM_OUTPUT_HIGH
TIM_Channel -- The channel need to be initialized, which can be one of the following parameters TIM Channel
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void RTIM_AudioandMotorSetBrakeLevelUp(RTIM_TypeDef *TIMx)
For fifo empty, after configuring the brake state of all channels, set brake state up and the brake state will take effect.
- 参数:
TIMx -- Where x only can be 5.
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void RTIM_AudioandMotorSetFIFOEmptyMode(RTIM_TypeDef *TIMx, u32 FIFO_EMPTY_MODE, u16 TIM_Channel)
Set the TIM5's FIFO empty mode.
- 参数:
TIMx -- Where x only can be 5.
FIFO_EMPTY_MODE --
Specifies the FIFO empty mode. This parameter can be any of the following values:
PWM_FIFO_EMPTY_MAINTAIN
PWM_FIFO_EMPTY_BRAKE
TIM_Channel -- The channel need to be initialized, which can be one of the following parameters TIM Channel
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void RTIM_AudxInit(RTIM_TypeDef *TIMx, TIM_AudInitTypeDef *TIM_AudInitStruct, u16 TIM_Channel)
Initialize the TIMx Channel 0-5 according to the specified parameters in the TIM_AudInitStruct.
- 参数:
TIMx -- Where x only can be 5.
TIM_AudInitStruct -- Pointer to a TIM_AudInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
TIM_Channel -- The channel need to be initialized, which can be one of the following parameters TIM Channel
备注
TIM5 has 6 channels: TIM_Channel_0-5.
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void RTIM_DeadzoneCmd(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 NewState)
Enable or disable deadzone control function.
- 参数:
TIMx -- Where x only can be 5.
TIM_Channel -- The channel need to be configured, which can be one of the following parameters TIM Channel
NewState -- New state of the deadzone control function. This parameter can be: ENABLE or DISABLE.
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void RTIM_EmgBrkDbcCmd(RTIM_TypeDef *TIMx, u32 NewState)
Enable/Disable debounce function of TIM emergency brake.
- 参数:
TIMx -- TIMx: where x only can be 5.
NewState -- New state of the TIMx peripheral. This parameter can be: ENABLE or DISABLE.
-
u32 RTIM_GetAudioandMotorINTStatus(RTIM_TypeDef *TIMx, u32 TIM_IT_AUD_FLAG)
Clear the TIM5's audio and motor interrupt bits.
- 参数:
TIMx -- Where x only can be 5.
TIM_IT_AUD_FLAG --
Specifies the TIM audio and motor interrupt flag to check. This parameter can be one of the following values:
TIM_IT_EMG_BRK_RELEASE_FLAG: emergency brake release intr flag.
TIM_IT_FIFO_EMPTY_FLAG: FIFO empty intr flag.
- 返回:
The new state of the TIM_IT:
TRUE: The specified TIM interrupt has occurred.
FALSE: The specified TIM interrupt has not occurred.
-
void RTIM_ResetFIFO(RTIM_TypeDef *TIMx)
Reset FIFO.
- 参数:
TIMx -- TIMx: where x only can be 5.
-
void RTIM_SetDeadzoneMAXChnID(RTIM_TypeDef *TIMx)
Set the max deadzone_tim'channel id.
- 参数:
TIMx -- Where x only can be 5.
-
void RTIM_SetDeadzoneTim(RTIM_TypeDef *TIMx, u32 deadzone_tim, u16 TIM_Channel)
Set deadzone_tim.
- 参数:
TIMx -- Where x only can be 5.
deadzone_tim -- It means delay cycles on positive edge, it's count by 40M.
TIM_Channel -- The channel need to be initialized, which can be one of the following parameters TIM Channel
-
void RTIM_SetEmgBrkDbcCnt(RTIM_TypeDef *TIMx, u16 Dbc_Cnt)
Set debounce counter under XTAL40M to realize signal deglitch.
- 参数:
TIMx -- TIMx: where x only can be 5.
Dbc_Cnt -- Debounce counter to be set.
备注
Dbc_Cnt = 0 means debounce function is disabled.
-
void RTIM_SetEmgBrkLevel(RTIM_TypeDef *TIMx, u32 EMG_BRK_LEVEL, u16 TIM_Channel)
Set emergency brake level.
- 参数:
TIMx -- TIMx: where x only can be 5.
EMG_BRK_LEVEL -- It means when emergency brake is triggered, the PWM output level. This parameter can be: PWM_EMGBRK_OUTPUT_LOW or PWM_EMGBRK_OUTPUT_HIGH.
TIM_Channel -- The channel need to be initialized, which can be one of the following parameters TIM Channel
-
void RTIM_SetEmgBrkPolarity(RTIM_TypeDef *TIMx, u32 EMG_BRK_POLARITY)
Set emergency brake trigger polarity.
- 参数:
TIMx -- Where x only can be 5.
EMG_BRK_POLARITY --
Emergency brake trigger polarity. This parameter can be one of the following values:
PWM_EMGBRK_TRI_POL_HIHG: High level to trigger emergency braking
PWM_EMGBRK_TRI_POL_LOW: Low level to trigger emergency braking
-
void RTIM_SetFIFOFirstLevel(RTIM_TypeDef *TIMx, u16 FIFO_Level)
When writing a FIFO for the first time, you should configure the level of FIFO before FIFO to be read. Generally greater than the number of chn working in FIFO.
- 参数:
TIMx -- TIMx: where x only can be 5.
FIFO_Level -- The level of FIFO before FIFO to be read.
-
void RTIM_SetPadOutMode(RTIM_TypeDef *TIMx, u32 Channel, u32 Mode)
Set the PAD output mode for the specified channel. Used to select the correspondence between ch and output pad.
- 参数:
TIMx -- Where x only can be 5.
Channel -- The index of the channel, range [0, PWM_CHAN_MAX-1].
Mode --
The PAD output mode selection. This parameter can be one of the following values:
PWM_CHANNEL_OUTPUT_TWOPAD: Two chns control two output pad.
PWM_CHANNEL_OUTPUT_ONEPAD: One chn controls two output pad.
-
void RTIM_SetPhaseSel(RTIM_TypeDef *TIMx, u16 TIM_Channel, u32 Phase)
Select output phase in audio/motor scenario.
- 参数:
TIMx -- Where x only can be 5.
TIM_Channel -- The channel need to be configured, which can be one of the following parameters TIM Channel
Phase --
Output phase selection. This parameter can be one of the following values:
0: opposite phase
1: same phase
Mbed API
MBED_PWM Exported Types
Structure Type
-
typedef struct pwmout_s pwmout_t
Typedef struct pwmout_s to pwmout_t.
MBED_PWM Exported Functions
-
void pwmout_free(pwmout_t *obj)
Deinitialize the PWM device of the specified channel.
- 参数:
obj -- PWM object defined in application software.
备注
If all channels are released, PWMTIMER will also be disabled.
-
void pwmout_init(pwmout_t *obj, PinName pin)
Initialize PWM channel output according to the specified pin.
- 参数:
obj -- PWM object defined in application software.
pin -- Pin name of corresponding PWM channel to be set.
备注
Default period: 1638us.
Default pulse width: 102us.
Default duty cycle: 6.227%.
-
void pwmout_period(pwmout_t *obj, float seconds)
Set the period of the specified channel in seconds.
- 参数:
obj -- PWM object defined in application software.
seconds -- The period value to be set in seconds(s).
-
void pwmout_period_ms(pwmout_t *obj, int ms)
Set the period of the specified channel in milliseconds.
- 参数:
obj -- PWM object defined in application software.
ms -- The period value to be set in milliseconds(ms).
-
void pwmout_period_us(pwmout_t *obj, int us)
Set the period of the specified channel in microseconds.
- 参数:
obj -- PWM object defined in application software.
us -- The period value to be set in microseconds(us).
-
void pwmout_pulsewidth(pwmout_t *obj, float seconds)
Set the pulse width of the specified channel in seconds.
- 参数:
obj -- PWM object defined in application software.
seconds -- The pulse width value to be set in seconds(s).
-
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
Set the pulse width of the specified channel in milliseconds.
- 参数:
obj -- PWM object defined in application software.
ms -- The pulse width value to be set in milliseconds(ms).
-
void pwmout_pulsewidth_us(pwmout_t *obj, int us)
Set the pulse width of the specified channel in microseconds.
- 参数:
obj -- PWM object defined in application software.
us -- The pulse width value to be set in microseconds(us).
-
float pwmout_read(pwmout_t *obj)
Get the duty cycle of the specified channel.
- 参数:
obj -- PWM object defined in application software.
- 返回:
Duty cycle of the specified channel, in the range [0.0, 1.0].
-
void pwmout_set_polarity(pwmout_t *obj, int polarity)
Set the polarity of the specified PWM channel.
- 参数:
obj -- PWM object defined in application software.
polarity --
This parameter can be one of the following values:
0: Output is LOW when timer count < set value.
1: Output is HIGH when timer count < set value (default).
注意
Configure polarity after setting duty cycle or pulse width.
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void pwmout_start(pwmout_t *obj)
Enable the specified channel to output PWM.
- 参数:
obj -- PWM object defined in application software.