Memory Management & Cache

This chapter introduces the memory management and cache architecture of the chip.

• Memory Protection
  • Introduction
  • Memory Protection Unit (Arm®v8-M)
  • Memory Protection Unit (HiFi 5 DSP)
  • Physical Memory Protection Unit (RISC-V PMP)
• Memory Management Unit
  • Introduction
  • MMU Workflow
• Cache
  • Introduction
  • Cache Configuration
  • Cache Way Restriction
  • Tightly-Coupled Memory (TCM)
  • Registers