Memory Organization

Introduction

The chip integrates several distinct address regions: ROM stores factory-programmed boot code and is read-only, SRAM serves as the primary working memory for program execution, Flash provides non-volatile storage for firmware and persistent data, and DRAM (PSRAM/DDR) supports large-capacity extended memory for demanding applications. In addition, the chip maps various peripherals onto the bus system through memory mapping, allowing peripheral access via the peripheral register region. All these resources are mapped within a unified 4GB linear address space, with data encoded in Little-Endian format.

The addressable space is divided into multiple main blocks, as shown in the following table and figure. All the areas that are not allocated to on-chip memories and peripherals are considered as RSVD (reserved).

Memory Layout

The following table lists the memory address allocation for each chip.

RTL8721Dx:

Base Address	End Address	Size (bytes)	Description	Type	TrustZone
0x0000_0000	0x0007_FFFF	512K	KM4 Internal ROM	ROM	-
0x0000_0000	0x0007_FFFF	512K	KM0 Internal ROM	ROM	-
0x0008_0000	0x000F_FFFF	512K	RSVD	-	-
0x0010_0000	0x07FF_FFFF	127M	RSVD	-	-
0x0800_0000	0x0FFF_FFFF	128M	SPI Flash	Flash	-
0x1000_0000	0x1FFF_FFFF	256M	RSVD	-	-
0x2000_0000	0x2007_FFFF	512K	SRAM	SRAM	-
0x2008_0000	0x200F_FFFF	512K	Shared SRAM	SRAM	-
0x2010_0000	0x2FFF_FFFF	255M	RSVD	-	-
0x3000_0000	0x3FFF_FFFF	256M	TrustZone secure address (SRAM)	-	Secure
0x4000_0000	0x40FF_FFFF	16M	High-Speed peripherals group	Peripherals	-
0x4100_0000	0x41FF_FFFF	16M	Low-Speed peripherals group	Peripherals	-
0x4200_0000	0x4FFF_FFFF	224M	RSVD	-	-
0x5000_0000	0x5FFF_FFFF	256M	TrustZone secure address (Peripherals)	-	Secure
0x6000_0000	0x6FFF_FFFF	256M	PSRAM	DRAM	-
0x7000_0000	0x7FFF_FFFF	256M	TrustZone secure address (PSRAM)	-	Secure
0x8000_0000	0xFFFF_FFFF	2048M	RSVD	-	-

Note

This is the division of address space, not representing actual physical occupation.
The TrustZone feature is only applicable to KM4, so the secure address spaces can only be accessed from the secure world of KM4 and other security-capable masters.
The security attribute of an address space is determined by bit[28] of that address.
Except for the specified processor-only address spaces, all other address spaces can be directly accessed by both KM0 and KM4.

RTL8720E:

Base Address	End Address	Size (bytes)	Description	Type	TrustZone
0x0000_0000	0x0007_FFFF	512K	KM4 Internal ROM	ROM	-
0x0000_0000	0x0007_FFFF	512K	KR4 Internal ROM	ROM	-
0x0008_0000	0x000F_FFFF	512K	RSVD	-	-
0x0010_0000	0x07FF_FFFF	127M	RSVD	-	-
0x0800_0000	0x0FFF_FFFF	128M	SPI Flash	Flash	-
0x1000_0000	0x1FFF_FFFF	256M	RSVD	-	-
0x2000_0000	0x2003_FFFF	256K	HS SRAM0	SRAM	-
0x2004_0000	0x200B_FFFF	512K	HS SRAM1	SRAM	-
0x200C_0000	0x21FF_FFFF	31.25M	RSVD	-	-
0x2200_0000	0x2204_3FFF	272K	Bluetooth SRAM	SRAM	-
0x2204_4000	0x2207_FFFF	240K	RSVD	-	-
0x2208_0000	0x2208_9FFF	40K	Wi-Fi SRAM	SRAM	-
0x2208_A000	0x2FFF_FFFF	223.5M	RSVD	-	-
0x3000_0000	0x3FFF_FFFF	256M	TrustZone secure address (SRAM)	-	Secure
0x4000_0000	0x40FF_FFFF	16M	HS peripherals group	Peripherals	-
0x4100_0000	0x41FF_FFFF	16M	LS peripherals group	Peripherals	-
0x4200_0000	0x4FFF_FFFF	224M	RSVD	-	-
0x5000_0000	0x5FFF_FFFF	256M	TrustZone secure address (Peripherals)	-	Secure
0x6000_0000	0x6FFF_FFFF	256M	PSRAM	DRAM	-
0x7000_0000	0x7FFF_FFFF	256M	TrustZone secure address (PSRAM)	-	Secure
0x8000_0000	0x8FFF_FFFF	256M	KR4 PLIC (KR4 only)	-	-
0x9000_0000	0xFFFF_FFFF	1792M	RSVD	-	-

Note

This is the division of address space, not representing actual physical occupation.
The TrustZone feature is only applicable to KM4, so the secure address spaces can only be accessed from the secure world of KM4 and other security-capable masters.
The security attribution of address space is determined by bit[28] of this address.
KM4 and KR4 can directly access all other address spaces except the specified processor-exclusive address spaces.

RTL8710E:

Base Address	End Address	Size (bytes)	Description	Type
0x0000_0000	0x0007_FFFF	512K	KM4 Internal ROM	ROM
0x0000_0000	0x0007_FFFF	512K	KR4 Internal ROM	ROM
0x0008_0000	0x000F_FFFF	512K	RSVD	-
0x0010_0000	0x07FF_FFFF	127M	RSVD	-
0x0800_0000	0x0FFF_FFFF	128M	SPI Flash	Flash
0x1000_0000	0x1FFF_FFFF	256M	RSVD	-
0x2000_0000	0x2003_FFFF	256K	HS SRAM0	SRAM
0x2004_0000	0x2007_FFFF	256K	HS SRAM1	SRAM
0x2008_0000	0x21FF_FFFF	31.5M	RSVD	-
0x2200_0000	0x2204_3FFF	272K	Bluetooth SRAM	SRAM
0x2204_4000	0x2207_FFFF	240K	RSVD	-
0x2208_0000	0x2208_9FFF	40K	Wi-Fi SRAM	SRAM
0x2208_A000	0x2FFF_FFFF	223.5M	RSVD	-
0x3000_0000	0x3FFF_FFFF	256M	RSVD	-
0x4000_0000	0x40FF_FFFF	16M	HS peripherals group	Peripherals
0x4100_0000	0x41FF_FFFF	16M	LS peripherals group	Peripherals
0x4200_0000	0x4FFF_FFFF	224M	RSVD	-
0x5000_0000	0x5FFF_FFFF	256M	RSVD	-
0x6000_0000	0x6FFF_FFFF	256M	PSRAM	DRAM
0x7000_0000	0x7FFF_FFFF	256M	RSVD	-
0x8000_0000	0x8FFF_FFFF	256M	KR4 PLIC (KR4 only)	-
0x9000_0000	0xFFFF_FFFF	1792M	RSVD	-

Note

This represents the address space allocation, not the actual physical memory usage.
Except for the processor-specific address spaces listed above, all other address spaces are directly accessible by both KM4 and KR4.

RTL8726E:

Base Address	End Address	Size (bytes)	Description	Type	TrustZone
0x0000_0000	0x0007_FFFF	512K	KM4 Internal ROM	ROM	-
0x0000_0000	0x0007_FFFF	512K	KR4 Internal ROM	ROM	-
0x0008_0000	0x000F_FFFF	512K	RSVD	-	-
0x0010_0000	0x07FF_FFFF	127M	RSVD	-	-
0x0800_0000	0x0FFF_FFFF	128M	SPI Flash	Flash	-
0x1000_0000	0x1FFB_FFFF	255.75M	RSVD	-	-
0x1FFC_0000	0x1FFF_FFFF	256K	HiFi 5 DSP DTCM RAM (DSP only)	SRAM	-
0x2000_0000	0x2003_FFFF	256K	HS SRAM0	SRAM	-
0x2004_0000	0x2007_FFFF	256K	HS SRAM1	SRAM	-
0x2008_0000	0x21FF_FFFF	31.5M	RSVD	-	-
0x2200_0000	0x2204_3FFF	272K	Bluetooth SRAM	SRAM	-
0x2204_4000	0x2207_FFFF	240K	RSVD	-	-
0x2208_0000	0x2208_9FFF	40K	Wi-Fi SRAM	SRAM	-
0x2208_A000	0x2FFF_FFFF	223.5M	RSVD	-	-
0x3000_0000	0x3FFF_FFFF	256M	TrustZone secure address (SRAM)	-	Secure
0x4000_0000	0x40FF_FFFF	16M	HS peripherals group	Peripherals	-
0x4100_0000	0x41FF_FFFF	16M	LS peripherals group	Peripherals	-
0x4200_0000	0x4FFF_FFFF	224M	RSVD	-	-
0x5000_0000	0x5FFF_FFFF	256M	TrustZone secure address (Peripherals)	-	Secure
0x6000_0000	0x6FFF_FFFF	256M	PSRAM	DRAM	-
0x7000_0000	0x7FFF_FFFF	256M	TrustZone secure address (PSRAM)	-	Secure
0x8000_0000	0x8FFF_FFFF	256M	KR4 PLIC (KR4 only)	-	-
0x9000_0000	0xFFFF_FFFF	1792M	RSVD	-	-

Note

This is the division of address space, not representing actual physical occupation.
The TrustZone feature is only applicable to KM4, so the secure address spaces can only be accessed from the secure world of KM4 and other security-capable masters.
The security attribution of address space, except the space of HiFi 5 DSP DTCM RAM (from 0x1FFC_0000 to 0x1FFF_FFFF), is determined by bit[28] of the address.
All other address spaces can be accessed directly by KM4, KR4, and HiFi 5 DSP, except the specified processor-only address spaces.

RTL8713E:

Base Address	End Address	Size (bytes)	Description	Type
0x0000_0000	0x0007_FFFF	512K	KM4 Internal ROM	ROM
0x0000_0000	0x0007_FFFF	512K	KR4 Internal ROM	ROM
0x0008_0000	0x000F_FFFF	512K	RSVD	-
0x0010_0000	0x07FF_FFFF	127M	RSVD	-
0x0800_0000	0x0FFF_FFFF	128M	SPI Flash	Flash
0x1000_0000	0x1FFB_FFFF	255.75M	RSVD	-
0x1FFC_0000	0x1FFF_FFFF	256K	HiFi 5 DSP DTCM RAM (DSP only)	SRAM
0x2000_0000	0x2003_FFFF	256K	HS SRAM0	SRAM
0x2004_0000	0x2007_FFFF	256K	HS SRAM1	SRAM
0x2008_0000	0x21FF_FFFF	31.5M	RSVD	-
0x2200_0000	0x2204_3FFF	272K	Bluetooth SRAM	SRAM
0x2204_4000	0x2207_FFFF	240K	RSVD	-
0x2208_0000	0x2208_9FFF	40K	Wi-Fi SRAM	SRAM
0x2208_A000	0x2FFF_FFFF	223.5M	RSVD	-
0x3000_0000	0x3FFF_FFFF	256M	RSVD	-
0x4000_0000	0x40FF_FFFF	16M	HS peripherals group	Peripherals
0x4100_0000	0x41FF_FFFF	16M	LS peripherals group	Peripherals
0x4200_0000	0x4FFF_FFFF	224M	RSVD	-
0x5000_0000	0x5FFF_FFFF	256M	RSVD	-
0x6000_0000	0x6FFF_FFFF	256M	PSRAM	DRAM
0x7000_0000	0x7FFF_FFFF	256M	RSVD	-
0x8000_0000	0x8FFF_FFFF	256M	KR4 PLIC (KR4 only)	-
0x9000_0000	0xFFFF_FFFF	1792M	RSVD	-

Note

This is the division of address space and does not represent actual physical occupation.
Except for the processor-specific address spaces indicated, all other address spaces are directly accessible by KM4, KR4, and HiFi 5 DSP.

RTL8730E:

Base Address	End Address	Size (bytes)	Description	Type	TrustZone
0x0000_0000	0x0007_FFFF	512K	CA32 Bus ROM	ROM	-
0x0000_0000	0x0007_FFFF	512K	KM4 Internal ROM	ROM	-
0x0000_0000	0x0007_FFFF	512K	KM0 Internal ROM	ROM	-
0x0008_0000	0x000F_FFFF	512K	KM4 TCM	TCM	-
0x0010_0000	0x07FF_FFFF	127M	RSVD	-	-
0x0800_0000	0x0FFF_FFFF	128M	SPI Flash	Flash	-
0x1000_0000	0x1FFF_FFFF	256M	RSVD	-	-
0x2000_0000	0x20FF_FFFF	16M	HP SRAM (actually 256KB)	SRAM	-
0x2100_0000	0x21FF_FFFF	16M	RSVD	-	-
0x2200_0000	0x22FF_FFFF	16M	Extension SRAM	SRAM	-
0x2300_0000	0x23FF_FFFF	16M	LS SRAM (actually 64KB)	SRAM	-
0x2400_0000	0x2FFF_FFFF	192M	RSVD	-	-
0x3000_0000	0x3FFF_FFFF	256M	TrustZone secure address (SRAM)	-	Secure
0x4000_0000	0x41FF_FFFF	32M	HP peripherals group	Peripherals	-
0x4200_0000	0x42FF_FFFF	16M	LS peripherals group	Peripherals	-
0x4300_0000	0x43FF_FFFF	16M	WLAN firmware	Peripherals	-
0x4400_0000	0x440F_FFFF	1M	SPI Flash Controller	Peripherals	-
0x4410_0000	0x4FFF_FFFF	191M	RSVD	-	-
0x5000_0000	0x5FFF_FFFF	256M	TrustZone secure address (Peripherals)	-	Secure
0x6000_0000	0x6FFF_FFFF	256M	External PSRAM/DDR (selectable)	DRAM	-
0x7000_0000	0x7FFF_FFFF	256M	TrustZone secure address (DRAM)	-	Secure
0x8000_0000	0x8003_FFFF	256K	CA32 internal debug register	-	-
0x8004_0000	0x9FFF_FFFF	511.75M	RSVD	-	-
0xA000_0000	0xA00F_FFFF	1M	CA32 debug register	CA32	-
0xA010_0000	0xA010_7FFF	32K	CA32 GIC	CA32	-
0xA010_8000	0xAFFF_FFFF	254.96875M	RSVD	-	-
0xB000_0000	0xB000_1FFF	8K	RSVD	-	Secure
0xB000_2000	0xB000_2FFF	4K	CA32 timestamp/system counter	-	Secure
0xB000_3000	0xBFFF_FFFF	255.98828125M	RSVD	-	Secure
0xC000_0000	0xDFFF_FFFF	512M	RSVD	-	-
0xE000_0000	0xE0FF_FFFF	16M	System PPB Device (RAM predefined)	-	-
0xE100_0000	0xFFFF_FFFF	496M	RSVD	-	-

Note

This is the division of address space, not representing actual physical occupation.
The function of TrustZone is only applicable to KM4 and CA32, so the secure address spaces can only be accessed from the secure world of KM4 and CA32 and other security-capable masters.
The security attribution of address space is determined by the bit[28] of this address.
All other address spaces can be accessed directly by KM0, KM4 and CA32 except the specified each processor-only address spaces.

RTL8721F:

Base Address	End Address	Size (bytes)	Description	Type	TrustZone
0x0000_0000	0x000E_FFFF	960K	KM4TZ Internal ROM	ROM	-
0x000F_0000	0x000F_FFFF	64K	TCM	TCM	-
0x0010_0000	0x001F_FFFF	1M	Common ROM	ROM	-
0x0020_0000	0x0FFF_FFFF	254M	SPI Flash	Flash	-
0x1000_0000	0x101F_FFFF	2M	RSVD	-	-
0x1020_0000	0x1FFF_FFFF	254M	SPI Flash Alias	Flash	Secure
0x2000_0000	0x200F_FFFF	1M	HS SRAM	SRAM	-
0x2010_0000	0x2FFF_FFFF	255M	RSVD	SRAM	-
0x3000_0000	0x3FFF_FFFF	256M	TrustZone secure address (SRAM)	-	Secure
0x4000_0000	0x407F_FFFF	8M	HS Peripherals Group	Peripherals	-
0x4080_0000	0x40FF_FFFF	8M	LS_ON Peripherals Group
0x4100_0000	0x417F_FFFF	8M	LS Peripherals Group
0x4180_0000	0x4FFF_FFFF	232M	RSVD
0x5000_0000	0x5FFF_FFFF	256M	TrustZone secure address (Peripherals)		Secure
0x6000_0000	0x6FFF_FFFF	256M	External PSRAM	DRAM	-
0x7000_0000	0x7FFF_FFFF	256M	TrustZone secure address (PSRAM)		Secure
0x8000_0000	0xFFFF_FFFF	2048M	RSVD	-	-

Note

This is the division of address space, not representing actual physical occupation.
The TrustZone feature is only applicable to KM4TZ, so the secure address spaces can only be accessed from the secure world of KM4TZ and other security-capable masters.
The security attribution of address space is determined by bit[28] of this address.
Except for the specified processor-exclusive address spaces, all other address spaces can be directly accessed by both KM4TZ and KM4NS.

The following figures show the corresponding memory address space diagrams:

RTL8721Dx:

Memory Map

The following table lists the memory map and boundary addresses of registers available in the chip.

RTL8721Dx:

Port ID	Port Name	Security	Base Address	End Address	Size (bytes)
S0	SPIC_AUTO_MODE	Non-secure	0x0800_0000	0x0FFF_FFFF	128M
S1	HS SRAM0	MPC	0x2000_0000	0x2007_FFFF	512K
S2	HS_SHARE_SRAM	MPC	0x2008_0000	0x200F_FFFF	512K
S3	WIFI_REG	PPC	0x4000_0000	0x4007_FFFF	512K
S3	BT_REG	PPC	0x4008_0000	0x400F_FFFF	512K
S3	AES_REG	PPC	0x4010_0000	0x4010_7FFF	32K
S3	SHA_REG	PPC	0x4010_8000	0x4010_FFFF	32K
S3	GDMA0_REG	PPC	0x4011_0000	0x4011_7FFF	32K
S3	PPE_REG	PPC	0x4011_8000	0x4011_FFFF	32K
S3	SDIO_REG	PPC	0x4012_0000	0x4012_3FFF	16K
S3	SPI0_REG	PPC	0x4012_4000	0x4012_4FFF	4K
S3	SPI1_REG	PPC	0x4012_5000	0x4012_5FFF	4K
S3	PSRAM_PHY_REG	PPC	0x4012_6000	0x4012_6FFF	4K
S3	PSRAM_REG	PPC	0x4012_7000	0x4012_7FFF	4K
S3	SPI_FLASH_CTRL	PPC	0x4012_8000	0x4012_8FFF	4K
S3	QSPI_REG	PPC	0x4012_9000	0x4012_9FFF	4K
S3	SPORT0_REG	PPC	0x4012_A000	0x4012_AFFF	4K
S3	SPORT1_REG	PPC	0x4012_B000	0x4012_BFFF	4K
S3	USB_REG	PPC	0x4012_C000	0x4017_FFFF	336K
S4	OTPC_REG	PPC	0x4100_0000	0x4100_7FFF	32K
S4	SYSTEM_CTRL	PPC	0x4100_8000	0x4100_BFFF	16K
S4	PINMUX_REG	PPC	0x4100_8800	0x4100_89FF	512
S4	RTC_REG	PPC	0x4100_8A00	0x4100_8BFF	512
S4	IWDG_REG	PPC	0x4100_8C00	0x4100_8CFF	256
S4	WDG0_REG	PPC	0x4100_8D00	0x4100_8D3F	64
S4	WDG1_REG	PPC	0x4100_8D40	0x4100_8D7F	64
S4	WDG2_REG	PPC	0x4100_8D80	0x4100_8DBF	64
S4	RETENTION_RAM	PPC	0x4100_8E00	0x4100_8FFF	512
S4	UART0_REG	PPC	0x4100_C000	0x4100_CFFF	4K
S4	UART1_REG	PPC	0x4100_D000	0x4100_DFFF	4K
S4	UART2_REG	PPC	0x4100_E000	0x4100_EFFF	4K
S4	LOGUART_REG	PPC	0x4100_F000	0x4100_FFFF	4K
S4	GPIO_REG	PPC	0x4101_0000	0x4101_0FFF	4K
S4	ADC_REG	PPC	0x4101_1000	0x4101_17FF	2K
S4	CMP_REG	PPC	0x4101_1800	0x4101_1FFF	2K
S4	CTC_REG	PPC	0x4101_2000	0x4101_2FFF	4K
S4	KSCAN_REG	PPC	0x4101_3000	0x4101_3FFF	4K
S4	IPC0_REG	PPC	0x4101_4000	0x4101_47FF	2K
S4	IPC1_REG	PPC	0x4101_4800	0x4101_4FFF	2K
S4	DEBUGTIMER_REG	PPC	0x4101_5000	0x4101_5FFF	4K
S4	PMC_TIMER_REG	PPC	0x4101_6000	0x4101_6FFF	4K
S4	TIMER0_REG	PPC	0x4101_7000	0x4101_71FF	512
S4	TIMER1_REG	PPC	0x4101_7200	0x4101_73FF	512
S4	TIMER2_REG	PPC	0x4101_7400	0x4101_75FF	512
S4	TIMER3_REG	PPC	0x4101_7600	0x4101_77FF	512
S4	TIMER4_REG	PPC	0x4101_7800	0x4101_79FF	512
S4	TIMER5_REG	PPC	0x4101_7A00	0x4101_7BFF	512
S4	TIMER6_REG	PPC	0x4101_7C00	0x4101_7DFF	512
S4	TIMER7_REG	PPC	0x4101_7E00	0x4101_7FFF	512
S5	TIMER8_REG	PPC	0x4110_0000	0x4110_01FF	512
S5	TIMER9_REG	PPC	0x4110_0200	0x4110_03FF	512
S5	TIMER10_REG	PPC	0x4110_0400	0x4110_05FF	512
S5	TIMER11_REG	PPC	0x4110_0600	0x4110_07FF	512
S5	TRNG_REG	PPC	0x4110_1000	0x4110_1FFF	4K
S5	RXI300M4_REG	PPC	0x4110_2000	0x4110_3FFF	8K
S5	RSIP_REG	PPC	0x4110_4000	0x4110_4FFF	4K
S5	LEDC_REG	PPC	0x4110_5000	0x4110_5FFF	4K
S5	AUDIO_REG	PPC	0x4110_6000	0x4110_6FFF	4K
S5	IR_REG	PPC	0x4110_7000	0x4110_7FFF	4K
S5	I2C0_REG	PPC	0x4110_8000	0x4110_9FFF	8K
S5	I2C1_REG	PPC	0x4110_A000	0x4110_BFFF	8K
S6	PSRAM	MPC	0x6000_0000	0x6FFF_FFFF	256M

RTL8720E:

Port ID	Port Name	Security	Base Address	End Address	Size (bytes)
S1	SPI_FLASH	Non-secure	0x0800_0000	0x0FFF_FFFF	128M
S2	HS_SRAM0	MPC	0x2000_0000	0x2003_FFFF	256K
S3	HS_SRAM1	MPC	0x2004_0000	0x2103_FFFF	16M
S4	HS_SRAM_EXT	Non-secure	0x2200_0000	0x22FF_FFFF	16M
S5	WIFI_REG	PPC	0x4000_0000	0x4007_FFFF	512K
S5	AES_REG	PPC	0x4010_0000	0x4010_7FFF	32K
S5	SHA_REG	PPC	0x4010_8000	0x4010_FFFF	32K
S5	GDMA0_REG	PPC	0x4011_0000	0x4011_7FFF	32K
S5	SPI0_REG	PPC	0x4011_8000	0x4011_8FFF	4K
S5	SPI1_REG	PPC	0x4011_9000	0x4011_9FFF	4K
S5	I2C0_REG	PPC	0x4011_A000	0x4011_AFFF	4K
S5	I2C1_REG	PPC	0x4011_B000	0x4011_BFFF	4K
S5	SPORT0_REG	PPC	0x4011_C000	0x4011_CFFF	4K
S5	SPORT1_REG	PPC	0x4011_D000	0x4011_DFFF	4K
S5	DEBUGTIMER_REG	PPC	0x4011_E000	0x4011_EFFF	4K
S5	ECDSA_REG	PPC	0x4011_F000	0x4011_FFFF	4K
S6	OTPC_REG	PPC	0x4100_0000	0x4100_7FFF	32K
S6	PSRAM_PHY_REG	PPC	0x4100_8000	0x4100_8FFF	4K
S6	PSRAM_REG	PPC	0x4100_9000	0x4100_9FFF	4K
S6	SPI_FLASH_CTRL	PPC	0x4100_A000	0x4100_AFFF	4K
S6	SYSTEM_CTRL	PPC	0x4100_C000	0x4100_DFFF	8K
S6	PINMUX_REG	PPC	0x4100_C800	0x4100_C9FF	512
S6	WDG0_REG	PPC	0x4100_CC00	0x4100_CDFF	512
S6	RETENTION_RAM	PPC	0x4100_CE00	0x4100_CFFF	512
S6	RXI300M4_REG	PPC	0x4100_E000	0x4100_FFFF	8K
S6	UART0_REG	PPC	0x4101_0000	0x4101_0FFF	4K
S6	UART1_REG	PPC	0x4101_1000	0x4101_1FFF	4K
S6	UART2_REG	PPC	0x4101_2000	0x4101_2FFF	4K
S6	UART3_REG	PPC	0x4101_3000	0x4101_3FFF	4K
S6	LOGUART_REG	PPC	0x4101_4000	0x4101_4FFF	4K
S6	LEDC_REG	PPC	0x4101_5000	0x4101_5FFF	4K
S6	TRNG_REG	PPC	0x4101_6000	0x4101_6FFF	4K
S6	AUDIO_REG	PPC	0x4101_7000	0x4101_7FFF	4K
S6	TIMER0_REG	PPC	0x4101_8000	0x4101_81FF	512
S6	TIMER1_REG	PPC	0x4101_8200	0x4101_83FF	512
S6	TIMER2_REG	PPC	0x4101_8400	0x4101_85FF	512
S6	TIMER3_REG	PPC	0x4101_8600	0x4101_87FF	512
S6	TIMER4_REG	PPC	0x4101_8800	0x4101_89FF	512
S6	TIMER5_REG	PPC	0x4101_8A00	0x4101_8BFF	512
S6	TIMER6_REG	PPC	0x4101_8C00	0x4101_8DFF	512
S6	TIMER7_REG	PPC	0x4101_8E00	0x4101_8FFF	512
S6	TIMER8_REG	PPC	0x4101_9000	0x4101_91FF	512
S6	TIMER9_REG	PPC	0x4101_9200	0x4101_93FF	512
S6	TIMER10_REG	PPC	0x4101_9400	0x4101_95FF	512
S6	TIMER11_REG	PPC	0x4101_9600	0x4101_97FF	512
S6	TIMER12_REG	PPC	0x4101_9800	0x4101_99FF	512
S6	TIMER13_REG	PPC	0x4101_9A00	0x4101_9BFF	512
S6	TIMER14_REG	PPC	0x4101_9C00	0x4101_9DFF	512
S6	GPIO_REG	PPC	0x4101_A000	0x4101_AFFF	4K
S6	RTC	PPC	0x4101_B000	0x4101_BFFF	4K
S6	ADC_REG	PPC	0x4101_C000	0x4101_C7FF	2K
S6	CMP_REG	PPC	0x4101_C800	0x4101_CFFF	2K
S6	THERMAL_REG	PPC	0x4101_D000	0x4101_DFFF	4K
S6	CTC_REG	PPC	0x4101_E000	0x4101_EFFF	4K
S6	WDG1_REG	PPC	0x4101_F000	0x4101_F03F	64
S6	WDG2_REG	PPC	0x4101_F040	0x4101_F07F	64
S6	WDG3_REG	PPC	0x4101_F080	0x4101_F0BF	64
S6	WDG4_REG	PPC	0x4101_F0C0	0x4101_F0FF	64
S6	IPC0_REG	PPC	0x4102_0000	0x4102_007F	128
S6	IPC1_REG	PPC	0x4102_0080	0x4102_00FF	128
S6	IPC2_REG	PPC	0x4102_0100	0x4102_017F	128
S6	SDM_REG	PPC	0x4102_1000	0x4102_1FFF	4K
S6	AUDIO_CFG	PPC	0x4102_2000	0x4102_2FFF	4K
S6	BT_REG	PPC	0x4108_0000	0x410F_FFFF	512K
S7	PSRAM	MPC	0x6000_0000	0x6FFF_FFFF	256M
S8	KR4_PLIC	Non-secure	0x8000_0000	0x8000_0FFF	4K

RTL8710E:

Port ID	Port Name	Base Address	End Address	Size (bytes)
S1	SPI_FLASH	0x0800_0000	0x0FFF_FFFF	128M
S2	HS_SRAM0	0x2000_0000	0x2003_FFFF	256K
S3	HS_SRAM1	0x2004_0000	0x2103_FFFF	16M
S4	HS_SRAM_EXT	0x2200_0000	0x22FF_FFFF	16M
S5	WIFI_REG	0x4000_0000	0x4007_FFFF	512K
S5	AES_REG	0x4010_0000	0x4010_7FFF	32K
S5	SHA_REG	0x4010_8000	0x4010_FFFF	32K
S5	GDMA0_REG	0x4011_0000	0x4011_7FFF	32K
S5	SPI0_REG	0x4011_8000	0x4011_8FFF	4K
S5	SPI1_REG	0x4011_9000	0x4011_9FFF	4K
S5	I2C0_REG	0x4011_A000	0x4011_AFFF	4K
S5	I2C1_REG	0x4011_B000	0x4011_BFFF	4K
S5	SPORT0_REG	0x4011_C000	0x4011_CFFF	4K
S5	SPORT1_REG	0x4011_D000	0x4011_DFFF	4K
S5	DEBUGTIMER_REG	0x4011_E000	0x4011_EFFF	4K
S5	ECDSA_REG	0x4011_F000	0x4011_FFFF	4K
S6	OTPC_REG	0x4100_0000	0x4100_7FFF	32K
S6	PSRAM_PHY_REG	0x4100_8000	0x4100_8FFF	4K
S6	PSRAM_REG	0x4100_9000	0x4100_9FFF	4K
S6	SPI_FLASH_CTRL	0x4100_A000	0x4100_AFFF	4K
S6	SYSTEM_CTRL	0x4100_C000	0x4100_DFFF	8K
S6	PINMUX_REG	0x4100_C800	0x4100_C9FF	512
S6	WDG0_REG	0x4100_CC00	0x4100_CDFF	512
S6	RETENTION_RAM	0x4100_CE00	0x4100_CFFF	512
S6	RXI300M4_REG	0x4100_E000	0x4100_FFFF	8K
S6	UART0_REG	0x4101_0000	0x4101_0FFF	4K
S6	UART1_REG	0x4101_1000	0x4101_1FFF	4K
S6	UART2_REG	0x4101_2000	0x4101_2FFF	4K
S6	UART3_REG	0x4101_3000	0x4101_3FFF	4K
S6	LOGUART_REG	0x4101_4000	0x4101_4FFF	4K
S6	LEDC_REG	0x4101_5000	0x4101_5FFF	4K
S6	TRNG_REG	0x4101_6000	0x4101_6FFF	4K
S6	AUDIO_REG	0x4101_7000	0x4101_7FFF	4K
S6	TIMER0_REG	0x4101_8000	0x4101_81FF	512
S6	TIMER1_REG	0x4101_8200	0x4101_83FF	512
S6	TIMER2_REG	0x4101_8400	0x4101_85FF	512
S6	TIMER3_REG	0x4101_8600	0x4101_87FF	512
S6	TIMER4_REG	0x4101_8800	0x4101_89FF	512
S6	TIMER5_REG	0x4101_8A00	0x4101_8BFF	512
S6	TIMER6_REG	0x4101_8C00	0x4101_8DFF	512
S6	TIMER7_REG	0x4101_8E00	0x4101_8FFF	512
S6	TIMER8_REG	0x4101_9000	0x4101_91FF	512
S6	TIMER9_REG	0x4101_9200	0x4101_93FF	512
S6	TIMER10_REG	0x4101_9400	0x4101_95FF	512
S6	TIMER11_REG	0x4101_9600	0x4101_97FF	512
S6	TIMER12_REG	0x4101_9800	0x4101_99FF	512
S6	TIMER13_REG	0x4101_9A00	0x4101_9BFF	512
S6	TIMER14_REG	0x4101_9C00	0x4101_9DFF	512
S6	GPIO_REG	0x4101_A000	0x4101_AFFF	4K
S6	RTC	0x4101_B000	0x4101_BFFF	4K
S6	ADC_REG	0x4101_C000	0x4101_C7FF	2K
S6	CMP_REG	0x4101_C800	0x4101_CFFF	2K
S6	THERMAL_REG	0x4101_D000	0x4101_DFFF	4K
S6	CTC_REG	0x4101_E000	0x4101_EFFF	4K
S6	WDG1_REG	0x4101_F000	0x4101_F03F	64
S6	WDG2_REG	0x4101_F040	0x4101_F07F	64
S6	WDG3_REG	0x4101_F080	0x4101_F0BF	64
S6	WDG4_REG	0x4101_F0C0	0x4101_F0FF	64
S6	IPC0_REG	0x4102_0000	0x4102_007F	128
S6	IPC1_REG	0x4102_0080	0x4102_00FF	128
S6	IPC2_REG	0x4102_0100	0x4102_017F	128
S6	SDM_REG	0x4102_1000	0x4102_1FFF	4K
S6	AUDIO_CFG	0x4102_2000	0x4102_2FFF	4K
S6	BT_REG	0x4108_0000	0x410F_FFFF	512K
S7	PSRAM	0x6000_0000	0x6FFF_FFFF	256M
S8	KR4_PLIC	0x8000_0000	0x8000_0FFF	4K

RTL8726E:

Port ID	Port Name	Security	Base Address	End Address	Size (bytes)
S1	SPI_FLASH	Non-secure	0x0800_0000	0x0FFF_FFFF	128M
S2	HS_SRAM0	MPC	0x2000_0000	0x2003_FFFF	256K
S3	HS_SRAM1	MPC	0x2004_0000	0x2103_FFFF	16M
S4	HS_SRAM_EXT	Non-secure	0x2200_0000	0x22FF_FFFF	16M
S5	WIFI_REG	PPC	0x4000_0000	0x4007_FFFF	512K
S5	AES_REG	PPC	0x4010_0000	0x4010_7FFF	32K
S5	SHA_REG	PPC	0x4010_8000	0x4010_FFFF	32K
S5	GDMA0_REG	PPC	0x4011_0000	0x4011_7FFF	32K
S5	SPI0_REG	PPC	0x4011_8000	0x4011_8FFF	4K
S5	SPI1_REG	PPC	0x4011_9000	0x4011_9FFF	4K
S5	I2C0_REG	PPC	0x4011_A000	0x4011_AFFF	4K
S5	I2C1_REG	PPC	0x4011_B000	0x4011_BFFF	4K
S5	SPORT0_REG	PPC	0x4011_C000	0x4011_CFFF	4K
S5	SPORT1_REG	PPC	0x4011_D000	0x4011_DFFF	4K
S5	DEBUGTIMER_REG	PPC	0x4011_E000	0x4011_EFFF	4K
S5	ECDSA_REG	PPC	0x4011_F000	0x4011_FFFF	4K
S6	OTPC_REG	PPC	0x4100_0000	0x4100_7FFF	32K
S6	PSRAM_PHY_REG	PPC	0x4100_8000	0x4100_8FFF	4K
S6	PSRAM_REG	PPC	0x4100_9000	0x4100_9FFF	4K
S6	SPI_FLASH_CTRL	PPC	0x4100_A000	0x4100_AFFF	4K
S6	SYSTEM_CTRL	PPC	0x4100_C000	0x4100_DFFF	8K
S6	PINMUX_REG	PPC	0x4100_C800	0x4100_C9FF	512
S6	WDG0_REG	PPC	0x4100_CC00	0x4100_CDFF	512
S6	RETENTION_RAM	PPC	0x4100_CE00	0x4100_CFFF	512
S6	RXI300M4_REG	PPC	0x4100_E000	0x4100_FFFF	8K
S6	UART0_REG	PPC	0x4101_0000	0x4101_0FFF	4K
S6	UART1_REG	PPC	0x4101_1000	0x4101_1FFF	4K
S6	UART2_REG	PPC	0x4101_2000	0x4101_2FFF	4K
S6	UART3_REG	PPC	0x4101_3000	0x4101_3FFF	4K
S6	LOGUART_REG	PPC	0x4101_4000	0x4101_4FFF	4K
S6	LEDC_REG	PPC	0x4101_5000	0x4101_5FFF	4K
S6	TRNG_REG	PPC	0x4101_6000	0x4101_6FFF	4K
S6	AUDIO_REG	PPC	0x4101_7000	0x4101_7FFF	4K
S6	TIMER0_REG	PPC	0x4101_8000	0x4101_81FF	512
S6	TIMER1_REG	PPC	0x4101_8200	0x4101_83FF	512
S6	TIMER2_REG	PPC	0x4101_8400	0x4101_85FF	512
S6	TIMER3_REG	PPC	0x4101_8600	0x4101_87FF	512
S6	TIMER4_REG	PPC	0x4101_8800	0x4101_89FF	512
S6	TIMER5_REG	PPC	0x4101_8A00	0x4101_8BFF	512
S6	TIMER6_REG	PPC	0x4101_8C00	0x4101_8DFF	512
S6	TIMER7_REG	PPC	0x4101_8E00	0x4101_8FFF	512
S6	TIMER8_REG	PPC	0x4101_9000	0x4101_91FF	512
S6	TIMER9_REG	PPC	0x4101_9200	0x4101_93FF	512
S6	TIMER10_REG	PPC	0x4101_9400	0x4101_95FF	512
S6	TIMER11_REG	PPC	0x4101_9600	0x4101_97FF	512
S6	TIMER12_REG	PPC	0x4101_9800	0x4101_99FF	512
S6	TIMER13_REG	PPC	0x4101_9A00	0x4101_9BFF	512
S6	TIMER14_REG	PPC	0x4101_9C00	0x4101_9DFF	512
S6	GPIO_REG	PPC	0x4101_A000	0x4101_AFFF	4K
S6	RTC	PPC	0x4101_B000	0x4101_BFFF	4K
S6	ADC_REG	PPC	0x4101_C000	0x4101_C7FF	2K
S6	CMP_REG	PPC	0x4101_C800	0x4101_CFFF	2K
S6	THERMAL_REG	PPC	0x4101_D000	0x4101_DFFF	4K
S6	CTC_REG	PPC	0x4101_E000	0x4101_EFFF	4K
S6	WDG1_REG	PPC	0x4101_F000	0x4101_F03F	64
S6	WDG2_REG	PPC	0x4101_F040	0x4101_F07F	64
S6	WDG3_REG	PPC	0x4101_F080	0x4101_F0BF	64
S6	WDG4_REG	PPC	0x4101_F0C0	0x4101_F0FF	64
S6	IPC0_REG	PPC	0x4102_0000	0x4102_007F	128
S6	IPC1_REG	PPC	0x4102_0080	0x4102_00FF	128
S6	IPC2_REG	PPC	0x4102_0100	0x4102_017F	128
S6	SDM_REG	PPC	0x4102_1000	0x4102_1FFF	4K
S6	AUDIO_CFG	PPC	0x4102_2000	0x4102_2FFF	4K
S6	BT_REG	PPC	0x4108_0000	0x410F_FFFF	512K
S7	PSRAM	MPC	0x6000_0000	0x6FFF_FFFF	256M
S8	KR4_PLIC	Non-secure	0x8000_0000	0x8000_0FFF	4K

RTL8713E:

Port ID	Port Name	Base Address	End Address	Size (bytes)
S1	SPI_FLASH	0x0800_0000	0x0FFF_FFFF	128M
S2	HS_SRAM0	0x2000_0000	0x2003_FFFF	256K
S3	HS_SRAM1	0x2004_0000	0x2103_FFFF	16M
S4	HS_SRAM_EXT	0x2200_0000	0x22FF_FFFF	16M
S5	WIFI_REG	0x4000_0000	0x4007_FFFF	512K
S5	AES_REG	0x4010_0000	0x4010_7FFF	32K
S5	SHA_REG	0x4010_8000	0x4010_FFFF	32K
S5	GDMA0_REG	0x4011_0000	0x4011_7FFF	32K
S5	SPI0_REG	0x4011_8000	0x4011_8FFF	4K
S5	SPI1_REG	0x4011_9000	0x4011_9FFF	4K
S5	I2C0_REG	0x4011_A000	0x4011_AFFF	4K
S5	I2C1_REG	0x4011_B000	0x4011_BFFF	4K
S5	SPORT0_REG	0x4011_C000	0x4011_CFFF	4K
S5	SPORT1_REG	0x4011_D000	0x4011_DFFF	4K
S5	DEBUGTIMER_REG	0x4011_E000	0x4011_EFFF	4K
S5	ECDSA_REG	0x4011_F000	0x4011_FFFF	4K
S6	OTPC_REG	0x4100_0000	0x4100_7FFF	32K
S6	PSRAM_PHY_REG	0x4100_8000	0x4100_8FFF	4K
S6	PSRAM_REG	0x4100_9000	0x4100_9FFF	4K
S6	SPI_FLASH_CTRL	0x4100_A000	0x4100_AFFF	4K
S6	SYSTEM_CTRL	0x4100_C000	0x4100_DFFF	8K
S6	PINMUX_REG	0x4100_C800	0x4100_C9FF	512
S6	WDG0_REG	0x4100_CC00	0x4100_CDFF	512
S6	RETENTION_RAM	0x4100_CE00	0x4100_CFFF	512
S6	RXI300M4_REG	0x4100_E000	0x4100_FFFF	8K
S6	UART0_REG	0x4101_0000	0x4101_0FFF	4K
S6	UART1_REG	0x4101_1000	0x4101_1FFF	4K
S6	UART2_REG	0x4101_2000	0x4101_2FFF	4K
S6	UART3_REG	0x4101_3000	0x4101_3FFF	4K
S6	LOGUART_REG	0x4101_4000	0x4101_4FFF	4K
S6	LEDC_REG	0x4101_5000	0x4101_5FFF	4K
S6	TRNG_REG	0x4101_6000	0x4101_6FFF	4K
S6	AUDIO_REG	0x4101_7000	0x4101_7FFF	4K
S6	TIMER0_REG	0x4101_8000	0x4101_81FF	512
S6	TIMER1_REG	0x4101_8200	0x4101_83FF	512
S6	TIMER2_REG	0x4101_8400	0x4101_85FF	512
S6	TIMER3_REG	0x4101_8600	0x4101_87FF	512
S6	TIMER4_REG	0x4101_8800	0x4101_89FF	512
S6	TIMER5_REG	0x4101_8A00	0x4101_8BFF	512
S6	TIMER6_REG	0x4101_8C00	0x4101_8DFF	512
S6	TIMER7_REG	0x4101_8E00	0x4101_8FFF	512
S6	TIMER8_REG	0x4101_9000	0x4101_91FF	512
S6	TIMER9_REG	0x4101_9200	0x4101_93FF	512
S6	TIMER10_REG	0x4101_9400	0x4101_95FF	512
S6	TIMER11_REG	0x4101_9600	0x4101_97FF	512
S6	TIMER12_REG	0x4101_9800	0x4101_99FF	512
S6	TIMER13_REG	0x4101_9A00	0x4101_9BFF	512
S6	TIMER14_REG	0x4101_9C00	0x4101_9DFF	512
S6	GPIO_REG	0x4101_A000	0x4101_AFFF	4K
S6	RTC	0x4101_B000	0x4101_BFFF	4K
S6	ADC_REG	0x4101_C000	0x4101_C7FF	2K
S6	CMP_REG	0x4101_C800	0x4101_CFFF	2K
S6	THERMAL_REG	0x4101_D000	0x4101_DFFF	4K
S6	CTC_REG	0x4101_E000	0x4101_EFFF	4K
S6	WDG1_REG	0x4101_F000	0x4101_F03F	64
S6	WDG2_REG	0x4101_F040	0x4101_F07F	64
S6	WDG3_REG	0x4101_F080	0x4101_F0BF	64
S6	WDG4_REG	0x4101_F0C0	0x4101_F0FF	64
S6	IPC0_REG	0x4102_0000	0x4102_007F	128
S6	IPC1_REG	0x4102_0080	0x4102_00FF	128
S6	IPC2_REG	0x4102_0100	0x4102_017F	128
S6	SDM_REG	0x4102_1000	0x4102_1FFF	4K
S6	AUDIO_CFG	0x4102_2000	0x4102_2FFF	4K
S6	BT_REG	0x4108_0000	0x410F_FFFF	512K
S7	PSRAM	0x6000_0000	0x6FFF_FFFF	256M
S8	KR4_PLIC	0x8000_0000	0x8000_0FFF	4K

RTL8730E:

Memory Map of HP Platform

The following table gives the boundary addresses of the peripherals available in the HP platform.

Port ID	Port name	Security	Base address	End address	Size (bytes)
S10	CA32_ROM	Secure	0x0000_0000	0x0000_03FF	1K
S11	SPI_FLASH	Non-secure	0x0800_0000	0x0FFF_FFFF	128M
S3	HP_SRAM0	MPC	0x2000_0000	0x20FF_FFFF	16M
S5	HP_SRAM0_EXT	Non-secure	0x2200_0000	0x22FF_FFFF	16M
S8	WIFI_REG	PPC	0x4000_0000	0x4007_FFFF	512K
S8	USB_OTG_REG	PPC	0x4008_0000	0x400B_FFFF	256K
S8	AES_REG	PPC	0x400C_0000	0x400C_7FFF	32K
S8	SHA_REG	PPC	0x400C_8000	0x400C_FFFF	32K
S8	SDIOH_REG	PPC	0x400D_0000	0x400D_7FFF	32K
S8	LCDC_REG	PPC	0x400D_8000	0x400D_FFFF	32K
S8	GDMA0_REG	PPC	0x400E_0000	0x400E_7FFF	32K
S8	SPI0_REG	PPC	0x400E_8000	0x400E_8FFF	4K
S8	SPI1_REG	PPC	0x400E_9000	0x400E_9FFF	4K
S8	MIPI_DSI_REG	PPC	0x400E_A000	0x400E_AFFF	4K
S8	RSA_REG	PPC	0x400E_B000	0x400E_BFFF	4K
S8	ED25519_REG	PPC	0x400E_C000	0x400E_CFFF	4K
S8	ECDSA_REG	PPC	0x400E_D000	0x400E_DFFF	4K
S8	IR_REG	PPC	0x400E_E000	0x400E_EFFF	4K
S8	I2C1_REG	PPC	0x400E_F000	0x400E_FFFF	4K
S8	I2C2_REG	PPC	0x400F_0000	0x400F_0FFF	4K
S8	ZIGBEE_REG	PPC	0x400F_2000	0x400F_3FFF	8K
S8	BT_REG	PPC	0x4010_0000	0x4017_FFFF	512K
S9	SYSTEM_CTRL_HP	PPC	0x4100_0000	0x4100_0FFF	4K
S9	WDG1_REG	PPC	0x4100_0400	0x4100_043F	64
S9	WDG2_REG	PPC	0x4100_0440	0x4100_047F	64
S9	WDG3_REG	PPC	0x4100_0480	0x4100_04BF	64
S9	WDG4_REG	PPC	0x4100_04C0	0x4100_04FF	64
S9	RXI300M4_REG	PPC	0x4100_1000	0x4100_1FFF	4K
S9	PSRAM_PHY_REG	PPC	0x4100_2000	0x4100_2FFF	4K
S9	UART0_REG	PPC	0x4100_4000	0x4100_4FFF	4K
S9	UART1_REG	PPC	0x4100_5000	0x4100_5FFF	4K
S9	UART2_REG	PPC	0x4100_6000	0x4100_6FFF	4K
S9	UART3_REG	PPC	0x4100_7000	0x4100_7FFF	4K
S9	LEDC_REG	PPC	0x4100_8000	0x4100_8FFF	4K
S9	TRNG_REG	PPC	0x4100_9000	0x4100_9FFF	4K
S9	TIMER8_REG	PPC	0x4100_A000	0x4100_A1FF	512
S9	TIMER9_REG	PPC	0x4100_A200	0x4100_A3FF	512
S9	TIMER10_REG	PPC	0x4100_A400	0x4100_A5FF	512
S9	TIMER11_REG	PPC	0x4100_A600	0x4100_A7FF	512
S9	TIMER12_REG	PPC	0x4100_A800	0x4100_A9FF	512
S9	TIMER13_REG	PPC	0x4100_AA00	0x4100_ABFF	512
S9	AUDIO_REG	PPC	0x4100_B000	0x4100_BFFF	4K
S9	VAD_REG	PPC	0x4100_C000	0x4100_CFFF	4K
S9	SPORT0_REG	PPC	0x4100_D000	0x4100_DFFF	4K
S9	SPORT1_REG	PPC	0x4100_E000	0x4100_EFFF	4K
S9	SPORT2_REG	PPC	0x4100_F000	0x4100_FFFF	4K
S9	SPORT3_REG	PPC	0x4101_0000	0x4101_0FFF	4K
S9	DDRPHY_REG	PPC	0x4101_1000	0x4101_1FFF	4K
S9	PSRAM_REG	PPC	0x4101_2000	0x4101_2FFF	4K
S9	DDRC_REG	PPC	0x4110_0000	0x4110_3FFF	16K
S9	DDRC_BSTC_REG	PPC	0x4112_0000	0x4113_FFFF	12K
S7	SPI_FLASH_CTRL	Non-secure	0x4400_0000	0x440F_FFFF	1M
S0/S1/S2	DDR/PSRAM	MPC	0x6000_0000	0x6FFF_FFFF	256M
S12	CA32_DBG_REG	Non-secure	0xA000_0000	0xA003_FFFF	256K
S12	CA32_TIMESTAMP	Secure	0xB000_2000	0xB000_2FFF	4K
S13	CA32_GIC	Non-secure	0xA010_0000	0xA010_7FFF	32K

Memory Map of LS Platform

The following table gives the boundary addresses of the peripherals available in the LS platform.

Port ID	Port name	Security	Base address	End address	Size (bytes)
S5	SPI_FLASH	Non-secure	0x0800_0000	0x0FFF_FFFF	128M
S0	LS_SRAM*	Non-secure	0x2300_0000	0x23FF_FFFF	16M
S1	OTPC_REG	Non-secure	0x4200_0000	0x4200_7FFF	32K
S1	SYSTEM_CTRL_LS	Non-secure	0x4200_8000	0x4200_9FFF	8K
S1	WDG0_REG	Non-secure	0x4200_8400	0x4200_85FF	512
S1	PINMUX_REG	Non-secure	0x4200_8A00	0x4200_8BFF	512
S1	RXI300M0_REG	Non-secure	0x4200_A000	0x4200_AFFF	4K
S1	TIMER0_REG	Non-secure	0x4200_B000	0x4200_B1FF	512
S1	TIMER1_REG	Non-secure	0x4200_B200	0x4200_B3FF	512
S1	TIMER2_REG	Non-secure	0x4200_B400	0x4200_B5FF	512
S1	TIMER3_REG	Non-secure	0x4200_B600	0x4200_B7FF	512
S1	TIMER4_REG	Non-secure	0x4200_B800	0x4200_B9FF	512
S1	TIMER5_REG	Non-secure	0x4200_BA00	0x4200_BBFF	512
S1	TIMER6_REG	Non-secure	0x4200_BC00	0x4200_BFDF	512
S1	TIMER7_REG	Non-secure	0x4200_BE00	0x4200_BFFF	512
S1	UARTLOG_REG	Non-secure	0x4200_C000	0x4200_CFFF	4K
S1	GPIO_REG	Non-secure	0x4200_D000	0x4200_DFFF	4K
S1	RTC_REG	Non-secure	0x4200_E000	0x4200_EFFF	4K
S1	I2C0_REG	Non-secure	0x4200_F000	0x4200_FFFF	4K
S1	CTC_REG	Non-secure	0x4201_0000	0x4201_0FFF	4K
S1	ADC_REG	Non-secure	0x4201_2000	0x4201_2FFF	4K
S1	CMP_REG	Non-secure	0x4201_2200	0x4201_2FFF	4K
S1	THERMAL_REG	Non-secure	0x4201_3000	0x4201_3FFF	4K
S3	WIFI_FW_REG	Non-secure	0x4300_0000	0x43FF_FFFF	16M
S4	SPI_FLASH_CTRL	Non-secure	0x4400_0000	0x440F_FFFF	1M

RTL8721F:

Port ID	Port Name	Security	Base Address	End Address	Size (bytes)
S0	COMMON_ROM	MPC	0x0010_0000	0x001F_FFFF	1M
S1	SPIC_AUTO_MODE	Non-secure	0x0020_0000	0x0FFF_FFFF	254M
S2	HS_SRAM0	MPC	0x2000_0000	0x200F_FFFF	1024K
S3	WIFI_REG	PPC	0x4000_0000	0x4007_FFFF	512K
S3	USB_REG	PPC	0x4008_0000	0x400B_0FFF	196K
S3	UVC_REG	PPC	0x400B_1000	0x400B_1FFF	4K
S3	PKE_REG	PPC	0x400C_0000	0x400F_FFFF	256K
S3	LCDC_REG	PPC	0x4010_0000	0x4010_7FFF	32K
S3	MJPEG_REG	PPC	0x4010_8000	0x4010_FFFF	32K
S3	SDIO_CCCR_REG	PPC	0x4011_0000	0x4011_0FFF	4K
S3	SDIO_WIFI_REG	PPC	0x4011_1000	0x4011_1FFF	4K
S3	SDIO_BT_REG	PPC	0x4011_2000	0x4011_2FFF	4K
S3	SDIO_LOCAL_REG	PPC	0x4011_3000	0x4011_3FFF	4K
S3	SDIO_HOST_CCCR_REG	PPC	0x4011_4000	0x4011_6FFF	12K
S3	SDIO_HOST_LOCAL_REG	PPC	0x4011_7000	0x4011_7FFF	4K
S3	SPORT0_REG	PPC	0x4011_8000	0x4011_8FFF	4K
S3	RMII_REG	PPC	0x4011_A000	0x4011_BFFF	8K
S3	SPI_FLASH_CTRL	PPC	0x4011_D000	0x4011_DFFF	4K
S3	PSRAM_REG	PPC	0x4011_E000	0x4011_EFFF	4K
S3	PSRAM_PHY_REG	PPC	0x4011_F000	0x4011_FFFF	4K
S3	GDMA0_REG	PPC	0x4012_0000	0x4012_0FFF	4K
S3	SPI0_REG	PPC	0x4012_1000	0x4012_1FFF	4K
S3	SPI1_REG	PPC	0x4012_2000	0x4012_2FFF	4K
S3	AES_REG	PPC	0x4012_3000	0x4012_3FFF	4K
S3	SHA_REG	PPC	0x4012_4000	0x4012_4FFF	4K
S3	AES_SHA_DMA_REG	PPC	0x4012_5000	0x4012_5FFF	4K
S3	PPE_REG	PPC	0x4012_6000	0x4012_6FFF	4K
S4	OTPC_REG	PPC	0x4080_0000	0x4080_7FFF	32K
S4	AES_KEY_REG	PPC	0x4080_8000	0x4080_8FFF	4K
S4	SYSTEM_CTRL_BASE	PPC	0x4080_A000	0x4080_BFFF	8K
S4	PINMUX_REG	PPC	0x4080_A800	0x4080_A9FF	512
S4	RTC_REG	PPC	0x4080_AA00	0x4080_ABFF	512
S4	IWDG_REG	PPC	0x4080_AC00	0x4080_ACFF	256
S4	WDG0_REG	PPC	0x4080_AD00	0x4080_AD3F	64
S4	WDG1_REG	PPC	0x4080_AD40	0x4080_AD7F	64
S4	WDG2_REG	PPC	0x4080_AD80	0x4080_ADBF	64
S4	RETENTION_RAM	PPC	0x4080_AE00	0x4080_AFFF	512
S4	UART0_REG	PPC	0x4080_C000	0x4080_CFFF	4K
S4	UART1_REG	PPC	0x4080_D000	0x4080_DFFF	4K
S4	UART2_REG	PPC	0x4080_E000	0x4080_EFFF	4K
S4	UART3_REG	PPC	0x4080_F000	0x4080_FFFF	4K
S4	UARTLOG_REG	PPC	0x4081_0000	0x4081_0FFF	4K
S4	GPIO_REG	PPC	0x4081_1000	0x4081_1FFF	4K
S4	ADC_REG	PPC	0x4081_2000	0x4081_27FF	2K
S4	CMP_REG	PPC	0x4081_2800	0x4081_2FFF	2K
S4	CTC_REG	PPC	0x4081_3000	0x4081_3FFF	4K
S4	SHA_KEY_REG	PPC	0x4081_4000	0x4081_4FFF	4K
S4	IPC0_REG	PPC	0x4081_5000	0x4081_507F	128
S4	IPC1_REG	PPC	0x4081_5080	0x4081_51FF	384
S4	IPC_SEMA	PPC	0x4081_5200	0x4081_53FF	512
S4	THERMAL_REG	PPC	0x4081_6000	0x4081_6FFF	4K
S4	DEBUGTIMER_REG	PPC	0x4081_7000	0x4081_7FFF	4K
S4	PMC_TIMER_REG	PPC	0x4081_8000	0x4081_8FFF	4K
S4	TIMER0_REG	PPC	0x4081_9000	0x4081_91FF	512
S4	TIMER1_REG	PPC	0x4081_9200	0x4081_93FF	512
S4	TIMER2_REG	PPC	0x4081_9400	0x4081_95FF	512
S4	TIMER3_REG	PPC	0x4081_9600	0x4081_97FF	512
S5	TIMER4_REG	PPC	0x4100_0000	0x4100_01FF	512
S5	TIMER5_REG	PPC	0x4100_0200	0x4100_03FF	512
S5	TIMER6_REG	PPC	0x4100_0400	0x4100_05FF	512
S5	TIMER7_REG	PPC	0x4100_0600	0x4100_07FF	512
S5	TIMER8_REG	PPC	0x4100_0800	0x4100_09FF	512
S5	UPS_REG	PPC	0x4100_0A00	0x4100_0BFF	512
S5	TRNG_REG	PPC	0x4100_1000	0x4100_1FFF	4K
S5	RXI300_REG	PPC	0x4100_2000	0x4100_3FFF	8K
S5	RSIP_REG	PPC	0x4100_4000	0x4100_4FFF	4K
S5	CAN0_REG	PPC	0x4100_5000	0x4100_5FFF	4K
S5	CAN1_REG	PPC	0x4100_6000	0x4100_6FFF	4K
S5	IR_REG	PPC	0x4100_7000	0x4100_7FFF	4K
S5	I2C0_REG	PPC	0x4100_8000	0x4100_8FFF	4K
S5	I2C1_REG	PPC	0x4100_9000	0x4100_9FFF	4K
S5	AUDIO_REG	PPC	0x4100_A000	0x4100_AFFF	4K
S5	RXI300_OST_REG	PPC	0x4101_0000	0x4101_FFFF	64K
S6	PSRAM	MPC	0x6000_0000	0x6FFF_FFFF	256M
S7	SHARE_TCM	MPC	0x000F_8000	0x000F_FFFF	32K

ROM

ROM is factory-programmed and contains Boot ROM startup code; it cannot be modified. In general, each CPU has a physically separate ROM that can only be accessed by that CPU, ensuring boot security and inter-core isolation. Some chips also have a shared ROM that is accessible by all CPUs.

RTL8721Dx:

ROM address space: 0x0000_0000 – 0x0007_FFFF.

KM4: 288KB ITCM ROM
KM0: 160KB ITCM ROM

TCM

TCM (Tightly Coupled Memory) is directly connected to the CPU, providing the lowest access latency and is suitable for time-critical tasks. It is repurposed from partially or fully disabled I-Cache/D-Cache. A given region operates in either Cache mode or TCM mode — the two cannot be used simultaneously.

RTL8721Dx:

Not supported.

SRAM

On-chip SRAM is the primary working memory for program execution, used for system stack, dynamic memory allocation, and application data. Some SRAM regions are shared with the Wi-Fi/BT protocol stacks; once the corresponding feature is enabled, those regions are occupied by the protocol stack and are no longer available as general-purpose SRAM.

RTL8721Dx:

The on-chip SRAM starts from 0x2000_0000 and consists of two blocks:

A general-purpose 512KB contiguous SRAM for system heap and application, connected to S1.
A dedicated 160KB SRAM, including 40KB shared with Wi-Fi and 120KB shared with BT, connected to S2. If the user application uses Wi-Fi or BT functionality, the corresponding SRAM will be occupied and can no longer be used as general-purpose SRAM.

All SRAM supports byte/half-word/word (8/16/32-bit) access. It can be enabled or disabled via the PMU to save power, and can enter retention mode for fast wake-up when the system enters sleep mode.

Flash

Flash is a non-volatile storage medium for firmware code and user data; data is retained when power is removed. The Flash memory consists of a SPI Flash controller and a Flash memory array module. The controller acts as an interface between the system bus and the Flash device, implements erase/program operations and read/write protection mechanisms, and accelerates code execution speed through an instruction prefetch and cache line system.

RTL8721Dx:

The SPI Flash controller supports Single/Dual/Quad-wire SPI NOR Flash, up to 100MHz SDR.

DRAM

Some chips integrate stacked high-speed DRAM (DDR or PSRAM) to provide large-capacity extended memory, suitable for applications requiring large data buffers such as audio/video processing and image transfer. For chip models that do not support DRAM, refer to the description in the corresponding tab.

PSRAM

PSRAM (Pseudo Static RAM) is based on the HyperBus interface and uses Double Data Rate (DDR) transfer. Its internal refresh logic is transparent to the host; the host does not need to manage refresh operations, making the usage experience similar to SRAM.

RTL8721Dx:

Supports DDR HyperBus PSRAM.

Clock rate: up to 200MHz
8-bit I/O
Supports half-sleep mode and deep power-down mode

DDR

The DDR interface uses Double Data Rate synchronous technology, transferring two data bytes per clock cycle on the DQ signals, enabling high-speed read/write throughput.

RTL8721Dx:

Not supported.