Interrupt Controller

Introduction

The interrupt controller is responsible for centrally managing interrupt requests from peripherals and internal modules, routing them to the corresponding CPU, and coordinating priority arbitration to ensure that the real-time system can reliably respond to events.

The chip series covers a variety of heterogeneous multi-core designs. Each model integrates one or more processor cores from the following architectures based on specific requirements. Each architecture possesses its own interrupt management system, and each CPU utilizes an interrupt controller compatible with its respective architecture.

The following table illustrates the mapping between each CPU and its corresponding interrupt controller.

Interrupt Index List

The following table shows the interrupt sources and interrupt index assignments for each CPU. When writing an interrupt service routine, look up the corresponding interrupt index for the target CPU to register it.

Note

An empty cell indicates that the interrupt does not exist for that CPU.

RTL8721Dx:

Function

KM0 Index

KM4 Index

WIFI_FISR_FESR_IRQ

0

0

WIFI_FTSR_MAILBOX

1

1

WL_DMA

2

2

WL_PROTOCOL

3

3

BT_SCB

4

4

SYS_ILLEGAL_WRITE

5

KM4_WAKE_IRQ

5

BT_WAKE_HOST

6

6

RXI300

7

7

IPC_KM0

8

IPC_KM4

8

IWDG

9

9

Timer0

10

10

Timer1

11

11

Timer2

12

12

Timer3

13

13

Timer4

14

14

Timer5

15

15

Timer6

16

16

Timer7

17

17

Timer8

18

18

Timer9

19

19

Timer10

20

20

Timer11

21

21

pmc_timer0

22

22

pmc_timer1

23

23

UART0

24

24

UART1

25

25

UART2_BT

26

26

UART_LOG

27

UART_LOG

27

UART_LOG

GPIOA

28

28

GPIOB

29

29

I2C0

30

30

I2C1

31

31

CTOUCH

32

32

GDMA0_Channel0

33

33

GDMA0_Channel1

34

34

GDMA0_Channel2

35

35

GDMA0_Channel3

36

36

GDMA0_Channel4

37

37

GDMA0_Channel5

38

38

GDMA0_Channel6

39

39

GDMA0_Channel7

40

40

PPE

41

41

SPI0

42

42

SPI1

43

43

SPORT0

44

44

SPORT1

45

45

RTC

46

46

ADC

47

47

ADC_COMP

48

48

BOR

49

49

PWR_DOWN

50

50

SPI_FLASH

51

51

Keyscan

52

52

RSIP

53

53

AES

54

54

SHA

55

55

PSRAMC

56

56

TRNG

57

57

AES_S

58

58

SHA_S

59

59

AON_TIM

60

60

AON_WAKEPIN

61

61

LEDC

62

62

IR

63

63

SDIO

64

64

KM0_WDG

65

KM4_NS_WDG

65

KM4_S_WDG

66

QSPI_INT

67

USB_INT

66

68

OCP_INT

69

Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is the interrupt controller for ARM Cortex-M series processors. It is tightly integrated with the processor core to enable low-latency interrupt handling.

NVIC Features:

  • Unified exception management: Processor exceptions (such as HardFault and SysTick) and peripheral interrupts share the same NVIC management mechanism for unified registration and response.

  • Nested interrupts: Supports priority-based nested interrupt handling. A higher-priority interrupt can preempt an active lower-priority interrupt service routine.

  • Vectored interrupts: When an interrupt occurs, the hardware directly jumps to the corresponding ISR entry in the vector table without requiring software polling to identify the interrupt source.

  • Hardware priority masking: The BASEPRI register (an ARM Cortex-M core special register, accessible via the CMSIS library) can be used to mask all interrupts below a specified priority.

  • Vector table relocation: The vector table can be relocated to a custom address via the vector table offset register VTOR (an SCB register in the core).

The NVIC features for each ARM Cortex-M series CPU are as follows:

RTL8721Dx:

KM4 NVIC support:

  • 80 vectored interrupts

  • 8 programmable interrupt priority levels. Values range from 0 to 7; a smaller value indicates a higher priority.

  • Secure and Non-secure NVICs

KM0 NVIC support:

  • 80 vectored interrupts

  • 4 programmable interrupt priority levels. Values range from 0 to 3; a smaller value indicates a higher priority.

Note

For more information on interrupt and NVIC programming, refer to the official technical manual: Arm® Cortex®-M55 Processor Technical Reference Manual.

Generic Interrupt Controller (GIC)

The Generic Interrupt Controller (GIC) is the interrupt controller used by ARM Cortex-A series processors. The GIC collects and arbitrates interrupts from interrupt sources and distributes them to the corresponding CPU.

GIC Architecture Components:

  • Distributor: A global module responsible for managing the priority and enable state of all interrupt sources, and distributing interrupts to the target CPU interfaces.

  • CPU Interface: A per-CPU interface responsible for delivering interrupt signals to the CPU and handling interrupt acknowledgment and end-of-interrupt (EOI) operations.

  • Peripheral interrupt inputs: Peripherals send interrupt signals into the Distributor via dedicated interrupt request lines (IRQ lines). This is the signal interface between the GIC and on-chip peripherals (not an internal GIC module).

GIC Features:

  • Interrupt masking: Interrupt enable and disable can be controlled by priority or on a per-source basis.

  • Priority ordering: Supports configurable interrupt priorities; a smaller value indicates a higher priority.

  • Interrupt distribution: Interrupts can be routed to one or more target CPUs.

  • Interrupt state tracking: The hardware maintains the pending and active state for each interrupt.

  • Software Generated Interrupts (SGI): Supports sending software interrupts to target CPUs by writing a register, commonly used for inter-core communication.

  • Security Extensions: Supports TrustZone security partitioning to isolate secure and non-secure interrupt management.

  • Virtualization Extensions: Supports virtual interrupt injection in Hypervisor scenarios.

  • Multi-core support: Interrupts can be distributed to any processing unit in a multi-core system.

  • Interrupt preemption: Supports higher-priority interrupts preempting a lower-priority interrupt currently being handled.

The above are general GIC features. The following are the specific configuration parameters for the CA32 CPU in this chip. The GIC divides interrupts into three categories: Software Generated Interrupts (SGI), triggered by software register writes for inter-core communication; Private Peripheral Interrupts (PPI), exclusive to each CPU such as the core timer; and Shared Peripheral Interrupts (SPI), shared by all CPUs and corresponding to on-chip peripheral IRQs.

CA32 GIC support:

  • 16 Software Generated Interrupts (SGI): for inter-core software-triggered interrupts.

  • 16 Private Peripheral Interrupts (PPI): private to each CPU, such as generic timer interrupts.

  • Up to 96 Shared Peripheral Interrupts (SPI): peripheral interrupts shared by all CPUs.

  • 32 programmable interrupt priority levels.

Note

All interrupts for CA32 must be routed to the CPU through the GIC. Although the CA32 processor retains the legacy nFIQ/nIRQ input pins, no interrupt sources in this chip are connected to these pins. Therefore, even if GIC interrupt bypass takes effect (for example, after a reset), no external interrupt will bypass the GIC to directly trigger CA32 via nFIQ/nIRQ.

Note

Platform-Level Interrupt Controller (PLIC)

The RISC-V Platform-Level Interrupt Controller (PLIC) is an interrupt controller designed specifically for RISC-V systems. The PLIC multiplexes various device interrupts onto the KR4’s external interrupt line and provides hardware interrupt priority support.

Note

  • In the PLIC, a larger value indicates a higher priority (the opposite of NVIC/GIC). The SDK abstracts this difference.

  • The SDK’s ISR framework automatically handles the explicit claim-complete operation required by the PLIC when processing external interrupts.

The PLIC can generate three types of interrupts with the following characteristics:

  • External Interrupts

    • Interrupt sources fed into the PLIC are called global interrupts, also referred to as PLIC interrupts.

    • Each interrupt source (e.g., an I/O interrupt) has its own:

      • Priority register. A larger value indicates a higher priority.

      • Enable register per interrupt target.

      • Interrupt identifier (ID), starting from 1 (0 is reserved).

    • Each interrupt target (e.g., a CPU) has its own:

      • Threshold register.

      • Enable register per interrupt source.

    • An interrupt is triggered when the maximum priority is strictly greater than the corresponding interrupt threshold.

    • The PLIC uses a “claim-complete” handshake mechanism to handle interrupts: the CPU reads the claim register (an MMIO read operation) to obtain the highest-priority interrupt ID (claim), and after handling it, writes that ID back to the complete register (complete).

    • The PLIC supports both level-sensitive and pulse-sensitive interrupt signal types, and the pending behavior differs in the claim-complete flow:

      • For level-sensitive interrupts: as long as the interrupt source is cleared before the complete signal is issued, the interrupt handler runs only once. If the interrupt source remains asserted after the complete signal is issued, the interrupt will become pending again.

      • For pulse-sensitive interrupts: regardless of how many pulses the PLIC detects before the complete signal is issued, the interrupt pending is only triggered once.

  • Timer Interrupts

    • Triggered when the timer count value exceeds the value set in the MTIMECMP register.

  • Software Interrupts

    • Triggered when 0x1 is written to the MSIP address.

KR4 PLIC support:

  • 80 interrupt sources. All interrupts are level-sensitive.

  • 7 programmable interrupt priority levels with hardware priority masking.

Note

The KR4 PLIC pending bit behavior differs from the standard RISC-V specification as follows:

  • Standard PLIC: When an interrupt is triggered, the pending bit is set regardless of the enable bit state. A pending interrupt will be handled once re-enabled.

  • KR4 modification: A trigger signal sets the pending bit only when the corresponding interrupt’s enable bit is already set. A signal that arrives while the enable bit is not set does not produce a pending entry, and will not be handled even after the enable bit is re-asserted.

Note

For more information on interrupt and PLIC programming, refer to the RISC-V privileged architecture proposal.

DSP Interrupt Controller (XEA2)

The HiFi 5 DSP uses the Xtensa Interrupt Architecture 2 (XEA2) as its interrupt controller. XEA2 is the standard interrupt architecture defined by Tensilica for the Xtensa processor family.

Note

The XEA2 priority model uses a larger value to indicate a higher priority (the opposite of NVIC/GIC), and interrupt source priorities are fixed in hardware and cannot be modified by software (refer to the DSP_INT_LEVEL column in the Interrupt Index List).

HiFi 5 DSP Interrupt Controller Features:

  • 32 asynchronous interrupts: Generated by external and internal sources, covering interrupt priorities from normal level (Level-1) up to high priority and Non-Maskable Interrupt (NMI), as well as internal interrupt sources such as timers.

  • Multi-level priorities and NMI: Supports multiple interrupt priority levels (up to six in the XEA2 standard, four on this chip’s DSP) and an optional Non-Maskable Interrupt (NMI). The interrupt priority of each function is fixed in hardware and cannot be modified.

  • iDMA interrupts: The integrated DMA engine can be configured to interrupt the DSP upon completion of a specific descriptor or when an error occurs.

  • Timer Interrupts: Two internal timer interrupts, generated by comparing trigger values in special registers against a 32-bit cycle counter.

  • Interrupt vectors: High-priority and non-maskable interrupts each have a dedicated interrupt vector per level.

  • Performance Monitor Interrupts: The performance monitor sends a level-sensitive signal (from the debug module) to the processor to trigger an interrupt when a performance counter overflows.

  • Supports multiple interrupt types:

    • External Level Interrupts: Level-sensitive interrupt signals input to the processor.

    • External Edge Interrupts: Edge-triggered interrupt signals input to the processor.

    • Internal Interrupts: Interrupts generated by the processor’s internal logic (e.g., timers and debug interrupts).

    • Non-Maskable Interrupt (NMI): An external edge-triggered interrupt signal input to the processor with an implicitly infinite priority.

    • Write Error Interrupts: Interrupts generated when a PIF write response encounters an error.