Bus Architecture

Introduction

The chip uses a Multi-layer AXI Matrix as its on-chip communication bus architecture. This can be understood as a “multi-lane interchange hub” inside the chip: multiple Masters (modules that initiate transfers, such as CPUs and DMAs) can simultaneously access Slaves (target modules being accessed, such as SRAM, Flash, and peripherals) through different paths without interference. Its key features are as follows:

• Multi-channel Parallel Access: Multiple Masters can simultaneously access different Slaves through different paths at the same time, eliminating the serial bottleneck of traditional single-bus architectures and significantly improving data throughput.

• Hierarchical Peripheral Integration: The high-speed AXI matrix directly connects CPUs and memories, while low-speed peripherals (APB) are connected through dedicated AXI-to-AHB/APB bridges at reduced speeds, ensuring that the high-speed core is not slowed down by waiting for slow peripherals.

Note

The ARM AMBA bus protocols are divided into three tiers by performance: AXI4 (high-speed, used for CPU/DMA/memory), AHB (medium-speed, commonly used for bus bridges), and APB4 (low-speed, used for peripheral register access).

Architecture Diagram

The bus architecture of each chip is shown in the figures below. The figures illustrate how each master port (M*) connects to each slave port (S*) through the interconnect matrix, as well as the hierarchical positions of AXI/AHB/APB bridges.

RTL8721DxRTL8720ERTL8710ERTL8726ERTL8713ERTL8730ERTL8721F

RTL8721Dx:

Master Ports

Master Ports are the initiating side of bus transactions. Modules that need to actively read and write data — such as CPUs, DMAs, and Wi-Fi — connect to the interconnect matrix through master ports.

RTL8721DxRTL8720ERTL8710ERTL8726ERTL8713ERTL8730ERTL8721F

RTL8721Dx:

Port ID	Master	Interconnect type	Data bus width	Description
M0	KM0	AXI4	32 bits	KM0 CPU master
M1	KM4	AXI4	32 bits	KM4 CPU master
M2	GDMA0	AXI4	32 bits	GDMA0 controller master
M3	Wi-Fi	AXI4	32 bits	Wi-Fi master
M4-0	SDIO	AHB	32 bits	SDIO master
M4-1	LX_Master_AES_Hash	AXI4	32 bits	AES/SHA master
M5-0	SIC	APB4	32 bits	SIC master
M5-1	OTPC	APB4	32 bits	OTP controller master
M6	PPE	AXI4	32 bits	PPE master

Slave Ports

Slave Ports are the responding side of bus accesses, where memories and peripherals are attached as slave devices. The “Security Attribute” column in the tables describes the access control mechanism for each port:

• MPC (Memory Protection Controller): Controls security/non-secure partitioning of the memory region; only authorized masters can access the corresponding partition.

• PPC (Peripheral Protection Controller): Controls access permissions for peripheral registers.

• Non-secure: Not subject to security control; all masters can access directly.

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RTL8721Dx:

Port ID	Slave Port	Interconnect type	Data bus width	Security	Description
S0	SPIC Auto Mode	AXI4	32 bits	Non-secure	Flash auto mode access, connected to the matrix through SPI Flash controller
S1	HS SRAM0	AXI4	64 bits	MPC	On-chip SRAM
S2	HS_SHARE_SRAM	AXI4	32 bits	MPC	BT/Wi-Fi shared SRAM, can be used by masters when BT/Wi-Fi is off.
S3	HS Peripherals	AXI4/AHB/APB4	32 bits	PPC	High-speed peripherals
S4	LS_ON Peripherals	APB4	32 bits	PPC	Low-speed peripherals that remain powered in sleep mode.
S5	LS Peripherals	APB4	32 bits	PPC	Low-speed peripherals
S6	PSRAM	AXI4	32 bits	MPC	External PSRAM

Note

For detailed contents of each slave port, refer to Memory Organization .