Reset and Clock Control (RCC)

The RCC (Reset and Clock Control) module is responsible for chip-wide clock generation and reset management, forming the foundation for reliable system operation. Its main functions include:

  • Reset Control: Centrally manages multiple reset sources such as POR, BOR, WDG, and software-triggered resets, and records the reset reason for the current boot to facilitate debugging and fault diagnosis.

  • Clock Management: Supports multiple clock sources (external crystal oscillator, internal RC oscillator, PLL), with independent clock source and divider ratio configuration for each module, balancing performance and power consumption.

  • Clock Gating: Unused clocks can be dynamically disabled to avoid unnecessary dynamic power consumption.

Reset Control

Introduction

The chip supports multiple types of reset signals, including POR (Power-On Reset), CHIP_EN reset, BOR (Brown-Out Reset), System reset, WDG reset, etc. Different reset types have different trigger conditions and scopes, covering scenarios from hardware power-on to software-triggered resets.

Reset Architecture

The overall reset architecture diagram is shown below:

RTL8721Dx:
../../_images/rcc_reset_diagram_dplus.svg

Reset Types

The table below lists the reset types supported by the chip and their trigger conditions. The reset type of the current boot can be obtained via the Boot Reason Register.

RTL8721Dx:

Reset Type

Description

POR

Power-on reset generated by the voltage regulator at power-up. Refer to the Power Sequence section in the datasheet for the power sequence of POR.

CHIP_EN reset

External power-on reset generated when the external CHIP_EN pin is pulled low. Refer to the Power Sequence section in the datasheet for the power sequence of CHIP_EN reset.

BOR

Brownout reset generated by the voltage regulator when a brownout (BOR) is detected. Refer to the Power Sequence section in the datasheet for the power sequence of BOR.

System reset

System reset triggered by the CPU writing to the system reset register. Refer to System reset.

Warm reset

Warm reset triggered by writing to the CPU register.

IWDG reset

Reset generated by Independent Watchdog (IWDG) timeout. Refer to WDG .

WDG reset

Reset generated by System Watchdog (WDG) timeout. Refer to WDG .

DSLP

Reset generated by Deep sleep.

System Reset

System reset is a software reset mechanism provided by the chip for safely resetting the system. All CPUs can perform a System reset using the following sequence:

RTL8721Dx:

  1. Write 0x96969696 to the REG_SW_RST_TRIG register to unlock write access to the REG_SW_RST_CTRL register.

  2. Get the CPU ID of the current CPU, and write 1 to the corresponding CPU control bit in the REG_SW_RST_CTRL register.

  3. Write 0x69696969 to the REG_SW_RST_TRIG register to trigger System reset.

Note

For register descriptions, refer to System Reset Registers

Plfm1 Reset

Plfm1 reset is used to reset the modules located on platform 1 in 2in1 mode.

RTL8721Dx:

Not supported.

Reset Domain

The scope of each reset type is as follows:

RTL8721Dx:

Scope

RTC

Backup registers, Retention RAM, Wake pin, Trap pin

Other peripherals

CHIP_EN

Y

Y

Y

POR

Y

Y

Y

BOR

N

N

Y

DSLP

N

N

Y

System reset

N

N

Y

IWDG reset

N

N

Y

WDG reset

N

N

Y

  • Y: Indicates that the corresponding module will be reset when the reset event occurs.

  • N: Indicates that the corresponding module will not be reset when the reset event occurs.

Note

  • Warm reset is configured at system startup to reset all CPUs instead of only the local CPU. Refer to the Peripheral_Reset() function in the Bootloader for the peripherals that are reset by warm reset.

Clock Control

The chip’s clock system consists of three types of clock sources: external oscillator, internal RC oscillator, and PLL. These are flexibly distributed to functional modules through clock selection and division mechanisms.

Properly configuring clock sources enables a balance between performance and power consumption: high-performance peripherals use the high-frequency clock output from PLL, while low-power modules can switch to the internal RC oscillator to save energy.

Clock Tree

The chip’s clock tree is shown below. Different clock sources can be used to drive different functions, and each clock source can be independently enabled or disabled when not in use to optimize power consumption.

RTL8721Dx:
../../_images/rcc_clock_diagram_dplus.svg

Clock Sources

The clock sources supported by the chip and their purposes are as follows:

RTL8721Dx:

  • Three external oscillators:

    • XTAL40M: Used directly by peripherals or after frequency division.

    • XTAL20M: Used as one of the optional clock sources for UART and LOGUART.

    • XTAL128K: Dedicated to BT_32K after frequency division.

  • Four internal oscillators:

    • OSC4M: Provides a 4MHz clock to KM0 or a 2MHz clock to peripherals (after frequency division).

    • OSC131K: Used as the input to SDM and as the clock for Cap-Touch and Key-Scan.

    • OSC100K: Located in the AON domain, used to drive IWDG and AON modules.

    • SDM_32K: Used by modules such as Timer.

  • Four independent PLLs: each can be configured with an integer or fractional ratio.

    • PLL_SYS: 300MHz ~ 600MHz, provides clocks to KM4, KM0, and high-performance peripherals after frequency division.

    • SPIC_CK: Dedicated to SPIC and PSRAM, with the same frequency as PLL_SYS but a different phase.

    • SPIC_PS_CK: Dedicated to SPIC and PSRAM power saving.

    • One PLL dedicated to Wi-Fi: 320MHz.

Registers

System Reset Registers

The following registers are used for system software reset.

RTL8721Dx:

The base address of the system reset registers is 0x41008000.

Name

Offset

Access

Description

REG_SW_RST_CTRL

0x260

R/W

System reset control register

REG_SW_RST_TRIG

0x264

W

System reset trigger register

REG_SW_RST_CTRL

  • Name: System reset control register

  • Size: 32 bits

  • Address offset: 0x260

  • Read/Write access: Read/Write

Bits

Symbol

Access

Reset

Description

31

LSYS_BIT_KM4_SYS_RST

R/W

0

Used for KM4 to reset the system

30

LSYS_BIT_KM0_SYS_RST

R/W

0

Used for KM0 to reset the system

29:0

RSVD

N/A

0

Reserved for reset domain control

REG_SW_RST_TRIG

  • Name: System reset trigger register

  • Size: 32 bits

  • Address offset: 0x264

  • Read/Write access: Write-only

Bits

Symbol

Access

Description

31:0

LSYS_MASK_TRIG_RST

W

System reset trigger register

  • Write 0x96969696 to enable writing to the REG_SW_RST_CTRL register.

  • Write 0x69696969 to trigger a system reset if REG_SW_RST_CTRL has already been set.

  • Writing any other value clears bits [31:30] of REG_SW_RST_CTRL.

Boot Reason Registers

The following registers are used to provide the boot reason.

Note

After system startup, the Bootloader will clear this register and save the boot reason to the REG_LSYS_BOOT_REASON_SW register.

RTL8721Dx:

The base address of boot reason registers is 0x41008000.

REG_BOOT_REASON_HW

  • Name: Boot Reason Register

  • Size: 32 bits

  • Address Offset: 0x20

  • Read/Write Access: Read/Write (Write 1 to Clear)

Bits

Symbol

Access

Reset

Description

31:10

RSVD

Reserved

9

KM0_WARM2PERI_RSTF

R/W1C

0

Set to 1 when KM0 warm resets the system. Write 1 to clear.

8

KM4_WARM2PERI_RSTF

R/W1C

0

Set to 1 when KM4 warm resets the system. Write 1 to clear.

7

WDG2_RSTF

R/W1C

0

Set to 1 when WDG2 resets the system. Write 1 to clear.

6

WDG1_RSTF

R/W1C

0

Set to 1 when WDG1 resets the system. Write 1 to clear.

5

WDG0_RSTF

R/W1C

0

Set to 1 when WDG0 resets the system. Write 1 to clear.

4

IWDG_RSTF

R/W1C

0

Set to 1 when IWDG resets the system. Write 1 to clear.

3

KM0SYS_RSTF

R/W1C

0

Set to 1 when KM0 triggers a system reset. Write 1 to clear.

2

KM4SYS_RSTF

R/W1C

0

Set to 1 when KM4 triggers a system reset. Write 1 to clear.

1

DSLP_RSTF

R/W1C

0

Set to 1 when exiting deep sleep (DSLP). Write 1 to clear.

0

BOR_RSTF

R/W1C

0

Set to 1 when BOR resets the system. Write 1 to clear.