Memory Management Unit

Supported IC [ RTL8730E ]

Introduction

The CA32 core integrates a Memory Management Unit (MMU) that complies with the ARMv8-A AArch32 architecture standard. This unit provides fine-grained memory control through a set of virtual-to-physical address mappings and memory attributes stored in translation tables.

The MMU has the following features:

  • Address Translation: Converts virtual addresses to physical addresses, supporting fine-grained memory page management.

  • Permission Control: Sets read/write/execute attributes for memory regions to ensure that only authorized processes can access specific memory areas, preventing out-of-bounds or unauthorized access.

  • Memory Isolation: Eliminates inter-process memory interference at its root by assigning independent virtual address spaces to different processes.

  • Cache Management: Allows independent cache policy configuration (Cacheable/Non-cacheable, Write-Back/Write-Through, etc.) for each virtual memory region to optimize memory access performance.

MMU Workflow

The MMU implements precise memory control through the following process.

  1. The CPU issues a virtual address access request, which is intercepted by the MMU.

  2. Translation Table lookup: The MMU traverses the multi-level page tables stored in memory to map the virtual address to the corresponding physical address. The SDK primarily uses long-descriptor format page tables.

  3. Permission check: The MMU simultaneously checks the access permissions (readable/writable/executable) of the memory region for the current execution level (EL0/EL1), and triggers an exception if a violation occurs.

  4. TLB acceleration: The Translation Lookaside Buffer (TLB) caches recently used address mapping entries, avoiding the need to traverse multi-level page tables on every access, thereby significantly reducing address translation overhead.

  5. Physical address output: After passing the permission check, the actual physical address is sent to the memory bus for access.

Note

For more information about MMU, refer to Arm® Cortex®-A32 Processor Technical Reference Manual Revision: r1p0.