Overview

Ameba series products support UART interfaces, capable of asynchronous serial full-duplex communication.

Features

• Supports multiple UART data formats

• Configurable receive clock, supporting low-power receive mode

• Supports hardware auto flow control

• Supports de-bounce of receive signal

• Supports receive baud rate monitoring and correction

• Supports serial infrared encoding and decoding

• Operation Modes

  • Polling mode

  • Interrupt mode

  • DMA mode

TRX Clock

Transmission Clock and Baud Rate

• Clock: XTAL40M

• Baud Rate: 110bps - 8Mbps

Reception Clock and Baud Rate

Reception clocks include XTAL40M, OSC2M and XTAL2M. The supported reception clocks for each chip are shown in the table below:

Ameba SoC	RTL8721Dx	RTL8720E	RTL8726E	RTL8713E	RTL8730E	RTL8721F
XTAL40M	Y	Y	Y	Y	Y	Y
OSC2M	Y	Y	Y	Y	Y	Y
XTAL2M	N	Y	Y	Y	Y	N

The baud rate ranges corresponding to each reception clock are shown in the table below:

Reception Clock	XTAL40M (Default)	OSC2M	XTAL2M
Baud Rate	110bps - 8Mbps	110bps - 115200bps	110bps - 115200bps

Operating Modes

According to the requirements, the UART can be configured to operate in the following three modes:

Polling Mode

This is the most basic operation mode. The CPU polls the status registers of the UART and reads/writes the FIFO buffer as needed to achieve data transmission and reception.

Suitable for small-scale data transfer with lower real-time requirements.

Interrupt Mode

When the configured trigger conditions are met, the UART hardware sends an interrupt signal to notify the CPU to handle related tasks.

This method reduces the need for frequent polling, thereby lowering CPU utilization and improving response speed.

DMA Mode

Data transfer is managed by the DMA controller through a handshaking mechanism with the UART, reducing the processing burden on the CPU.

Applicable to applications requiring handling of large amounts of data, such as audio/video streaming and large data transfers.

• UART sends data in DMA mode with GDMA as flow controller.

• UART receives data in DMA mode with GDMA or UART as flow controller:

  • If developers need to receive data of a fixed amount, GDMA can be used to control UART DMA.

  • If developers need to receive data of an unfixed amount, UART can be used to control UART DMA.

Note

• For considerations regarding data transmission in DMA mode, refer to the DMA and Cache section.

• For different methods of in UART DMA for reception, refer to the content in Application Examples.

Hardware Auto Flow Control

UART supports hardware auto flow control by asserting RTS signals to request to send data and clearing CTS signals to prevent data transmission, thereby avoiding data loss or overflow.

The connection of devices for hardware auto flow control is shown in the figure below:

UART Auto Flow Control Signal Connection

Note

The nRTS signal and nCTS signal are active low.

Auto Request to Send

• Device A sets its RTS signal to low when it is ready to receive data, notifying Device B that it can send data.

• When the amount of data in Device A’s receive FIFO reaches the configured threshold, the RTS signal is set to high, indicating Device B should stop sending data.

• When the amount of data in Device A’s receive FIFO decreases to a certain level, the RTS signal is set to low, notifying Device B to resume data transmission.

Note

• Once RTS is set to high, the timing to set RTS to low again depends on the data count in the receive FIFO.

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730ERTL8721F

• The RTS signal is set to low only when the receive FIFO is completely empty.

Auto Clear to Send

Device A monitors the CTS signal from Device B to determine whether to continue sending data:

• When the CTS signal is low, Device A can send data.

• When the CTS signal is high, Device A does not send data.

Application Examples

The SDK provides two types of functional examples to help developers understand and use UART features:

• mbed Examples

  • Path: {SDK}\component\example\peripheral\mbed\UART\{demo}

  • Demonstrate how to implement UART control in the mbed environment.

• Raw Examples

  • Path: {SDK}\component\example\peripheral\raw\UART\{demo}

  • Demonstrate how to directly control UART without an abstraction layer.

Below is a brief description of the functions of the raw examples:

• raw_uart_poll_trx demonstrates data transmission and reception in the UART polling operation mode;

• raw_uart_poll_autoctrl demonstrates transmission and reception of large amounts of data in UART polling operation mode with auto flow control;

• raw_uart_int_trx demonstrates data transmission and reception in the UART interrupt operation mode;

• raw_uart_int_stream demonstrates transmission and reception of large amounts of data in the UART interrupt operation mode;

• raw_uart_int_rx_timeout demonstrates data transmission and reception in UART interrupt operation mode with timeout protection;

• raw_uart_dma_clock demonstrates data transmission in the UART DMA operation mode;

• raw_uart_dma_stream demonstrates transmission and reception of a fixed amount of data in the UART DMA operation mode;

• raw_uart_dma_rx_fc demonstrates transmission and reception of an unfixed amount of data in the UART DMA operation mode.

Note

To find out which chips the examples support, check the README.md file in the example path.

API Reference

For detailed understanding and usage of the related APIs, refer to {SDK}\component\soc\amebaxxxx\fwlib\include\ameba_uart.h.

Troubleshooting

Data Loss on Wakeup via UART

Phenomenon	Data sent to the UART to wake up the system results in some data loss after waking up.
Cause	The UART receive FIFO has limited size. When sent data is too long, the system cannot process it in time, resulting in only part of the data being retained.
Solution	Adjust the wake-up data length to not exceed the size of the receive FIFO. Use dummy characters to wake up the system first and then send the valid data.

Out-of-Bounds Data Reception with UART DMA

Phenomenon	On RTL8721Dx/RTL8720E/RTL8726E/RTL8713E/RTL8730E, received data exceeds the predefined buffer limits when running the raw_uart_dma_rx_fc example.
Cause	The amount of received data cannot be controlled when UART performs as DMA rx flow controller.
Solution	Run the raw_uart_dma_stream example and enable the definition of macro UART_USE_GTIMER_TO. This allows developers to receive no more than a specified amount of data under continuous reception.