Overview

Ameba series products support Motorola’s SPI interface, enabling efficient four-wire full-duplex communication.

Features

  • Supports master or slave operation modes

  • Independent interrupt masking capability

  • Hardware/Software chip select supported

  • Programmable features

    • Supports dynamic control of serial interface frequency (effective in master mode)

    • Configurable data frame size (4~16 bits)

    • Configurable clock polarity and phase

    • Programmable delay sample time (effective in master mode)

  • Transmission modes

    • Transmit and receive

    • Transmit only

    • Receive only

  • Operation modes

    • Polling mode

    • Interrupt mode

    • DMA mode

Serial Clock Frequency

Interface Frequency (fsclk_out) Support:

  • Master Mode: Supports up to 50 MHz.

  • Slave Mode: Supports up to 25 MHz.

Attention

The maximum frequency is affected by the pinmux selection. Please refer to Pin Multiplexing Configuration Strategy.

Support for Slave Overclocking Mode:

  • Prerequisite: The communicating master device must support the delay sample mechanism.

  • Delay Sample Mechanism: Using the pre-agreed falling edge for data sampling, the figure contrasts standard sampling edge with the delay sample mechanism.

  • Theoretical Limit: 50 MHz

    ../../../_images/spi_master_sample_delay.svg

    Host Delay Sample Mechanism

Dividing Mechanism

  • Core Formula: fsclk_out = fssi_clk/div

    Where fssi_clk is a clock source from PLL.

  • Constraints:

    • The divider coefficient div only supports even values.

    • The actual output frequency is discrete, which means the output fsclk_out may deviate from the expected value.

Attention

The configuration of PLL output during the bootloader phase affects the SPI serial clock frequency. Methods for adjusting PLL output can be found in ameba_bootcfg.

For example, when the SPI target working clock (fssi_clk) is 100 MHz, and the PLL is set to 524 MHz, the SPI actual working clock is only 86.67 MHz. At this rate, the maximum resultant fsclk_out is just 43.3 MHz, not reaching the desired maximum of 50 MHz.

Pin Multiplexing Configuration Strategy

The interface frequency and pin configuration are listed below:

Configuration Mode

Master Frequency

Slave Frequency

Dedicated Pins

50 MHz

25 MHz

Full Matrix Pins

25 MHz

12.5 MHz

Note

For the difference between dedicated pins and full matrix pins, please refer to the Function Multiplexing section.

Operating Modes

SPI Configurable Operating Modes

Polling Mode

This is the most basic operating mode. The CPU polls the SPI status registers and reads or writes the FIFO buffer as needed to send and receive data.

Suited for small-scale data transfers with low real-time requirements.

Interrupt Mode

When configured trigger conditions are met, the SPI hardware sends an interrupt signal to notify the CPU to handle the relevant tasks.

This method reduces the need for frequent polling, lowering CPU usage and improving response speed.

Interrupt Response Delay Leading to Data Transmission Errors

If the CPU cannot respond to interrupts promptly due to OS critical section and other reasons, it may lead to FIFO Overflow/Underflow issues:

  • Transmission Response Delay

    Problems caused by failing to fill the TX FIFO in time, under different SPI roles, are as follows:

    • Master Device:

      • An empty FIFO causes the CS pin to be pulled high, interrupting data transmission.

    • Slave Device:

      • An empty FIFO triggers an underflow event, rendering the data on the MISO line invalid.

      • The master device is unaware of this and continues sampling MISO, possibly receiving incorrect data.

  • Reception Response Delay

    Failing to read the RX FIFO in time results in FIFO Overflow:

    • Impact: Hardware pauses receiving new data.

    • Outcome: Software data reception is incomplete.

DMA Mode

Through an SPI and DMA handshake mechanism, the DMA controller handles data transfers, reducing the CPU’s processing load.

Suitable for applications that require handling large amounts of data, such as audio/video stream processing and large data transfers.

Note

For considerations when using DMA mode for transfers, please refer to the DMA and Cache section.

Application Examples

The SDK provides two types of functional examples to help developers understand and use SPI functionality:

  • Mbed Examples

    • Path: {SDK}\component\example\peripheral\mbed\SPI\{demo}

    • Demonstrates how to implement SPI control in the mbed environment.

  • Raw Examples

    • Path: {SDK}\component\example\peripheral\raw\SPI\{demo}

    • Illustrates how to directly control SPI without abstraction layers.

Below is a brief description of the features of the raw examples:

Note

To see which chips are supported by the examples, refer to the README.md file in the example’s path.

API Reference

For detailed information and usage of related APIs, refer to {SDK}\component\soc\amebaxxxx\fwlib\include\ameba_spi.h.

Troubleshooting

CS Signal Premature High

  • Phenomenon: The CS (Chip Select) signal goes high prematurely before data transmission is complete, causing transmission interruption and incomplete data sending.

  • Possible Causes: FIFO buffer not filled in time or data flow control issues leading to data dropouts.

  • Solutions:

    • Check FIFO Threshold Configuration: Ensure it matches the data flow requirements.

    • Optimize Interrupt Priority: Increase interrupt priority to reduce data fill latency.

    • Use DMA Transfer Mode: This reduces the CPU load and enhances transfer stability.

Minor Data Transfer Errors in DMA Mode

  • Phenomenon: Initial data transfers may contain a few errors, but subsequent transfers are normal.

  • Causes and Solutions: Please refer to the DMA and Cache section.