Overview
Reset is used to restore the system to an initial state, which can be utilized for error recovery, system software reboot, and other functionalities.
Reset Types
The chip supports multiple reset types.
Reset Type |
Description |
Usage Method |
---|---|---|
Chipen |
Reset generated by chip enable |
Refer to Chip Enable |
POR reset |
Reset generated at power-on |
Refer to BOD |
BOR reset |
Reset generated by undervoltage |
Refer to BOD |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to WDG |
WDG reset |
Reset generated by system watchdog timeout |
Refer to WDG |
Reset Type |
Description |
Usage Method |
---|---|---|
Chipen |
Reset generated by chip enable |
Refer to Chip Enable |
POR reset |
Reset generated at power-on |
Refer to BOD |
BOR reset |
Reset generated by undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power Management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to WDG |
WDG reset |
Reset generated by system watchdog timeout |
Refer to WDG |
Reset Type |
Description |
Usage Method |
---|---|---|
Chipen |
Reset generated by chip enable |
Refer to Chip Enable |
POR reset |
Reset generated at power-on |
Refer to BOD |
BOR reset |
Reset generated by undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power Management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to WDG |
WDG reset |
Reset generated by system watchdog timeout |
Refer to WDG |
Reset Type |
Description |
Usage Method |
---|---|---|
Chipen |
Reset generated by chip enable |
Refer to Chip Enable |
POR reset |
Reset generated at power-on |
Refer to BOD |
BOR reset |
Reset generated by undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power Management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to WDG |
WDG reset |
Reset generated by system watchdog timeout |
Refer to WDG |
Reset Type |
Description |
Usage Method |
---|---|---|
Chipen |
Reset generated by chip enable |
Refer to Chip Enable |
POR reset |
Reset generated at power-on |
Refer to BOD |
BOR reset |
Reset generated by undervoltage |
Refer to BOD |
BOR ACC reset |
Reset generated by ACC undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power Management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
WDG reset |
Reset generated by system watchdog timeout |
Refer to WDG |
Reset Type |
Description |
Usage Method |
---|---|---|
Chipen |
Reset generated by chip enable |
Refer to Chip Enable |
POR reset |
Reset generated at power-on |
Refer to BOD |
RTC POR |
Reset generated at power-on in RTC reset domain |
- |
BOR reset |
Reset generated by undervoltage |
Refer to BOD |
Thermal reset |
Reset generated by thermal sensor |
Refer to Thermal |
DSLP |
Reset generated when entering deep sleep mode |
Refer to Power Management |
System reset |
Software reset provided by the system |
Refer to Software Reset |
Warm reset |
Software reset provided by the CPU |
- |
IWDG reset |
Reset generated by independent watchdog timeout |
Refer to WDG |
WDG reset |
Reset generated by system watchdog timeout |
Refer to WDG |
Reset Domains
Power Domain |
Scope |
Chipen |
POR reset |
BOR reset |
DSLP |
system reset |
warm reset |
IWDG reset |
WDG reset |
---|---|---|---|---|---|---|---|---|---|
PD_AON |
RTC |
Y |
Y |
N |
N |
N* |
N* |
N |
N* |
PD_AON |
Backup registers, Retention RAM, Wake pin, Trap pin |
Y |
Y |
N |
N |
N |
N |
N |
N |
PD_AON PD_AON_OTP |
IWDG OTPC |
Y |
Y |
Y |
Y |
Y* |
Y* |
Y |
Y* |
PD_SYSON PD_SOC |
All peripherals in SYSON power domain All peripherals in SOC power domain |
Y |
Y |
Y |
Y |
N* |
N* |
Y |
N* |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Y*: Indicates that the corresponding module will be reset by default when the reset event occurs, but can be configured not to reset.
N*: Indicates that the corresponding module will not be reset by default when the reset event occurs, but can be configured to reset.
Note
The register
REG_AON_SYSRST_MSK
can be used to control whether RTC, IWDG, and OTPC are reset under system reset and WDG reset. The register definition and default values are located insysreg_aon.h
.REG_LSYS_SYSRST_MSK0
andREG_LSYS_SYSRST_MSK1
can be used to control whether peripherals in PD_SYSON and PD_SOC power domains are reset under system reset and WDG reset. The register definitions and default values are located insysreg_lsys.h
.Warm reset can provide more flexibility regarding reset domains through
REG_LSYS_SW_RST_CTRL
. The register definition and default values are located insysreg_lsys.h
.
Power Domain |
Scope |
Chipen |
POR reset |
BOR reset |
thermal reset |
DSLP |
system reset |
warm reset |
IWDG reset |
WDG reset |
---|---|---|---|---|---|---|---|---|---|---|
PD_AON |
AON_RTC |
Y |
Y |
N |
N |
N |
Y* |
Y* |
Y |
Y* |
PD_AON |
Wake pin, Trap pin, Backup registers, Retention RAM |
Y |
Y |
N |
N |
N |
N |
N |
N |
N |
PD_AON_RET PD_AON_OTP |
AON_IWDG OTPC |
Y |
Y |
Y |
Y |
Y |
Y* |
Y* |
Y |
Y* |
PD_SYSON PD_SOC |
All peripherals in PD_SYSON power domain, All peripherals in PD_SOC power domain |
Y |
Y |
Y |
Y |
Y |
Y* |
N* |
Y |
Y* |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Y*: Indicates that the corresponding module will be reset by default when the reset event occurs, but can be configured not to reset.
N*: Indicates that the corresponding module will not be reset by default when the reset event occurs, but can be configured to reset.
Note
The register
REG_AON_SYSRST_MSK
can be used to control whether RTC, IWDG, and OTPC are reset under system reset and warm reset. The register definition and default values are located insysreg_aon.h
.REG_LSYS_SYSRST_MSK0
andREG_LSYS_SYSRST_MSK1
can be used to control whether peripherals in PD_SYSON and PD_SOC power domains are reset under system reset and warm reset. The register definitions and default values are located insysreg_lsys.h
.Warm reset can provide more flexibility regarding reset domains through
REG_LSYS_SW_RST_CTRL
. The register definition and default values are located insysreg_lsys.h
.WDG reset can be controlled for global reset through
REG_LSYS_WDG_GLBRST
.
Power Domain |
Scope |
Chipen |
POR reset |
BOR reset |
thermal reset |
DSLP |
system reset |
warm reset |
IWDG reset |
WDG reset |
---|---|---|---|---|---|---|---|---|---|---|
PD_AON |
AON_RTC |
Y |
Y |
N |
N |
N |
Y* |
Y* |
Y |
Y* |
PD_AON |
Wake pin, Trap pin, Backup registers, Retention RAM |
Y |
Y |
N |
N |
N |
N |
N |
N |
N |
PD_AON_RET PD_AON_OTP |
AON_IWDG OTPC |
Y |
Y |
Y |
Y |
Y |
Y* |
Y* |
Y |
Y* |
PD_SYSON PD_SOC |
All peripherals in PD_SYSON power domain, All peripherals in PD_SOC power domain |
Y |
Y |
Y |
Y |
Y |
Y* |
N* |
Y |
Y* |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Y*: Indicates that the corresponding module will be reset by default when the reset event occurs, but can be configured not to reset.
N*: Indicates that the corresponding module will not be reset by default when the reset event occurs, but can be configured to reset.
Note
The register
REG_AON_SYSRST_MSK
can be used to control whether RTC, IWDG, and OTPC are reset under system reset and warm reset. The register definition and default values are located insysreg_aon.h
.REG_LSYS_SYSRST_MSK0
andREG_LSYS_SYSRST_MSK1
can be used to control whether peripherals in PD_SYSON and PD_SOC power domains are reset under system reset and warm reset. The register definitions and default values are located insysreg_lsys.h
.Warm reset can provide more flexibility regarding reset domains through
REG_LSYS_SW_RST_CTRL
. The register definition and default values are located insysreg_lsys.h
.WDG reset can be controlled for global reset through
REG_LSYS_WDG_GLBRST
.
Power Domain |
Scope |
Chipen |
POR reset |
BOR reset |
thermal reset |
DSLP |
system reset |
warm reset |
IWDG reset |
WDG reset |
---|---|---|---|---|---|---|---|---|---|---|
PD_AON |
AON_RTC |
Y |
Y |
N |
N |
N |
Y* |
Y* |
Y |
Y* |
PD_AON |
Wake pin, Trap pin, Backup registers, Retention RAM |
Y |
Y |
N |
N |
N |
N |
N |
N |
N |
PD_AON_RET PD_AON_OTP |
AON_IWDG OTPC |
Y |
Y |
Y |
Y |
Y |
Y* |
Y* |
Y |
Y* |
PD_SYSON PD_SOC |
All peripherals in PD_SYSON power domain, All peripherals in PD_SOC power domain |
Y |
Y |
Y |
Y |
Y |
Y* |
N* |
Y |
Y* |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Y*: Indicates that the corresponding module will be reset by default when the reset event occurs, but can be configured not to reset.
N*: Indicates that the corresponding module will not be reset by default when the reset event occurs, but can be configured to reset.
Note
The register
REG_AON_SYSRST_MSK
can be used to control whether RTC, IWDG, and OTPC are reset under system reset and warm reset. The register definition and default values are located insysreg_aon.h
.REG_LSYS_SYSRST_MSK0
andREG_LSYS_SYSRST_MSK1
can be used to control whether peripherals in PD_SYSON and PD_SOC power domains are reset under system reset and warm reset. The register definitions and default values are located insysreg_lsys.h
.Warm reset can provide more flexibility regarding reset domains through
REG_LSYS_SW_RST_CTRL
. The register definition and default values are located insysreg_lsys.h
.WDG reset can be controlled for global reset through
REG_LSYS_WDG_GLBRST
.
Power Domain |
Scope |
chipen |
POR reset |
BOR reset |
Thermal reset |
DSLP |
system reset |
warm reset |
IWDG reset |
WDG reset |
---|---|---|---|---|---|---|---|---|---|---|
PD_AON |
Wake pin, Trap pin, AON pad |
Y |
Y |
N |
N |
N |
N |
N |
N |
N |
PD_AON_RET |
RTC |
Y |
Y |
N |
N |
N |
Y* |
N* |
N |
N |
PD_AON_RET |
IWDG |
Y |
Y |
Y |
Y |
Y |
Y* |
N* |
Y |
Y |
PD_AON_OTP |
OTPC |
Y |
Y |
Y |
Y |
N |
Y* |
N* |
Y |
Y |
PD_SYSON PD_LP_PLAT PD_HP_PLAT |
All peripherals in SYSON, LP_PLAT, and HP_PLAT power domains |
Y |
Y |
Y |
Y |
Y |
Y* |
N* |
Y |
Y |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Y*: Indicates that the corresponding module will be reset by default when the reset event occurs, but can be configured not to reset.
N*: Indicates that the corresponding module will not be reset by default when the reset event occurs, but can be configured to reset.
Note
The register
REG_AON_SYSRST_MSK
can be used to control whether RTC, IWDG, and OTPC are reset under system reset and warm reset. The register definition and default values are located insysreg_aon.h
.REG_LSYS_SYSRST_MSK0
andREG_LSYS_SYSRST_MSK1
can be used to control whether peripherals in PD_SYSON, PD_LP_PLAT, and PD_HP_PLAT power domains are reset under system reset and warm reset. The register definitions and default values are located insysreg_lsys.h
.Warm reset can provide more flexibility regarding reset domains through
REG_LSYS_SW_RST_CTRL
. The register definition and default values are located insysreg_lsys.h
.
Power Domain |
Scope |
Chipen |
POR reset |
BOR reset |
Thermal reset |
DSLP |
System reset |
warm reset |
IWDG reset |
WDG reset |
---|---|---|---|---|---|---|---|---|---|---|
PD_RTC |
RTC |
N |
N |
N |
N |
N |
N |
N |
N |
N |
PD_AON PD_AON_RET |
Wake pin, Trap pin, Backup registers, Retention RAM, AON PAD, OTP |
Y |
Y |
N |
N |
N |
N |
N |
N |
N |
PD_AON_RET |
IWDG |
Y |
Y |
Y |
Y |
Y |
Y |
N |
Y |
Y |
PD_SYSON |
I2C like, Pinmux |
Y |
Y |
Y |
Y |
Y |
N* |
N* |
N* |
N* |
PD_SYSON PD_SOC |
All peripherals in SYSON power domain except LEDC and Pinmux, all peripherals in SOC power domain |
Y |
Y |
Y |
Y |
Y |
Y* |
Y* |
Y |
Y* |
Y: Indicates that the corresponding module will be reset when the reset event occurs.
N: Indicates that the corresponding module will not be reset when the reset event occurs.
Y*: Indicates that the corresponding module will be reset by default when the reset event occurs, but can be configured not to reset.
N*: Indicates that the corresponding module will not be reset by default when the reset event occurs, but can be configured to reset.
Note
The register
REG_AON_SYSRST_MSK
can be used to control whether I2C like and Pinmux are reset under System reset, warm reset, IWDG reset, and WDG reset. The register definition is located insysreg_aon.h
.Warm reset, WDG reset, and system reset can provide more flexibility regarding reset domains through
REG_LSYS_SW_RST_CTRL
. The register definition is located insysreg_lsys.h
.PD_RTC is only reset when a POR reset occurs within that power domain.
Obtaining Boot Reason
User can obtain the boot reason using the BOOT_Reason()
function. Refer to Boot reason.
Preserving Pre-reset Information
User can store critical data in backup registers or Retention RAM located in the AON region to prevent data loss due to reset.
Note
The following reset types will still cause data loss in backup registers or Retention RAM:
chipen
POR reset
Backup Registers
RealTek provides 4 32-bit backup registers: BKUP_REG0()
, BKUP_REG1()
, BKUP_REG2()
, and BKUP_REG3()
for use. User can manipulate these registers using the provided APIs.
Note
The system may use certain bits in the backup registers. User should search the SDK to confirm if a specific bit is already in use before using it.
API
BKUP_Write
Item |
Description |
---|---|
Function |
Write a value to the corresponding backup register |
Params |
|
Return |
None |
BKUP_Read
Item |
Description |
---|---|
Function |
Read the value from the corresponding backup register |
Params |
|
Return |
The value of the corresponding backup register |
BKUP_Set
Item |
Description |
---|---|
Function |
Set specific bits in the corresponding backup register |
Params |
|
Return |
None |
BKUP_Clear
Item |
Description |
---|---|
Function |
Clear specific bits in the corresponding backup register |
Params |
|
Return |
None |
Retention RAM
User can use the RRAM_DEV
variable to store data in Retention RAM. The structure definition of this variable is RRAM_TypeDef
, located in sysreg_lsys.h
. Its structure member RRAM_USER_RSVD
can be freely used by users.
Note
It is recommended that users prioritize using backup registers and only use Retention RAM when dealing with larger data volumes.
Software Reset Trigger Methods
User can execute a system reset by calling the System_Reset()
function or by issuing a command. The definition of the System_Reset()
function is as follows:
System_Reset
Item |
Description |
---|---|
Function |
Trigger a system software reset |
Params |
None |
Return |
None |
Alternatively, the following command can be issued to any CPU to trigger a system software reset:
AT+RST