Features

• Input Functionality

  • Debounce Feature:

    Input pins support debounce functionality to effectively prevent erroneous signals caused by bouncing.

  • Interrupt Support:

    • Level Trigger

    • Edge Trigger

    • Dual-edge Trigger

• Output Functionality

  • Single Pin Output Configuration:

    Supports setting the output state of a specific pin individually.

  • Simultaneous Multiple Pin Configuration:

    Multiple pins of the same port can be configured for output simultaneously.

Debounce Feature

Debounce Clock

• The debounce clock source is dbclk_src, with the output debounce clock dbclk defined as: dbclk = dbclk_src / (div + 1) .

  Here, div is an adjustable division factor.

  The debounce clock source for the chip is as follows:

  RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730ERTL8721F

  • 32.768KHz;

  • OSC4MHz。

Filtering Capability

• Glitch signals shorter than 1 debounce clock cycle can be filtered out.

• Glitch signals lasting between 1 to 2 debounce clock cycles are uncertain.

• Glitch signals longer than 2 debounce clock cycles cannot be filtered out.

Port Filtering Consistency

• For different pins on the same port, the div is shared, ensuring consistent debounce clock.

Attention

Using the debounce feature introduces input signal processing delay. This may slow system response, particularly in scenarios requiring fast response such as interrupts and wake-up operations.

Interrupt Types

• Level Trigger: Supports interrupt triggering via level state (high or low level).

• Edge Trigger: Supports interrupt triggering on rising or falling edges.

• Dual-edge Trigger: Supports triggering on both rising and falling edges.

Note

To avoid false triggering of interrupts when switching the edge trigger type, enable the interrupt only after a two-cycle debounce clock delay.

Output Race Condition Protection

GPIO outputs are controlled by port (PORT), and controlling the level state of a specific GPIO pin is a three-step operation in assembly: read, modify, write. If multiple threads control outputs on the same port group, a race condition may occur.

To mitigate this risk, both software and hardware protection methods are provided depending on the chip used:

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730ERTL8721F

Software Protection

• Use the GPIO_WriteBit_Critical() API instead of the GPIO_WriteBit() operation.

• Locks resources at the software layer to avoid race conditions in multi-threaded or interrupt contexts.

Usage Examples

The SDK provides two types of feature examples to help developers understand and utilize GPIO functionality:

• mbed Examples

  • Path: {SDK}\component\example\peripheral\mbed\GPIO\{demo}

  • Demonstrates how to implement GPIO control in the mbed environment.

• raw Examples

  • Path: {SDK}\component\example\peripheral\raw\GPIO\{demo}

  • Demonstrates direct GPIO control without abstraction layers.

A brief description of the raw examples:

• raw_gpio_rw demonstrates using the GPIO read/write API;

• raw_gpio_port demonstrates using the GPIO Port read/write API;

• raw_gpio_edge_irq demonstrates configuring GPIO to trigger edge interrupts;

• raw_gpio_level_irq demonstrates configuring GPIO to trigger level interrupts.

Note

To understand the chips supported by the examples, please refer to the README.md file in the example path.

API Reference

For detailed information on using related APIs, refer to {SDK}\component\soc\amebaxxxx\fwlib\include\ameba_gpio.h.