Introduction

The Universal Asynchronous Receiver/Transmitter (UART) offers a flexible means of full-duplex data exchange with external equipment, requiring an industry-standard NRZ asynchronous serial data format. It offers a very wide range of baud rates using a fractional baud rate generator. Low power Rx mode is implemented by monitoring Rx baud rate error and own frequency drift.

Features

• UART x 5

  • Three general UART interfaces: UART0/UART1/UART2

  • One internal BT UART interface: UART3_BT

  • One specific UART as LOGUART

• Various UART format: 1 start bit, 7/8 data bits, 0/1 parity bit and 1/2 stop bits

• Separated clocks for Tx path and Rx path

  • Tx path: XTAL 40MHz

  • Rx path: XTAL 40MHz, OSC 2MHz

• Fractional baud rate

  • Up to 8Mbps within high-speed mode (XTAL 40MHz)

  • Up to 115.2Kbps within low-power mode (OSC 2MHz)

• Asynchronous Transmit/Receive FIFO

• Configurable Auto Flow Control

• Interrupt control and error detection

• IrDA (SIR mode) encoder and decoder module

• Loop-back mode for test

• Low power mode for Rx path

• Monitor and elimination of Rx baud rate error and own frequency drift automatically for Rx path

• UART Rx timeout mechanism

• DMA interface for DMA transfer

  • DMA as DMA TRx flow controller

  • UART as DMA Rx flow controller

• Operation mode

  • Polling mode

  • Interrupt mode

  • DMA mode

Block Diagram

The block diagram of UART is illustrated below.

The UART consists of several sub-modules, which provide the following functions:

• dma_intf

  • DMA control unit

  • Interface with GDMA module

• tx_fifo

  • Asynchronous FIFO

  • \(16 * 11\) bits for UART0/1 and \(32 * 11\) bits for UART3_BT

• xmitckt

  • Shift register

  • Generate UART format data

  • Support fractional baud rate

• irda_sir_encoder

  • SIR encoder of UART Tx data

• rx_fifo

  • Asynchronous FIFO

  • \(64 * 11\) bits for UART0/1 and \(32 * 11\) bits for UART3_BT

• recvckt

  • Receive UART format data

  • Error detection

  • Interrupt control

  • Support fractional baud rate

  • Oscillator (OSC) clock for low power

  • Monitor and eliminate Rx baud rate error and own frequency drift

• irda_sir_decoder

  • SIR decoder of UART Rx data

• apb_slv_wrap

  • APB3 bus interface

• regmng

  • Register control unit

Functional Description

This section describes the functional operation of the UART.

UART Serial Protocol

Because the serial communication between the UART and the selected device is asynchronous, additional bits (start bit and stop bit) are added to the serial data to indicate the beginning and end. Utilizing these bits allows two devices to be synchronized. This structure of serial data accompanied by start and stop bits is referred to as a character, as shown below.

Serial data format

An additional parity bit may be added to the serial character. This bit appears after the last data bit and before the stop bit(s) in the character structure to provide the UART with the ability to perform simple error checking on the received data. The UART Line Control Register (LCR) is used to control the serial character characteristics. The individual bits of the data word (7 or 8 bits) are sent after the start bit, starting with the least-significant bit (LSB). These are followed by the optional parity bit (odd parity, even parity or stick parity), followed by the stop bit(s), which can be 1 or 2.

IrDA (SIR) Protocol

The Infrared Data Association (IrDA) Serial Infrared (SIR) mode supports bi-directional data communication with remote devices using infrared radiation as the transmission medium. IrDA 1.0 SIR mode specifies a maximum baud rate of 115.2K.

The data format is similar to the standard UART data format. Each data character is sent serially, beginning with a start bit, followed by 7 or 8 data bits and ending with 1 or 2 stop bits. The parity bit is invalid in IrDA mode, try to enable parity with the Line Control Register (LCR) will add one wrong parity bit in the serial data. When UART is configured to support IrDA, it can be enabled with MISC Control Register (MISCR) bit 0.

Transmitting a single infrared pulse signals a logic zero, while a logic one is represented by not sending a pulse. Thus, each new character begins with an infrared pulse for the start bit. However, received data is inverted from transmitted data due to the infrared pulses energizing the photo transistor base of the IrDA receiver, pulling its output low. This inverted transistor output is then fed to the UART Rx port, which then has correct UART polarity. The IrDA output and input logic can be reversed by setting MISCR bit19 and bit20. The width of each pulse is 3/16ths of a normal serial bit time. The IrDA Tx width can also be adjusted by configuring register SIR_TX_PWC0 with software. The timing diagram of the IrDA SIR Data format in comparison with the standard UART format is shown below:

Relationship between IrDA signal and UART signal

Interrupt

The UART supports both individual and combined interrupt requests, which can both be masked as well. The combined interrupt request is the ORed result of all other UART interrupts after masking. The system designer has the choice of routing individual interrupt requests or only the combined interrupt request to the Interrupt Controller. The UART interrupts are described as follows:

• Received Data Available Interrupt (ERBFI) - Set when Rx FIFO Trigger Level is reached or Rx FIFO is full. Rx FIFO Trigger Level can be configured by software in FIFO Control Register (FCR, bit[7:6]), defines the level of receiver FIFO entries at which an interrupt is generated. This interrupt is cleared by hardware when Rx FIFO entries decrease under the trigger level. Bit RXFIFO_INT in Line Status Register (LSR, bit8) will be set when this interrupt happens.

• Transmitter FIFO Empty Interrupt (ETBEI) - Set when the transmit FIFO is empty. This interrupt is cleared by hardware when data is written into the Tx FIFO buffer. Bit TX_EMPTY in Line Status Register (LSR, bit5) will be set when this interrupt happens.

• Receiver Line Status Interrupt (ELSI) - Set when overrun, parity error, framing error or break condition is detected on the Rx line. This interrupt remains set until the Receiver Line Status Interrupt Clear Flag (RLSICF) in Interrupt Clear Register (ICR) is set by the user. Bit OVR_ERR (LSR, bit1), bit PAR_ERR (LSR, bit2), bit FRM_ERR (LSR, bit3) and bit BREAK_INT (LSR, bit4) will be set accordingly when detecting overrun, parity error, framing error and break condition on the Rx line. Bit RXFIFO_ERR (LSR, bit7) will be set when any of the events mentioned before happens. Writing 1 to RLSICF will also clear RXFIFO_ERR status.

• Modem Status Interrupt (EDSSI) - Set when a falling edge is detected on CTS line with hardware auto-flow enabled. This interrupt remains set until the Modem Interrupt Clear Flag (MICF) in ICR is set by the user. Bit MODEM_INT (LSR, bit11) will be set when this interrupt happens.

• RX Path Monitor Done Interrupt (EMDI) - Set when monitor process is over with Rx path monitor function enabled. This interrupt remains set until the Monitor Done Interrupt Clear Flag (MDICF) in ICR is set by the user. Bit MONITOR_DONE_INT (LSR, bit10) will be set when this interrupt happens.

• RX Timeout Interrupt (ETOI) - Set when no character has been input to the Rx FIFO or read from it before time expires when there’s at least one character in the Rx FIFO. Time can be set in Rx Path Control Register ( RX_PATH_CTRL, bit[31:16]). This interrupt remains set until the Timeout Interrupt Clear Flag (TOICF) in ICR is set by the user. Bit TIMEOUT_INT (LSR, bit9) will be set when this interrupt happens.

• RXFIFO Empty Timeout Interrupt (ERETI) - Set when Rx FIFO stays empty until time expires. Time can be set in RXFIFO Empty Interrupt Timeout Threshold Register ( TH_RETI, bit[19:0]). This interrupt remains set until the RXFIFO Empty Timeout Interrupt Clear Flag (RETICF) in ICR is set by the user. Bit RE_TIMEOUT_INT (LSR, bit13) will be set when this interrupt happens.

• RX Noise Detected Interrupt (ERXNDI) - Set when Rx debouncer has detected noise. This interrupt remains set until the Rx Noise Detected Interrupt Clear Flag (RXNDICF) in ICR is set by the user. Bit RXND_INT (LSR, bit12) will be set when this interrupt happens.

Auto Flow Control

The UART can be configured to work under hardware data flow control, which is comprised of Auto RTS and Auto CTS. Enable Auto Flow Control by asserting AFE bit in the Modem Control Register (MCR, bit5). Auto RTS and Auto CTS are described as follows:

Auto RTS

Auto RTS becomes active when the following occurs:

• Auto Flow Control is enabled (MCR[5] is set)

• RTS output is enabled (MCR[1] is set)

• FIFOs are enabled (FCR[0] is set)

When Auto RTS is enabled (active), RTS signal is forced inactive (high) automatically once the receiver FIFO reaches Rx_FIFO_Trigger_Level . When RTS output is connected to the CTS input of the sending device (e.g. another UART), the sending device stops sending serial data until the receiver FIFO has available space.

The optional receiver FIFO threshold values are 1, 1/4, 1/2, and 2 less than full. Since one additional character may be transmitted to the UART after RTS has become inactive as shown in Auto RTS timing (due to data in the other UART has already entered the transmitter block before it recognize the deassertion of RTS), setting the threshold to 2 less than full makes the best use of the FIFO with a safety zone of one character.

Once the receiver FIFO level is below (Rx_FIFO_Trigger_Level - 2) by reading the Receiver Buffer Register (RBR_OR_THR), RTS becomes active (low) again, signaling the other UART to continue sending data. It is important to note that even if everything else is selected and the correct MCR bits are set, if the FIFOs are disabled through FCR bit0, Auto Flow Control is also disabled. When Auto RTS is not implemented or disabled, RTS is controlled solely by MCR bit1. The following figure shows a timing diagram of Auto RTS operation.

Auto RTS timing

Note

When Rx_FIFO_Trigger_Level is configured as 1, RTS signal will become active(low) when the receiver FIFO is completely empty.

When Rx_FIFO_Trigger_Level is configured as 2 less than full, RTS signal will become active(low) when the receiver FIFO level is below 2 less than full.

UART0/UART1/UART2/UART3_BT all support Auto RTS while only UART0 and UART3_BT are designed with RTS pin.

Auto CTS

Auto CTS becomes active when the following occurs:

• Auto Flow Control is enabled (MCR[5] is set)

• RTS output is enabled (MCR[1] is set)

• FIFOs are enabled (FCR[0] is set)

• SIR mode is disabled (MISCR[0] bit is cleared)

When Auto CTS is enabled (active), the UART transmitter is disabled automatically once the CTS input becomes inactive (high). This prevents overflowing the FIFO of the receiving device (e.g. another UART). If the CTS input is not inactivated before the middle of the last stop bit, another character is transmitted before the transmitter is disabled. While the transmitter is disabled, the transmitter FIFO can still be written to, and even overflowed. Therefore, when using this mode, the following happens:

• The UART status register can be read to check if the transmit FIFO is full (LSR bit6 = 0) or

• The Programmable ERBFI Interrupt can be enabled to access the FIFO full status via the Line Status Register (LSR).

When using the FIFO full status, the software can poll this before each write to the transmitter FIFO. When the CTS input becomes active (low) again, transmission resumes. It is important to note that even if everything else is selected, if the FIFOs are disabled via FCR[0], Auto Flow Control is also disabled. When Auto CTS is not implemented or disabled, the transmitter is unaffected by CTS. A Timing Diagram showing Auto CTS operation can be seen below:

Auto CTS timing

Note

UART0/UART1/UART2/UART3_BT all support Auto CTS while only UART0 and UART3_BT are designed with CTS pin.

DMA Flow Control

GDMA is always DMA flow controller for UART Tx, while either GDMA or UART can both be DMA flow controller for UART Rx. Only Rx DMA mode is illustrated here.

GDMA as DMA flow controller

When GDMA is DMA flow controller as shown below, GDMA sets expected block length before blocks transfer, and terminates block transfer when Rx length is equal to block length. Rx_dma_req is asserted when Rx size in Rx FIFO is not less than burst size, and rx_dma_single is asserted when Rx FIFO is not empty. Rx_dma_ack signal is asserted after the data phase of the last AHB transfer (single or burst) in the current transaction has been completed. When GDMA is the flow controller, rx_dma_last is not sampled and is ignored.

Specially, when data transfer is unpredictable, e.g. number of rx data is unknown, it is suggested to set GDMA as flow controller. UART rx burst size and GDMA burst transaction size shall both be set to 1, GDMA block transfer size shall be set to a larger value than expected number or 65535(max value) directly, and RXFIFO Empty Timeout Interrupt (ERETI) shall be enabled to notify transaction has been halted for a while. Once RXFIFO Empty Timeout Interrupt (ERETI) is triggered, RXDMA_EN will be cleared automatically by hardware and DMA request will not be set even when new data comes into RX FIFO. Number of data read from RX FIFO by DMA can be got in register UART_RX_BYTE_CNT. If new data comes after interrupt arises, user can read the remaining RX FIFO data manually. DMA should also be disabled by user.

UART as DMA flow controller

When UART is DMA flow controller as shown below, UART asserts rx_dma_last to terminate block transfer when UART has received the whole packet. The finish flag is defined that no new Rx character comes in for UART_RX_BYTE_CNT time in register UART_RX_PATH_CTRL after the last Rx character.

Rx Path Monitor Function

UART Rx path supports fractional baud rate generator and it can monitor and eliminate Rx baud rate error and own frequency drift. Fractional baud rate and baud rate monitor cannot be used simultaneously.

When the monitor function is enabled (UART_MON_BAUD_CTRL, bit[0]), software sets the original cycle number according to default baud rate, then Rx circuit counts total cycle number M of N bit duration, so average cycle number per bit duration \(L=M/N\), the maximum value of N is 127. Hardware will replace the original cycle number per bit with the newly calculated value L, thus baud rate error from peer device and own frequency deviation can be almost eliminated.

Note

When Rx path monitor function is enabled, baud rate should not be greater than 1/17 of current LP clock frequency.

Clock Structure of Rx Path

The clock structure of Rx path for UART0, UART1, UART2, UART3_BT and LOGUART is similar. The following figure is the clock structure of UARTx Rx clock, where x can be from 0 to 2. The cksl_uart signal in REG_CKSL_GRP0 register decides clock for UARTx Rx path.

UART Rx Debounce

UART supports Rx debounce to filter glitches in Rx signals. The function could be enabled by asserting DBNC_FEN bit in UART_RXDBCR register. Rx debounce clock source is the same with Rx clock source, which could be XTAL 40MHz, XTAL 20MHz or OSC 4MHz. DBNC_CYC field in UART_RXDBCR register is set to debounce Rx signals with different glitches.

When DBNC_FEN bit in UART_RXDBCR register is asserted, glitches shorter than DBNC_CYC debounce clock cycles will be filtered as shown below. Meanwhile, delay will be introduced to Rx signal for (DBNC_CYC + 2) debounce clock cycles.

UART Rx debounce

UART3_BT Used as Normal UART

UART3_BT is used for internal BT UART by default. For normal UART usage, set the relevant register described below.

• Name: REG_LSYS_BT_CTRL0

• Size: 32 bits

• Base Address: 0x41008000

• Address offset: 0x280

• Read/write access: read/write

Bit	Name	Access	Reset	Description
19	BT_USE_EXT_UART	R/W	0x0	1: BT use external uart 0: BT use internal uart

Registers

The following table lists the memory map of the UART registers. The base addresses are:

• UART0: 0x4100_C000

• UART1: 0x4100_D000

• UART2: 0x4100_E000

• UART3_BT: 0x4100_E000

• LOGUART: 0x4100_F000

Name	Address offset	Access	Description
REG_UART_DLL	000h	R/W	The low 8 bits of divisor coefficient only valid when the DLAB bit of LCR bit[7] = 1
REG_UART_IER	004h	R/W	Generate enable and disable interrupt by the UART, only valid when the DLAB bit of LCR bit[7] = 0.
REG_UART_IIR	008h	R	Interrupt source indication
REG_UART_LCR	00Ch	R/W	Set the general communication parameters
REG_UART_MCR	010h	R/W	It is used to perform handshaking actions with the attached device.
REG_UART_LSR	014h	R	Indicate the current state of communication and errors
REG_UART_MSR	018h	R	It contains information about the four incoming modem control lines on the device
REG_UART_SCR	01Ch	R/W	It is used to store information of TX
REG_UART_STS	020h	R/W	Indicate the information of TX baud rate
REG_UART_RBR_OR_UART_THR	024h	R/W	The buffers of received data / The buffers of transmitted data
REG_UART_MISCR	028h	R/W	Provide DMA and IrDA related information
REG_UART_SIR_TX_PWC0	02Ch	R/W	Indicates the shift value of SIR TX pulse
REG_UART_SIR_RX_PFC	030h	R/W	Indicates the threshold of SIR Rx pulse
REG_UART_BAUD_MON	034h	R/W	Monitor the baud rate of Rx pulse
REG_UART_DBGR	03Ch	R	Debug
REG_UART_RX_PATH_CTRL	040h	R/W	Monitor the Rx baud rate error and Rx baudrate factor setting
REG_UART_MON_BAUD_CTRL	044h	R/W	Monitor the baud rate of Rx path
REG_UART_MON_BAUD_STS	048h	R/W	Monitor the baud rate of Rx path
REG_UART_MON_CYC_NUM	04Ch	R	Monitored clock cycle number of Rx path
REG_UART_RX_BYTE_CNT	050h	R/W	Count the number of data read from rxfifo (byte)
REG_UART_FCR	054h	R/W	FIFO control
REG_UART_ICR	058h	R/W	Interrupt clear
REG_UART_RXDBCR	05Ch	R/W	Added in MP version, not existed in Test chip version
REG_UART_TH_RETI	060h	R/W
REG_UART_DUMMY	064h	R

REG_UART_DLL

• Name : UART divisor length register

• Size : 32

• Address offset : 000h

• Read/write access : R/W

The low 8 bits of divisor coefficient only valid when the DLAB bit of LCR bit[7] = 1

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7:0	BAUD	R/W	0x0	The low 8 bits of divisor coefficient (not used)

REG_UART_IER

• Name : UART interrupt enable register

• Size : 32

• Address offset : 004h

• Read/write access : R/W

Generate enable and disable interrupt by the UART, only valid when the DLAB bit of LCR bit[7] = 0.

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7	ERETI	R/W	0x0	RXFIFO_EMPTY_TIMEOUT interrupt enable
6	ERXNDI	R/W	0x0	Rx noise detected interrupt enable
5	ETOI	R/W	0x0	Rx timeout interrupt enable
4	EMDI	R/W	0x0	Rx path monitor done interrupt enable
3	EDSSI	R/W	0x0	Modem Status Interrupt (EDSSI) (modem status transition) ena ble
2	ELSI	R/W	0x0	Receiver Line Status Interrupt (ELSI) (receiver line status) enable
1	ETBEI	R/W	0x0	Transmitter FIFO Empty interrupt (ETBEI) (Tx FIFO empty) ena ble
0	ERBI	R/W	0x0	Received Data Available Interrupt (ERBFI) (Rx trigger) enabl e

REG_UART_IIR

• Name : UART interrupt identification register

• Size : 32

• Address offset : 008h

• Read/write access : R

Interrupt source indication

Bit	Symbol	Access	Reset	Description
31:1	RSVD	R	-	Reserved
0	INT_PEND	R	0x1	0: pending, and the IIR contents may be used as a pointer to the appropriate interrupt service routine 1: no interrupt is pending

REG_UART_LCR

• Name : UART line control register

• Size : 32

• Address offset : 00Ch

• Read/write access : R/W

Set the general communication parameters

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7	DLAB	R/W	0x0	Divisor Latch Access bit, and control the accessibility of t he DLL, DLM and IER registers 0: The divisor latches not accessible; IER accessible 1: The divisor latches accessible; DLL and DLM accessible Note THR/RBR don’t care the value of dlab bit.
6	BRCTL	R/W	0x0	Break Control bit 0: break signal disable 1: break signal enable (logic ‘0’)
5	STKP	R/W	0x0	Stick Parity bit 0: Not stick parity, the parity type is ODD or EVEN (depen ding on eps) 1: Stick parity - eps=1: low parity (1’b0) - eps=0: high parity (1’b1)
4	EPS	R/W	0x0	Even Parity selection 0: Odd parity, the number of Logic ‘1’ is odd 1: Even parity, the number of Logic ‘1’ is even
3	PEN	R/W	0x0	Parity Enable 0: No parity bit 1: Parity bit is generated on each outgoing character and is checked on each incoming one
2	STB	R/W	0x0	Stop bits length selection 0: 1 stop bit 1: 2 stop bits Note The receiver always checks the first stop bit only.
1	RSVD	R	-	Reserved
0	WLS0	R/W	0x1	Word length selection 0: 7 bits data 1: 8 bits data

REG_UART_MCR

• Name : UART modem control register

• Size : 32

• Address offset : 010h

• Read/write access : R/W

It is used to perform handshaking actions with the attached device.

Bit	Symbol	Access	Reset	Description
31:6	RSVD	R	-	Reserved
5	AFE	R/W	0x0	Auto flow control enable
4	LOOP_EN	R/W	0x0	LoopBack mode 0: Normal operation mode 1: Loopback mode
3	OUT2	R/W	0x0	Auxiliary output 2 Bit[3] affects the OUT2_ output in a manner identical to tha t described above set to 0 In loopback mode, connected to Data Carrier Detect (DCD).
2	OUT1	R/W	0x0	Auxiliary output 1 Bit3 affects the OUT1_ output in a manner identical to that described above set to 0 In loopback mode, connected to Ring Indicator (RI)
1	RTS	R/W	0x0	Request to Send (RTS) signal control 0: rts is logic 1. 1: rts is logic 0. This bit controls the RTS_ output. Bit[1] affects the RTS_ o utput in a manner identical to that described above set to 0 .
0	DTR	R/W	0x0	0: dtr is logic 1 1: dtr is logic 0 This bit controls the DTR output

REG_UART_LSR

• Name : UART line status register

• Size : 32

• Address offset : 014h

• Read/write access : R

Indicate the current state of communication and errors

Bit	Symbol	Access	Reset	Description
31:14	RSVD	R	-	Reserved
13	RE_TIMEOUT_INT	R	0	This bit is only set when rxfifo empty timeout interrupt is enabled(ERETI is set) 1:Rxfifo is empty for longer than TH_RETI
12	RXND_INT	R	0	This bit is only set when RX debouncer has detected noise 1: Rx path noise detected interrupt
11	MODEM_INT	R	0	This bit is only set when Modem status pending 1: Modem interrupt
10	MONITOR_DONE_INT	R	0	This bit is only set when Rx Path Monitor Done interrupt is enabled(EMDI is set) 1: Rx path monitor done
9	TIMEOUT_INT	R	0	This bit is only set when Rx Timeout interrupt is enabled(ET OI is set) 1: at least one character in the FIFO but no character has been input to the FIFO or reading from it for the time dur ation, which depends on the value in register REG_RX_PATH_ CTRL[31:16]
8	RXFIFO_INT	R	0	This bit is only set when Received Data Available Interrupt interrupt is enabled(ERBI is set) 1: FIFO Trigger level reached or Rx FIFO full
7	RXFIFO_ERR	R	0	Uart_rx_error, depending on the FIFO control register (FCR) bit[0] 0: clear when the CPU reads the LSR, if there are no subse quent errors in the FIFO. 1: parity error, overrun error, framing error or break ind ication in the FIFO.
6	TX_NOT_FULL	R	1	TXFIFO not full indicator
5	TX_EMPTY	R	1	TXFIFO empty indicator
4	BREAK_INT	R		Break Interrupt (BI) indicator 0: No break condition in the current character 1: The received data input held in the Spacing ( logic 0) state is longer than a full word transmission time
3	FRM_ERR	R		Framing Error (FE) indicator 0: No framing error in the current character 1: The received character does not have a valid stop bit
2	PAR_ERR	R		Parity Error (PE) indicator 0: No parity error in current character 1: The received character does not have the correct parity bit
1	OVR_ERR	R		Overrun Error (OE) indicator 0: No Overrun state 1: The transmission is continue although the Rx FIFO is fu ll
0	DRDY	R		0: No characters in the Receiver FIFO 1: At least one character has been received and transferre d into the FIFO

REG_UART_MSR

• Name : UART modem status register

• Size : 32

• Address offset : 018h

• Read/write access : R

It contains information about the four incoming modem control lines on the device

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7	R_DCD	R		Complement of the DCD input or equals to Out2 in loopback mo de.
6	R_RI	R		Complement of the RI input or equals to Out1 in loopback mod e.
5	R_DSR	R		Complement of the DSR input or equals to DTR in loopback mod e.
4	R_CTS	R		Complement of the CTS input or equals to RTS in loopback mod e.
3	D_DCD	R		0: Otherwise 1: The DCD line has changed its state
2	TERI	R		0: Otherwise 1: The RI line has changed its state from low to high stat e
1	D_DSR	R		0: Otherwise 1: The DSR line has changed its state
0	D_CTS	R		0: Otherwise 1: The CTS line has changed its state

REG_UART_SCR

• Name : UART scratch pad register

• Size : 32

• Address offset : 01Ch

• Read/write access : R/W

It is used to store information of TX

Bit	Symbol	Access	Reset	Description
31:27	RSVD	R	-	Reserved
26:16	XFACTOR_ADJ	R/W	0x0	One factor of Baud rate calculation for TX path
15:13	RSVD	R	-	Reserved
12:8	DBG_SEL	R/W	0x0	Debug port selection
7	SCRATCH_7	R/W	0x0	Clear rx break signal interrupt status
6:0	SCRATCH_6_0	R/W	0x30	Bit[6]: rx break signal interrupt enable Bit[5]: fl_set_bi_err Bit[4]: fl_frame_err Bit[3]: pin_lb_test Bit[2:0]: reserved

REG_UART_STS

• Name : UART STS register

• Size : 32

• Address offset : 020h

• Read/write access : R/W

Indicate the information of TX baud rate

Bit	Symbol	Access	Reset	Description
31:24	RSVD	R	-	Reserved
23:4	XFACTOR	R/W	0x1047	Factor of Baud rate calculation for Tx path
3:0	RSVD	R	-	Reserved

REG_UART_RBR_OR_UART_THR

• Name : UART receiver buffer register/UART transmitter holding register

• Size : 32

• Address offset : 024h

• Read/write access : R/W

The buffers of received data / The buffers of transmitted data

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7:0	DATABIT	R/W	0x0	UART_RBR’s Rx data bits or UART_THR’s Tx data bit[7:0] Note Bit[0] is the least significant bit. It is the first bit serially received/transmitted.

REG_UART_MISCR

• Name : UART MISC control register

• Size : 32

• Address offset : 028h

• Read/write access : R/W

Provide DMA and IrDA related information

Bit	Symbol	Access	Reset	Description
31	RSVD	R	-	Reserved
30	CLR_DUMMY_FLAG	R/W	0x0	Indicate the clearing of dummy data
29:22	DUMMY_DATA	R/W	0x0	Store dummy data, when UART is DMA flow controller, dummy da ta is padded for last RXDMA burst request.
21	RXDMA_OWNER	R/W	0x0	0: GDMA 1: UART, interrupt enable signal other than erpd should be masked
20	IRDA_RX_INV	R/W	0x0	Irda_rx_i reverse input enable
19	IRDA_TX_INV	R/W	0x0	Irda_tx_o reverse output enable
18:11	RXDMA_BURSTSIZE	R/W	0x4	RXDMA burstsize, maximum value is 16.
10:3	TXDMA_BURSTSIZE	R/W	0x4	TXDMA burstsize, maximum value is 16.
2	RXDMA_EN	R/W	0x0	RXDMA enable, valid when dma_mode in FCR is 1’b1
1	TXDMA_EN	R/W	0x0	TXDMA enable, valid when dma_mode in FCR is 1’b1
0	IRDA_ENABLE	R/W	0x0	0: UART mode only 1: UART is co-work with IRDA SIR mode

REG_UART_SIR_TX_PWC0

• Name : UART IRDA SIR TX pulse width control 0 register

• Size : 32

• Address offset : 02Ch

• Read/write access : R/W

Indicates the shift value of SIR TX pulse

Bit	Symbol	Access	Reset	Description
31	UPPERBOUND_SHIFTRIGHT	R/W	0x0	0: Shift left, minus offset value of upperbound_shiftval 1: Shift right, plus offset value of upperbound_shiftval
30:16	UPPERBOUND_SHIFTVAL	R/W	0x0	The shift value of SIR TX pulse’s right edge
15	LOWBOUND_SHIFTRIGHT	R/W	0x0	0: Shift left, minus offset value of lowbound_shiftval 1: Shift right, plus offset value of lowbound_shiftval
14:0	LOWBOUND_SHIFTVAL	R/W	0x0	The shift value of SIR TX pulse’s left edge

REG_UART_SIR_RX_PFC

• Name : UART IRDA SIR Rx pulse filter control register

• Size : 32

• Address offset : 030h

• Read/write access : R/W

Indicates the threshold of SIR Rx pulse

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:1	R_SIR_RX_FILTER_THRS	R/W	0x0	The threshold of SIR Rx filter, Rx pulse is valid only when Rx pulse width is larger than the threshold.
0	R_SIR_RX_FILTER_EN	R/W	0x0	IrDA SIR Rx filter enable

REG_UART_BAUD_MON

• Name : UART baud monitor register

• Size : 32

• Address offset : 034h

• Read/write access : R/W

Monitor the baud rate of Rx pulse

Bit	Symbol	Access	Reset	Description
31	TOGGLE_MON_EN	R/W	0x0	Toggle monitor enable
30	MON_DATA_VLD	R		Indicate valid monitoring data
29:24	FALLING_THRESH	R/W	0x7	Indicate the threshold of Rx data rising edge
23:12	MIN_LOW_PERIOD	R		Minimum space of consecutive logic ‘0’ of Rx data
11:0	MIN_FALL_SPACE	R		Minimum space of adjacent falling edge of Rx data

REG_UART_DBGR

• Name : UART debug register

• Size : 32

• Address offset : 03Ch

• Read/write access : R

Debug

Bit	Symbol	Access	Reset	Description
31:0	DBG_UART	R		The output value of debug port, depending on dbg_sel value i n SCR[2:0]

REG_UART_RX_PATH_CTRL

• Name : UART Rx path control register

• Size : 32

• Address offset : 040h

• Read/write access : R/W

Monitor the Rx baud rate error and Rx baudrate factor setting

Bit	Symbol	Access	Reset	Description
31:16	R_RXTO_THRS	R/W	0x40	Indicate the timeout threshold of Rx path, unit in one-bit time
15:14	RSVD	R	-	Reserved
13:3	RXBAUD_ADJ_10_0	R/W	0x0	One factor of Baud rate calculation for Rx path, similar wit h xfactor_adj
2	R_RST_NEWRX_N	R/W	0x0	Reset new Rx path, low active
1:0	RSVD	R	-	Reserved

REG_UART_MON_BAUD_CTRL

• Name : UART monitor baud rate control register

• Size : 32

• Address offset : 044h

• Read/write access : R/W

Monitor the baud rate of Rx path

Bit	Symbol	Access	Reset	Description
31:30	RSVD	R	-	Reserved
29	R_UPD_OSC_IN_XTAL	R/W	0x0	Update parameter r_cycnum_perbit_osc (during the update of p arameter r_cycnum_perbit_xtal) enable
28:9	R_CYCNUM_PERBIT_OSC	R/W	0x0	Indicate the average OSC clock cycle number of one bit, for Rx path OSC clk Note SW sets the initial value, HW updates it depending on the monitor result.
8:1	R_BIT_NUM_THRES	R/W	0x0	Indicate the bit number threshold of one monitor period, max value is 127
0	R_MON_BAUD_EN	R/W	0x0	Monitor Rx baud enable

REG_UART_MON_BAUD_STS

• Name : UART monitor baud rate status register

• Size : 32

• Address offset : 048h

• Read/write access : R/W

Monitor the baud rate of Rx path

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28:21	RO_MON_TOTAL_BIT	R	0x0	Indicate the number of bits actually monitored
20	RO_MON_RDY	R	0x0	Indicate the finish of calculation of actual cycle number pe r bit, it’s cleared when r_mon_baud_en is 0
19:0	R_CYCNUM_PERBIT_XTAL	R/W	0x0	Indicate the fractional xtal clock cycle number of one bit, for Rx path xtal clk Note SW sets the initial value, HW updates it depending on the monitor result.

REG_UART_MON_CYC_NUM

• Name : UART monitored cycle number register

• Size : 32

• Address offset : 04Ch

• Read/write access : R

Monitored clock cycle number of Rx path

Bit	Symbol	Access	Reset	Description
31:28	RSVD	R	-	Reserved
27:0	RO_MON_TOTAL_CYCLE	R		Indicate the number of clock cycle actually monitored

REG_UART_RX_BYTE_CNT

• Name : UART Rx data byte count register

• Size : 32

• Address offset : 050h

• Read/write access : R/W

Count the number of data read from rxfifo (byte)

Bit	Symbol	Access	Reset	Description
31:17	RSVD	R	-	Reserved
16	CLR_RX_BYTE_CNT	R/W		Write 1 to clear ro_rx_byte_cnt
15:0	RO_RX_BYTE_CNT	R		Count the byte number of data read from rxfifo

REG_UART_FCR

• Name : UART FIFO control register

• Size : 32

• Address offset : 054h

• Read/write access : R/W

FIFO control

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7:6	RECVTRG	R/W	0x3	Define the 16-entries Receiver FIFO Interrupt trigger level (0~15 bytes) 00: 1 byte 01: 16 bytes (FIFO_DEPTH/4) 10: 32 bytes (FIFO_DEPTH/2) 11: 62 bytes (FIFO_DEPTH-2)
5:4	RSVD	R	-	Reserved
3	DMA_MODE	R/W	0x0	Support dma mode (cooperate with DW DDMA in the data path)
2	XMIT_CLR	R/W	0x0	Clear xmitckt
1	RECV_CLR	R/W	0x0	Clear receiving
0	FIFO_EN	R/W	0x1	Error report of RCVR FIFO field enable, only valid when the LSR bit[7] is set to 1.

REG_UART_ICR

• Name : UART interrupt clear register

• Size : 32

• Address offset : 058h

• Read/write access : R/W

Interrupt clear

Bit	Symbol	Access	Reset	Description
31:6	RSVD	R	-	Reserved
5	RETICF	R/W	0x0	Rxfifo empty timeout Interrupt Clear Flag
4	RXNDICF	R/W	0x0	Rx noise Detected Interrupt Flag
3	MDICF	R/W	0x0	Monitor Done Interrupt Flag
2	MICF	R/W	0x0	Modem Interrupt Clear Flag
1	TOICF	R/W	0x0	Timeout Interrupt Clear Flag
0	RLSICF	R/W	0x0	Receiver Line Statue Interrupt Clear Flag Writing 1 to this bit clears PARITY_ERR, OVERRUN_ERR, FRAMIN G_ERR, BREAK_ERR_INT and RXFIFO_ERR in the USART_LSR regist er.

REG_UART_RXDBCR

• Name : UART RX debounce control register

• Size : 32

• Address offset : 05Ch

• Read/write access : R/W

Added in MP version, not existed in Test chip version

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:1	DBNC_CYC	R/W	0xF	Debounce cycles in unit of sclk
0	DBNC_FEN	R/W	0x0	UART RX debounce enable

REG_UART_TH_RETI

• Name : UART rxfifo empty interrupt timeout threshold

• Size : 32

• Address offset : 060h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:28	RSVD	R	-	Reserved
27:0	TH_RETI	R/W	0x0	Set rxfifo empty timeout interrupt, when rxfifo is empty for longer than TH_RETI. Timeout counter works in uart_rclk.

REG_UART_DUMMY

• Name : UART Dummy Register

• Size : 32

• Address offset : 064h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	DUMMY	R	0x0	Rsvd for hw