Inter-integrated Circuit (I2C)

• Introduction
  • Features
  • Block Diagram
• Functional Description
  • Overview
  • I2C Terminology
  • I2C Behavior
  • I2C Protocols
  • Transmit FIFO Management and START, STOP and RESTART Generation
  • Clock Synchronization
  • Multiple Master Arbitration
  • SDA/SCL Filter
  • IC_CLK Frequency Configuration
  • Programmable SDA Hold Time
  • Slave Mode Dual Own Address
• Operation Flow
  • Slave Mode Operation
  • Master Mode Operation
• Registers
  • REG_IC_CON
  • REG_IC_TAR
  • REG_IC_SAR
  • REG_IC_HS_MAR
  • REG_IC_DATA_CMD
  • REG_IC_SS_SCL_HCNT
  • REG_IC_SS_SCL_LCNT
  • REG_IC_FS_SCL_HCNT
  • REG_IC_FS_SCL_LCNT
  • REG_IC_HS_SCL_HCNT
  • REG_IC_HS_SCL_LCNT
  • REG_IC_INTR_STAT
  • REG_IC_INTR_MASK
  • REG_IC_RAW_INTR_STAT
  • REG_IC_RX_TL
  • REG_IC_TX_TL
  • REG_IC_CLR_INTR
  • REG_IC_CLR_RX_UNDER
  • REG_IC_CLR_RX_OVER
  • REG_IC_CLR_TX_OVER
  • REG_IC_CLR_RD_REQ
  • REG_IC_CLR_TX_ABRT
  • REG_IC_CLR_RX_DONE
  • REG_IC_CLR_ACTIVITY
  • REG_IC_CLR_STOP_DET
  • REG_IC_CLR_START_DET
  • REG_IC_CLR_GEN_CALL
  • REG_IC_ENABLE
  • REG_IC_STATUS
  • REG_IC_TXFLR
  • REG_IC_RXFLR
  • REG_IC_SDA_HOLD
  • REG_IC_TX_ABRT_SOURCE
  • REG_IC_SLV_DATA_NACK_ONLY
  • REG_IC_DMA_CR
  • REG_IC_DMA_TDLR
  • REG_IC_DMA_RDLR
  • REG_IC_SDA_SETUP
  • REG_IC_ACK_GENERAL_CALL
  • REG_IC_ENABLE_STATUS
  • REG_IC_DMA_CMD
  • REG_IC_DMA_DATA_LEN
  • REG_IC_DMA_MODE
  • REG_IC_SLEEP
  • REG_IC_DEBUG_SEL
  • REG_IC_OUT_SMP_DLY
  • REG_IC_CLR_ADDR_MATCH
  • REG_IC_CLR_DMA_DONE
  • REG_IC_FILTER
  • REG_IC_SAR2
  • REG_IC_COMP_VERSION
  • REG_IC_DUMMY