Introduction

Introduction

The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter. One 32-bit register contains the seconds, minutes, hours (12- or 24-hour format) expressed in BCD format. One 32-bit register contains the days expressed in binary format. One 8-bit register contains the years expressed in binary format.

Daylight saving time compensation can be performed.

Additional two 32-bit registers contain the programmable alarm seconds, minutes, hours and days. Year information is saved in another register.

A digital calibration feature is available to compensate for some deviation.

Periodic auto-wakeup function can wakeup systems in periodically with programmable period.

After backup domain reset, all RTC registers are protected against possible parasitic write accesses.

As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status which is running mode, low power mode or under reset.

Features

• Time with seconds, minutes, hours (12- or 24-hour format) days and years

• Daylight saving compensation programmable by software

• One programmable alarm with interrupt function. The alarm can be triggered by any combination of the time fields.

• Maskable interrupt/event:

  • Alarm

  • Day threshold

  • Wakeup timer

• Digital calibration circuit

• Register write protection

• Periodic auto-wakeup

Block Diagram

The RTC is connected under APB buses. The total block diagram is shown below.

• rtc_reg

  • Used for RTC configuration

  • Can set alarm, day over interrupt, periodic auto wakeup function

• rtc_clk_rst_gen

  • clk_apre and clk_spre selection

  • Generate almf_rst, dovthf_rst

• rtc_clk_div_apre

  • Divide RTCCLK and generate clk_apre

• rtc_clk_div_spre

  • Divide clk_apre and generate 1Hz clk_spre

  • Digital calibration used to compensate RTCCLK inaccuracy by adding or masking clock cycles at the output of clk_apre

• rtc_counter

  • Calendar seconds, minutes, hours, days count

• rtc_alarm

  • Generate alarm out if the calendar seconds, minutes, hours or days match the values programmed in the alarm registers RTC_ALMR1L and RTL_ALMR1H.

• rtc_ctrl

  • Generate RTC interrupt

  • Generate RTC control signal

• rtc_auto_wakeup

  • Periodic auto wakeup

  • Can set wakeup timer

  • Wakeup timer clock can select RTCCLK or clk_spre

  • Wakeup timer divide two parts

The RTC prescaler diagram is shown below.

RTC Clock Select Diagram

The RTC clock select diagram is shown below.

• When system boots, the default RTC clock source (RTCCLK) is from SDM32K with 0x4200_8010 [5:4] = 0.

• When setting 0x4200_8010 [5:4] = 2’b00/2’b01, it means that SDM32K is selected as RTC clock source.

• When setting 0x4200_8010 [5:4] = 2’b11, it means that EXT32K is selected as RTC clock source.

Functional Description

Clock and Prescaler

A programmable prescaler stage generates a 1Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers.

• A 9-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register.

• A 9-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register.

Note

It is recommended to configure the asynchronous prescaler to a high value to minimize consumption.

Default, the asynchronous prescaler division factor is set to 128, and the synchronous division factor is set to 256, to obtain an internal clock frequency of 1Hz (clk_spre) with 32.768kHz as RTCCLK.

fclk_apre is given by the following formula:

\[f_{clk\_apre} = \frac{f_{RTCCLK}}{\text{PREDIV_A + 1}}\]

fclk_spre is given by the following formula:

\[f_{clk\_spre} = \frac{f_{clk\_apre}}{\text{PREDIV_S + 1}}\]

Programmable Alarm

The RTC unit provides one programmable alarm.

The programmable alarm function is enabled through the ALME bit in the RTC_CR register. The ALMF is set to ‘1’ if the calendar seconds, minutes, hours or days match the values programmed in the alarm registers RTC_ALMR1L and RTL_ALMR1H. Each calendar field can be independently selected through the MSKx bits. The alarm interrupt is enabled through the ALMIE bit in the RTC_CR register.

Alarm (if enabled by the OSEL [1:0] bits in RTC_CR) can be routed to the RTC_OUT output except when system is in deepsleep mode. The alarm output is a pulse which width is 1/RTCCLK.

Write Protection

After RTC domain reset, all the RTC registers are write-protected. Writing to the RTC registers is enabled by writing a key into the RTC_WPR register.

The following steps are required to unlock the write protection on all the RTC registers except for ALMF in RTC_ISR.

1. Write ‘0xCA’ into the RTC_WPR register.

2. Write ‘0x53’ into the RTC_WPR register.

Writing a wrong key reactivates the write protection. The protection mechanism is not affected by system reset.

Digital Calibration

The digital calibration can be used to compensate RTCCLK inaccuracy by adding (positive calibration) or masking (negative calibration) clock cycles at the output of the asynchronous prescaler (clk_apre).

Positive and negative calibrations are selected by setting the DCS bit to ‘0’ and ‘1’ in RTC_CALIBR register, respectively.

• When positive calibration is enabled (DCS = ‘0’), DC clk_apre cycle is added every (CALP +1) minutes, which causes the calendar updated sooner, thereby adjusting the effective RTC frequency to be a bit higher.

• When negative calibration is enabled (DCS = ‘1’), DC clk_apre cycle is removed every (CALP +1) minutes, which causes the calendar updated later, thereby adjusting the effective RTC frequency to be a bit lower.

DC and CALP can be configured through the RTC_CALIBR register. DC must be less than PREDIV_S in the RTC_PRER register.

The calibration parameter can be configured on-the-fly. Calibrating resolution is determined by the frequency of clk_apre and the calibration period. Formula is as follows:

The example is illustrated below.

\[\text{resolution} = \frac{period\_clk\_apre}{calp}\]

CALP	clk_apre (128Hz)	clk_apre (256Hz)	clk_apre (512Hz)
1 min.	130.2ppm	65.1ppm	32.55ppm
2 min.	65.1ppm	32.55ppm	16.27ppm
4 min.	32.55ppm	16.27ppm	8.14ppm
8 min.	16.27ppm	8.14ppm	4.07ppm

Re-calibration on-the-fly:

The calibration register (RTC_CALIBR) can be updated on the fly while INITF =0, by following the following steps:

• Poll the RECALPF (re-calibration pending flag).

• If RECALPF is set to 0, write a new value to RTC_CALIBR if necessary, RECALPF is then automatically set to 1.

• Within three clk_apre cycles after the write operation to RTC_CALIBR, the new calibration settings take effect.

Day Threshold Program

The RTC provides day interrupt for users. When wants to use day interrupt, DAY_THRES [8:0] must be programmed first in RTC_CR and then set the DOVTHIE bit in RTC_CR to enable day over threshold interrupt.

Daylight Saving

The daylight saving time management is performed through bits SUBIH, ADD1H, and BKP of the RTC_CR register.

Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure. In addition, the software can use the BKP bit to memorize this operation. It is recommended not to change the hour during the calendar hour increment as it could mask the incrimination of the calendar hour. (HW can handle this condition, if this condition occurs, HW will delay the SUB1H or ADD1H operation for 1 second.) When calendar hour is 0 of 24-hour system, SUB1H is not supported.

RTC Output

There are two types of RTC output pins which are in different domains. One type is in AON domain, it has power in active, sleep and deep sleep modes. The other can output in active mode and sleep mode, and has no power and cannot output in deep sleep mode. If it has output before, the output continues after wakeup from deep sleep.

The output of rtc_out can be determined by the OSEL [1:0].

Periodic Auto-wakeup

The wakeup function is enabled by setting the WUTE bit in the RTC_CR register.

The clock source of wakeup timer is ck_spre (usually 1Hz internal clock). When ck_spre frequency is 1Hz, this allows to achieve a wakeup time from 1s to around 36hours with one-second resolution. 3 to 4 wakeup timer cycles after the initialization sequence is complete (refer to this section), the timer starts counting down. The down-counting remains active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value).

The WUTF flag must then be cleared by software.

When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR register, it can exit the device from low-power modes.

System resets, as well as low-power modes have no influence on the wakeup timer.

Once wakeup timer is initialized and enabled, wakeup auto-reload value can be changed according to steps in this section.

Each time wakeup timer is enabled, 3 to 4 wakeup timer cycles (usually 3 to 4 seconds) are needed before wakeup timer works and counting actually begins. Because the enable command is generated in APB domain, it costs 2 RTC clock to sync to RTC domain, another 2 wakeup timer cycles are needed to sync to wakeup timer domain and one more wakeup cycle is needed before starting counting. After sync process of WUTE bit is done, WUTRSF flag bit is set for users to check.

Read and Write Timing

The write timing of RTC is shown below. Take the example of writing register RTC_TR. First write INIT bit=1 in RTC_ISR register, enter initialize mode, steady_n_o_f(low active) and steady_o_f (high active) are init mode flag. In the initialization phase, RTC_TR register is written, and then INIT BIT is configured to exit the initialization phase. exit_initmode_ps_rtc is the exit initialization flag signal that the APB domain synchronizes to the RTC domain. When it is raised, the APB value is loaded to the RTC, as shown at moment 1. Init_mode_n_rtc is the signal that steady_n_o_f synchronizes to the RTC domain, and then combines with rtc_rst_n to form init_rst_n_rtc. When counter_init is low, the value on the RTC is loaded into the clk_spre field, as shown at moment 2, when the value in the RTC field is loaded into the clk_spre field.

The read timing of RTC is shown below. The RTC domain clock collects the rising edge of clk_spre clock and synchronizes the acquired rising edge to the APB domain. When rd_time_ps_rtc is raised in the RTC domain, the values in the clk_spre domain are loaded into the RTC domain. When rd_time_ps_apb is raised in the APB domain, the values in the RTC domain are loaded into the APB domain. The read value is determined by the BYPSHAD bit in RTC_CR register. When BYPSHAD =0, it is read from the APB field, and when BYPSHAD =1, it is read directly from the RTC field.

Registers

Name	Address offset	Access	Description
REG_RTC_TR	000h	R/W	This register is the calendar time shadow register. This register is write protected, and must be wr itten in initialization mode only
REG_RTC_CR	004h	R/W	This register is write protected. Bit[7] (FMT) of this register can be written in initialization mod e only when INITF = 1. ADD1H and SUB1H changes are effective in 2~3 seconds. Don’t write this regist er continuously without any delay when RTC is in free run mode. Software can use the RSF bit in RTC_ ISR register to handle the delay.
REG_RTC_ISR	008h	R/W	RTC Initialization mode and status register,The ALMF/WUTF/DOVTHF bit can be written without unlockin g the write protection. Two APB clock cycles after programming it to 1, this bit is cleaned.
REG_RTC_PRER	00Ch	R/W	This register is write protected, and must be written in initialization mode only.
REG_RTC_CALIBR	010h	R/W	This register is write protected, and can be dynamically configured when RTC is running
REG_RTC_ALMR1L	014h	R/W	This register is write protected, and can be written only when ALMWF is set to 1 in RTC_ISR register , or in initialization mode.
REG_RTC_ALMR1H	018h	R/W	This register is write protected, and can be written only when ALMWF is set to 1 in RTC_ISR register , or in initialization mode
REG_RTC_WPR	01Ch	R/W	RTC write protection register,write “0xCA”then write “0x53” disable write protect,write “0xFF” enabl e write protect
REG_RTC_YEAR	020h	R/W	RTC year register,this register is controlled by software
REG_RTC_WUTR	024h	R/W	RTC wakeup timer register,set wakeup timer value.
REG_RTC_DUMMY	028h	R/W	Dummy register

REG_RTC_TR

• Name : RTC Time Reg

• Size : 32

• Address offset : 000h

• Read/write access : R/W

This register is the calendar time shadow register. This register is write protected, and must be wr

itten in initialization mode only

Bit	Symbol	Access	Reset	Description
31:23	DAY	R/W	0	DAY in binary format
22	PM	R/W	0	PM:AM/PM notation 0: AM or 24-hour foramt 1: PM
21:20	HT	R/W	0	Hour tens in BCD format
19:16	HU	R/W	0	Hour units in BCD format
15	RSVD	R	-	Reserved
14:12	MNT	R/W	0	Minute tens in BCD format
11:8	MNU	R/W	0	Minute units in BCD format
7	RSVD	R	-	Reserved
6:4	ST	R/W	0	Second tens in BCD format
3:0	SU	R/W	0	Second units in BCD format

REG_RTC_CR

• Name : RTC Ctrl Reg

• Size : 32

• Address offset : 004h

• Read/write access : R/W

This register is write protected. Bit[7] (FMT) of this register can be written in initialization mod

e only when INITF = 1. ADD1H and SUB1H changes are effective in 2~3 seconds. Don’t write this regist

er continuously without any delay when RTC is in free run mode. Software can use the RSF bit in RTC_

ISR register to handle the delay.

Bit	Symbol	Access	Reset	Description
31:23	DAY_THRES	R	1FFh	Day threshold in binary format
22:18	RSVD	R	-	Reserved
17	CLKDIV2_EN	R/W	1	Rtc_clk/rtc_bclk use divided clock enable 0: unuse div2 clk 1: use div2 clk
16	DOVTHIE	R/W	0	Day over threshold interrupt enable 0: Day over threshold interrupt disabled 1: Day over threshold interrupt enabled
15	RSVD	R	-	Reserved
14	WUTIE	R/W	0	Wakeup timer interrupt enable 0: Wakeup timer interrupt disabled 1: Wakeup timer interrupt enabled
13	RSVD	R	-	Reserved
12	ALMIE	R/W	0	Alarm interrupt enable 0: Alarm interrupt disabled 1: Alarm interrupt enabled
11	RSVD	R	-	Reserved
10	WUTE	R/W	0	Wakeup timer enable 0: Wakeup timer disabled 1: Wakeup timer enabled
9	RSVD	R	-	Reserved
8	ALME	R/W	0	Alarm enable 0: Alarm disabled 1: Alarm enabled
7	FMT	R/W	0	Hour format 0: 24 hour/day format 1: AM/PM hour format
6:5	OSEL	R/W	0	Output selection.There bits are used to select the flag to b e routed to RTC_OUT output. 00: Output disabled 01: Alarm output enabled 10: Clock output is clk_spre (default:1Hz) 11: Clock output is clk_apre (default:256Hz)
4	RSVD	R	-	Reserved
3	BYPSHAD	R/W	0	Bypass the shadow registers. 0: Calendar values (when reading from RTC_TR) are taken fr om the shadow register, which are updated once every two R TCCLK cycles. 1: Calendar values (when reading from RTC_TR) are taken di rectly from the calendar counters.
2	BKP	R/W	0	Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
1	SUB1H	R/W	0	Subtract one hour(winter time change),when this bit is set o utside initialization mode,1 hour is subtracted to the calen dar time if the current hour is not 0,this bit is always rea d as 0. 0:No effect 1:subtract one hour to the current time
0	ADD1H	R/W	0	Add one hour(summer time change),when this bit is set outsid e initialization mode,1 hour is add to the calendar time,thi s bit is always read as 0. 0:No effect 1:add one hour to the current time

REG_RTC_ISR

• Name : RTC Init And Status Reg

• Size : 32

• Address offset : 008h

• Read/write access : R/W

RTC Initialization mode and status register,The ALMF/WUTF/DOVTHF bit can be written without unlockin

g the write protection. Two APB clock cycles after programming it to 1, this bit is cleaned.

Bit	Symbol	Access	Reset	Description
31:17	RSVD	R	-	Reserved
16	RECALPF	R	0	Recalibration pending flag The RECALPF status flag is automatically set to ‘1’ when sof tware writes to the RTC_CALIBR register, indicating that the RTCCALIBR register is blocked. When the new calibration sett ings are taken into account, this bit returns to ‘0’. Refer to Re-calibration on-the-fly.
15	DOVTHF	R/W	0	Day over threshold flag This flag is set by hardware when the Day in RTC_TR over the DAY_THRES set in RTC_CR register.
14:11	RSVD	R	-	Reserved
10	WUTF	R/W	0	Wakeup timer flag This flag is set by hardware when the wakeup auto-reload co unter reaches to. This flag must be cleared by software at least 2 RTCCLK peri ods before WUTF is set to ‘1’ again.
9	RSVD	R	-	Reserved
8	ALMF	R/W	0	Alarm flag This flag is set by hardware when the time register (RTC_TR) matches the Alarm registers (RTC_ALMR1L and RTC_ALMR1H).
7	INIT	R/W	0	Initialization mode 0: Free running mode. 1: Initialization mode used to program time and date regis ter (RTC_TR), and prescaler register (RTC_PRER). Counters are stoped and start counting from the new value when INIT is set.
6	INITF	R	0	Initialization flag. When this bit is set to ‘1’, the RTC is in initialization st ate, and the time, date, and prescaler registers can be upda ted. 0: Calendar registers update is not allowed. 1: Calendar registers update is allowed.
5	RSF	R/W	0	Registers synchronization flag. This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_TR). This bit is c leared by hardware in initialization mode or when in bypass shadow register mode (BYPSHAD=1). This bit can also be clear ed by software. It is cleared either by software or by hardware in initializ ation mode. 0: Calendar shadow registers are not yet synchronized. 1: Calendar shadow registers are synchronized.
4	INITS	R	0	This bit is set by hardware when the calendar day field is d ifferent from 0 (RTC domain reset state). 0: Calendar has not been initialized. 1: Calendar has been initialized.
3	RSVD	R	-	Reserved
2	WUTWF	R	0	Wakeup timer write flag This flag is set by hardware when WUT value can be changed, after the WUTE bit has been set to ‘0’ in RTC_CR. 0: Wakeup timer configuration update not allowd except in initialization mode 1: Wakeup timer configuration update allowed
1	WUTRSF	R/W	0	This bit is set by hardware each time the WUTE bit is copied into the shadow register. This bit is cleared by hardware in initialization mode. This bit can also be cleared by softwar e. It is cleared either by software or by hardware in initializ ation mode. 0: WUTE is not yet synchronized. 1: WUTE is synchronized.
0	ALMWF	R	0	Alarm write flag This bit is set by hardware when Alarm values can be changed , after the ALME bit has been set to ‘0’ in RTC_CR. It is cleared by hardware when ALME bit has been set to ‘1’ in RTC_CR. 0: Alarm update not allowed 1: Alarm update allowed

REG_RTC_PRER

• Name : RTC Prescaler Reg

• Size : 32

• Address offset : 00Ch

• Read/write access : R/W

This register is write protected, and must be written in initialization mode only.

Bit	Symbol	Access	Reset	Description
31:25	RSVD	R	-	Reserved
24:16	PREDIV_A	R/W	7Fh	Asynchronous prescaler factor This is the asynchronous division factor: clk_apre freq = RT CCLK freq/(PREDIV_A + 1)
15:9	RSVD	R	-	Reserved
8:0	PREDIV_S	R/W	FFh	Synchronous prescaler factor This is the synchronous division factor: clk_spre freq = clk _apre freq/(PREDIV_S + 1)

REG_RTC_CALIBR

• Name : RTC Calibration Reg

• Size : 32

• Address offset : 010h

• Read/write access : R/W

This register is write protected, and can be dynamically configured when RTC is running

Bit	Symbol	Access	Reset	Description
31:19	RSVD	R	-	Reserved
18:16	CALP	R/W	0	Calibration period
15	DCE	R/W	0	Digital calibration enable 0: Digital calibration disabled 1: Digital calibration enabled
14	DCS	R/W	0	Digital calibration signal 0: Positive calibration, time update frequency is increase d. 1: Negative calibration, time update frequency is decrease d.
13:7	RSVD	R	-	Reserved
6:0	DC	R/W	0	Digital calibration

REG_RTC_ALMR1L

• Name : RTC Alarm 1 Reg Low

• Size : 32

• Address offset : 014h

• Read/write access : R/W

This register is write protected, and can be written only when ALMWF is set to 1 in RTC_ISR register

, or in initialization mode.

Bit	Symbol	Access	Reset	Description
31:24	RSVD	R	-	Reserved
23	MSK2	R/W	0	Alarm hour mask 0: Alarm set if the hours match 1: Hours don’t care in Alarm comparison
22	ALR_PM	R/W	0	AM/PM notation. 0: AM or 24-hour format 1: PM
21:20	ALR_HT	R/W	0	Hour tens in BCD format
19:16	ALR_HU	R/W	0	Hour units in BCD format
15	MSK1	R/W	0	Alarm minutes mask. 0: Alarm set if the minutes match 1: Minutes don’t care in Alarm comprison
14:12	ALR_MNT	R/W	0	Minute tens in BCD format
11:8	ALR_MNU	R/W	0	Minute units in BCD format
7	MSK0	R/W	0	Alarm seconds mask 0: Alarm set if the seconds match 1: Seconds don’t care in Alarm comprison
6:4	ALR_ST	R/W	0	Second tens in BCD format
3:0	ALR_SU	R/W	0	Second units in BCD format

REG_RTC_ALMR1H

• Name : - RTC Alarm 1 Reg High

• Size : 32

• Address offset : 018h

• Read/write access : R/W

This register is write protected, and can be written only when ALMWF is set to 1 in RTC_ISR register

, or in initialization mode

Bit	Symbol	Access	Reset	Description
31:10	RSVD	R	-	Reserved
9	MSK3	R/W	0	Alarm day mask 0: Alarm set if the days match 1: Days don’t care in Alarm comprison
8:0	ALR_DAY	R/W	0	DAY in binary format

REG_RTC_WPR

• Name : RTC Write Protect Reg

• Size : 32

• Address offset : 01Ch

• Read/write access : R/W

RTC write protection register,write “0xCA”then write “0x53” disable write protect,write “0xFF” enabl

e write protect

Bit	Symbol	Access	Reset	Description
31:8	RSVD	R	-	Reserved
7:0	KEY	R/W	0	Write protection key This byte is written by software. Refer to RTC register writ e protection for a description of how to unlock RTC register write protection.RTC write protection register,write “0xCA”t hen write “0x53” disable write protect,write “0xFF” enable w rite protect

REG_RTC_YEAR

• Name : RTC Year Reg

• Size : 32

• Address offset : 020h

• Read/write access : R/W

RTC year register,this register is controlled by software

Bit	Symbol	Access	Reset	Description
31	RESTORE	R/W	0	Reset Flag. Indicates whether any reset conditions have occu rred (except POR/PDR/BOD), so that the bit is set to ‘1’ bef ore reset, and then the global variable that determines whet her the recovery time information is needed depending on whe ther the bit is ‘1’.
30:8	RSVD	R	-	Reserved
7:0	YEAR	R/W	0	Year in binary format

REG_RTC_WUTR

• Name : RTC Wakeup Timer Reg

• Size : 32

• Address offset : 024h

• Read/write access : R/W

RTC wakeup timer register,set wakeup timer value.

Bit	Symbol	Access	Reset	Description
31:17	RSVD	R	-	Reserved
16:0	WUT	R/W	0	Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE is set to ‘1’), the W UTF flag is set every (WUT[16:0]+1) cycles. The first assert ion of WUTF occurs between WUT and (WUT+1) cycles after WUTE is set.

REG_RTC_DUMMY

• Name : RTC Dummy Register

• Size : 32

• Address offset : 028h

• Read/write access : R/W

Dummy register

Bit	Symbol	Access	Reset	Description
31:0	DUMMY	R/W	ffffh	Dummy register

Operation Flow

Initializing the Calendar

The initialization steps of the calendar are illustrated below.

Step	What to do	How to do	Comments
1	Disable the RTC registers write protection	Write “0xCA” and then “0x53” into the RTC_WPR register	RTC registers can be modified
2	Enter initialization mode	Set INIT bit to ‘1’ in RTC_ISR register	The calendar counter is stopped to allow update
3	Wait for the confirmation of initialization mode (clock synchronization)	Poll INITF bit in RTC_ISR until it is set	It takes approximately 2 RTCCLK clock cycles for medium density devices
4	Program the prescaler register if needed	Configure RTC_PRER register	By default, the RTC_PRER prescalers register is initialized to provide 1Hz to the calendar unit when RTCCLK=32768Hz
5	Load time value in the shadow registers	Set RTC_TR
6	Configure the time format (12-hour or 24-hour)	Set FMT bit in RTC_CR register	FMT =0: 24 hour/day format FMT =1: AM/PM hour format
7	Exit initialization mode	Clear INIT bit in RTC_ISR register	The current calendar counter is automatically loaded and the counting restarts after 4 RTCCLK clock cycles.
8	Enable the RTC registers write protection	Write “0xFF” into the RTC_WPR register	RTC registers can no longer be modified

Configuring Alarm

The configuration steps of alarm are illustrated below.

Step	What to do	How to do	Comments
1	Disable the RTC registers write protection	Write “0xCA” and then “0x53” into the RTC_WPR register	RTC registers can be modified
2	Disable alarm	Clear ALME bit in RTC_CR register	Read RTC_CR first and set ALME to 1’b0
3	Check that the RTC_ALRMA register can be accessed	Poll ALMWF bit until it is set in RTC_ISR	It takes approximately two RTCCLK clock cycles(clock synchronization)
4	Configure the alarm	Configure RTC_ALMR1 and RTC_ALMR2 register	The alarm hour format must be the same as the RTC calendar
5	Re-enable alarm	Set ALME bit in RTC_CR register
6	Enable the RTC registers write protection	Write “0xFF” into the RTC_WPR register	RTC registers can no longer be modified

Note

1. The alarm behavior can be configured using the MSKx bits (x=0,1,2,3) of the RTC_ALMR1 and RTC_ALMR2 registers.

2. Alarm can also be configured in the initialization mode.

Configuring Calibration

The configuration steps of calibration are illustrated below.

Step	What to do	How to do	Comments
1	Disable the RTC registers write protection	Write “0xCA” and then “0x53” into the RTC_WPR register	RTC registers can be modified
2	Check that the RTC_CALIBR register can be updated	Poll the RTC_ISR / RECALPF until it is 0 in RTC_ISR
3	Configure the calibration parameter	Configure RTC_CALIBR register
4	Enable the RTC registers write protection	Write “0xFF” into the RTC_WPR register	RTC registers can no longer be modified

Note

1. Calibration can also be configured in the initialization mode.

2. The calibration parameter will be not used immediately. HW will automatically reload the new calibration parameter at the end of calibration period.

Programming the Wakeup Timer

The following sequence is required to configure or change the wakeup timer auto-reload value(WUT [16:0] in RTC_WUTR), see the table below.

Step	What to do	How to do	Comments
1	Disable the RTC registers write protection	Write “0xCA” and then “0x53” into the RTC_WPR register	RTC registers can be modified
2	Disable the wakeup timer	Clear WUTE in RTC_CR register	Read RTC_CR first and set WUTE to 1’b0
3	Check that wakeup auto-reload counter can be updated	Poll WUTWF in RTC_ISR register until it is set
4	Program the wakeup auto-reload value	Configure WUT [16:0] in RTC_WUTR register
5	Re-enable the wakeup timer	Set WUTE in RTC_CR register	The WUTWF bit is cleared up to 2 RTCCLK clocks cycles after WUTE is set, due to clock synchronization.
6	Wait for the confirmation of configuration (clock synchronization)	Poll WUTRSF bit in RTC_ISR until it is set	It takes approximately 3 to 4 RTCCLK clock cycles before the wakeup timer restarts down-counting
7	Enable the RTC registers write protection	Write “0xFF” into the RTC_WPR register	RTC registers can no longer be modified

Daylight Saving Time

In the U.S., 2:00 a.m. was originally chosen as the changeover time because it was practical and minimized disruption. Most people were at home and this was the time when fewest trains were running. It is late enough to minimally affect bars and restaurants, and it prevents the day from switching to yesterday, which would be confusing. It is early enough that the entire continental U.S. switches by daybreak, and the changeover occurs before earliest shift workers and early churchgoers are affected.