The chip includes six basic timers, one capture timer, and four PWM timers.

Basic Timer

Introduction

The basic timers (TIM0 ~ TIM5) consist of a 32-bit auto-reload counter. They may be used as generic timers for time-base generation.

Each basic timer can independently select the clock source as SDM32KHz or XTAL40MHz, If clock source is XTAL40MHz, prescaler can be configured from 2 to 40. All basic timers share a prescaler.

Features

The features of basic timers are listed below.

Basic timers features

Name	TIM0 ~ TIM5
Clock source	SDM32KHz(default) or XTAL40MHz
Resolution	32-bit
Counter mode	Up
One pulse mode	-
PWM mode with polarity selection	-
Statistic pulse width	-
Statistic pulse number	-
Interrupt generation	√

Block Diagram

The block diagram of the basic timers is shown below.

Functional Description

Configurable Count Direction

This timer is a 32-bit counter with its related auto-reload register. The counter, as well as the auto-reload register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter register (TIMx_CNT)

• Auto-reload register (TIMx_ARR)

timer is in count-up mode where the counter counts from 0 to the auto-reload value (the content of the TIMx_ARR register). A counter overflow event is generated after the counter reaches the auto-reload value. The timer will restart from 0 or stop according to the auto reload enable bit (ARE) in the TIMx_CR register.

Preloaded Auto-Reload Register

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The contents of the preload register are transferred into the shadow register permanently or at each update event (UEV) depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR register.

The update event is sent when the counter reaches the overflow in count-up mode; or if the UDIS bit equals to 0 in the TIMx_CR register, it can also be generated by software.

Setting the UG bit in the TIMx_EGR register by software also generates an update event.

The update event can be disabled by software by setting the UDIS bit in the TIMx_CR register. This is to avoid updating the shadow registers while writing new values into the preload register. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0 in count-up mode. In addition, if the URS bit in the TIMx_CR register is set, setting the UG bit generates an update event but without setting the update interrupt flag (UIF), thus no interrupt is sent.

When an update event occurs, all the registers are updated and the update flag (the UIF bit in TIMx_SR) is set depending on the URS bit. The auto-reload shadow register is updated with the preload value (TIMx_ARR).

Interrupt Event

The interrupt event is configured by TIMx_DIER.

When the UIF bit in the TIMx_SR register is asserted, the according interrupt event is asserted, which is determined by the configuration of TIMx_DIER. And when the counter overflows in count-up mode, the UIF is set automatically.

Security Attribution

Because all basic timers are in the same port and security attributions are not limited by PPC, these basic timers have secure enable bit to configure their security attributions individually.

Every basic timer consists of a secure control register, which contains a secure enable bit. This register is used for setting the security attribution of this basic timer. The secure control register can only be accessed by secure region, and non-secure region cannot access this register.

When secure enable bit of one basic timer is set, this basic timer is a secure timer now. All registers of this timer can be accessed by secure address, and non-secure address cannot access. When secure enable bit of one basic timer is cleared, this basic timer is a non-secure timer now and all register of this timer except secure control register can be accessed by both secure address and non-secure address.

Capture Timer

Introduction

The capture timer (TIM10) consists of a 16-bit auto-reload counter driven by a 16-bit programmable prescaler. It can be used for a variety of purposes, including measuring the pulse lengths or numbers of input signals.

Features

The features of the capture timer are listed below.

Capture timer features

Name	TIM10
Clock source	XTAL40MHz
Resolution	16-bit
Prescaler	16-bit
Counter mode	Up
One pulse mode	-
PWM mode with polarity selection	-
Statistic pulse width	√
Statistic pulse number	√
Interrupt generation	√

Block Diagram

The block diagram of the capture timer is shown below.

Functional Description

Upcounting Mode

This timer is a 16-bit counter with its related auto-reload register. The counter can count up. The counter clock can be divided by a 16-bit prescaler.

The counter, also the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter register (TIMx_CNT)

• Prescaler register (TIMx_PSC)

• Auto-reload register (TIMx_ARR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The contents of the preload register are transferred into the shadow register permanently or at each update event depending on the ARPE bit in the TIMx_CR register. The update event is sent when the counter reaches the overflow; or if the UDIS bit equals 0 in the TIMx_CR register, it can also be generated by software.

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

In upcounting mode, the counter counts from 0 to the auto-reload value (the content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

Setting the UG bit in the TIMx_EGR register by software also generates an update event.

The update event can be disabled by software by setting the UDIS bit in the TIMx_CR register. This is to avoid updating the shadow registers while writing new values to the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler, but the prescale rate doesn’t change. In addition, if the URS bit in the TIMx_CR register is set, setting the UG bit generates an update event but without setting the UIF flag, thus no interrupt is sent. This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (the UIF bit in TIMx_SR) is set depending on the URS bit:

• The auto-reload shadow register is updated with the preload value (TIMx_ARR).

• The buffer of the prescaler is reloaded with the preload value (the content of the TIMx_PSC register).

Statistic Pulse Width

In pulse mode 0, setting 0 in the CC0M bit of the TIMx_CCR0 register, the capture timer can count the width of active level of TRGI. When the TRGI is transferred to active level from inactive level, the counter is enabled automatically. When the TRGI is transferred to inactive level from active level, the counter is disabled automatically, the CC0IF is set and the current counter value is copied to CCR0 field of the TIMx_CCR0 register.

The following figure gives an example of statistic pulse width mode when prescaler division is 1 and positive edge of TRGI is active for capture.

Statistic Pulse Number

In pulse mode 1, setting 1 in the CC0M bit of the TIMx_CCR0 register, the capture timer can count the number of active edge of TRGI in the given period. When the counter overflows, the CC0IF is set and the number is copied to CCR0 field of the TIMx_CCR0 register.

The following figure gives an example of statistic pulse number mode when prescaler division is 1, positive edge of TRGI is active for capture, and the ARR field equals E6.

PWM Timer

Introduction

The PWM timer (TIM6~TIM9) consists of a 16-bit auto-reload counter driven by a 16-bit programmable prescaler. It can be used for a variety of purposes, including measuring the pulse frequency of input signals (input capture) or generating output waveforms (PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several seconds using the timer prescaler.

Features

The features of the PWM timer are listed below.

PWM timer features

Name	TIM6~TIM9
Channels	4
Clock source	XTAL40M
Resolution	16-bit
Prescaler	16-bit
Counter mode	Up
One-pulse mode	√
PWM mode with polarity selection	√
Statistic pulse width	-
Statistic pulse number	-
Interrupt generation	√
Sleep mode	√
Duty cycle 0%/100%	√
Phase shift	√

Block Diagram

The block diagram of the PWM timer is shown below.

Functional Description

Upcounting Mode

This timer is a 16-bit counter with its related auto-reload register. The counter can count up. The counter clock can be divided by a 16-bit prescaler.

The counter, also the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter register (TIMx_CNT)

• Prescaler register (TIMx_PSC)

• Auto-reload register (TIMx_ARR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The contents of the preload register are transferred into the shadow register permanently or at each update event depending on the ARPE bit in the TIMx_CR register. The update event is sent when the counter reaches the overflow; or if the UDIS bit equals to 0 in the TIMx_CR register, it can also be generated by software.

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Counter timing diagram with prescaler division change from 1 to 2 and Counter timing diagram with prescaler division change from 1 to 4 give some examples of the counter behavior when the prescaler ratio is changed on the fly.

Counter timing diagram with prescaler division change from 1 to 2

Counter timing diagram with prescaler division change from 1 to 4

In upcounting mode, the counter counts from 0 to the auto-reload value (the content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

Setting the UG bit in the TIMx_EGR register by software also generates an update event.

The update event can be disabled by software by setting the UDIS bit in the TIMx_CR register. This is to avoid updating the shadow registers while writing new values to the preload registers. No update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler, but the prescale rate doesn’t change. In addition, if the URS bit in the TIMx_CR register is set, setting the UG bit generates an update event but without setting the UIF flag, thus no interrupt is sent. This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (the UIF bit in TIMx_SR) is set depending on the URS bit:

• The auto-reload shadow register is updated with the preload value (TIMx_ARR).

• The buffer of the prescaler is reloaded with the preload value (the content of the TIMx_PSC register)

The following figures show some examples of the counter behavior for different clock frequencies when the ARR field equals 0x36.

Counter timing diagram (internal clock divided by 1)

Counter timing diagram (internal clock divided by 2)

Counter timing diagram (internal clock divided by 4)

Counter timing diagram (internal clock divided by N )

Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)

Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

Input Capture Mode

In input capture mode, setting 1 in the CCxM bit of the TIMx_CCRx register, the CCRx field of capture/compare registers (TIMx_CCRx) is used to latch the value of the counter after a transition detected by the TRGI signal. When a capture occurs, the corresponding CCxIF flag in the TIMx_SR register is set and an interrupt can be sent if they are enabled. CCxIF can be cleared by software by writing it to 1.

PWM Mode

Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the register and a duty cycle determined by the value of the CCRx field of the TIMx_CCRx register.

• Period:

• Duty cycle:

• Where

The PWM mode can be selected independently on each channel (one PWM per OCx output) by setting 0 in the OCxM bits in the TIMx_CCRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCRx register, and eventually the auto-reload preload register by setting the ARPE bit in the TIMx_CR register.

As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register.

OCx polarity is software programmable, using the CCxP bit in TIMx_CCRx register. It can be programmed as active high or active low.

In PWM mode, TIMx_CNT and CCRx (in TIMx_CCRx) are always compared to determine whether TIMx_CNT< CCRx. The PWM signal OCx is active as long as TIMx_CNT < CCRx, otherwise it becomes inactive. If the compare value in TIMx_CCRx is greater than the auto_reload value in TIMx_ARR, then PWM signal OCx output is active all the period. If the compare value is 0, then PWM signal OCx output is inactive all the period.

The timer is only able to generate PWM in edge-aligned mode. The following figure shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8.

Edge-aligned PWM waveforms (ARR=8, CCxP=0)

Phase Synchronization Function

This function is for users to configure a particular phase shift between channels. It can only be applied in PWM mode and one-pulse mode, input capture mode is not affected.

There are 7 counters in PWM timer, including one CNT in TIM_CNT register and six-channel counters for six channels. Each channel has one channel counter, the value of which can get from reading TIM_PHASECNTx(x=0, 1, 2, 3, 4, 5) registers. The value of each channel counter is calculated from the CNT value in TIM_CNT register. When the counter value in TIM_CNT changes, the channel value always updates immediately. The waveform of each channel uses its own channel counter as a benchmark.

The phase shift between channels is achieved by setting a phase shift of channel counter compared to the CNT value in TIM_CNT register. The phase shift function can be configured by TIM_PSYNCx(x=0, 1, 2, 3, 4, 5) registers. When phase shift function is enabled by setting SYNCENx bit in TIM_PSYNCx register, users can configure a phase shift between this channel counter and CNT value in TIM_CNT, and the phase shift value is set by SYNCDIR and SYNCPHASE in TIM_PSYNCx. When phase shift function is disabled, the channel counter value of this channel is exactly the same with CNT. The channel counter value is:

channel counter value = CNT - (-1)^SYNCDIR* (SYNCPHASE)

Hardware can always ensure channel value in the range 0-ARR. When channel counter value is above ARR, it changes to old value - ARR immediately to keep in range 0-ARR, when channel counter value is below zero, it changes to old value + ARR immediately.

Phase shift function shows change curves of channel counter value compared to counter, and corresponding waveforms generated from channel counter of channel 0, 1, 2. In the following configuration, the phase shift between every two channels is 1/3.

In the above example, for channel 0, SYNCEN0 of channel 0 is 0, so that channel counter0 is always equal to CNT. When channel counter0 is below CCR0, which is 30, channel 0 outputs high level, when channel counter0 is above CCR0, channel 0 outputs low level. For channel 1, SYNCEN1 is set to 1, so that channel counter1 has a phase shift with TIM_CNT. The value of channel counter 1 is CNT + 66, in which CNT is value of TIM_CNT. When channel counter1 is below CCR1, channel 1 outputs high level, and vice versa. For channel 2, channel counter2 is CNT + 33. Under the above setting, there is 1/3 phase shift between every two channels.

Software ensures SYNCPHASEx always smaller than ARR value. Otherwise, low level will be generated and output.

After PWM timer is enabled and waveforms are generated. Users may want to update some parameters such as period, duty cycle and phase shift value. Because ARR, PSC, CCRx and PSYNCx registers can be configured to be preloaded or not, there are three ways for users to change configurations on-the-fly.

1. Set the registers to be not preloaded and then set a new value, the new value will take effect immediately after the register value is changed.

2. Set the registers to be preloaded and then set a new value, the new value will update after the next UEV of CNT.

3. Set the registers to be preloaded, set a new value and then write UG bit, after that CNT will clear and recounts from 0, the new value will take effect immediately. This can help when multiple parameters need to be updated immediately.

Phase shift function

The following sections illustrate some cases.

Update Immediately

1. Change the period

   1. Increase ARR value

      waveform when ARR changes from 100 to 150 illustrates when ARR value is changed from 100 to 150. Because ARR is increased, the waveforms in red cycle shows that all three channels are in low level states.

   2. Decrease ARR value

      waveform when ARR changes from 100 to 80 shows when ARR value is changed from 100 to 80. Before ARR is decreased, there is only one channel in high level state at the same time, After ARR is set to 80, the waveforms in red cycle shows that channel 0 and 2 are both in high level states in this case.

      

      waveform when ARR changes from 100 to 150

      

      waveform when ARR changes from 100 to 80

2. Change the duty cycle

   The duty cycle of each channel depends on its CCRx value which is configured individually in its own TIM_CCRx registers. They can’t be updated exactly at the same time due to the time gap that CPU executes instructions. The length of this time gap is unpredictable. The following examples ignore this time gap.

   1. Increase CCRx value

      The following figure displays when CCRx changes from 30 to 40. For channel 2, CCR2 is changed when channel counter2 value is 35 and also 30 < 35 < 40, so that waveform of channel 2 falls into high level simultaneously when CCRs is updated. This causes a glitch. Also, channel 0 and 1 both in high level state because of increasing its CCRx in this case.

      

   2. Decrease CCRx value

      The following figure shows when CCRx changes from 30 to 20. For channel 2, CCR2 is changed when channel counter2 value is 25 and also 20 < 25 < 30, so that waveform of channel 2 falls into low level simultaneously when CCRs is updated. The duty cycle of channel 2 in this period is neither 20% nor 30%, but 25% instead.

      

3. Change phase shift value

   Phase shift of each channel is configured individually in TIM_PSYNCx registers. They can’t be updated exactly at the same time and the following example ignore this time gap. Also, the change of phase shift always results in discrete channel counters and waveforms. The following figure is an example that phase shift of channel 1 changes from 66 to 36 and channel 2 from 33 to 63. For channel 1, channel counter1 is above and below CCR1 before and after changing. For channel 2, channel counter2 is below and above CCR2 before and after changing.

   

   Waveforms when phase shifts change

Update after Next UEV of CNT

1. Change the period

   1. Increase ARR value

      Waveform when ARR changes from 100 to 150 illustrates when ARR value is changed from 100 to 150. Because ARR is increased, the waveforms in red cycle shows that all three channels are in low level states in this case.

   2. Decrease ARR value

      Waveform when ARR changes from 100 to 80 shows when ARR value is changed from 100 to 80. Before ARR is decreased, there is only one channel in high level state at the same time, After ARR is set to 80, the waveforms in red cycle shows that channel 0 and 2 are both in high level states in this case.

      

      Waveform when ARR changes from 100 to 150

      

      Waveform when ARR changes from 100 to 80

2. Change the duty cycle

   The following examples ignore the time gap of configuration. The waveform is similar with cases that CCRx updates immediately.

   1. Increase CCRx value

      The following figure displays when CCRx changes from 30 to 40.

      

   2. Decrease CCRx value

      The following figure shows when CCRx changes from 30 to 20.

      

3. Change phase shift value

   The following example ignores the time gap of configuration; the waveform is similar with cases that phase shifts update immediately.

   

   waveform when phase shift change

Update after Writing UG Bit

Before writing the UG bit, the waveform was generated according to the old configuration. The new configuration comes into effect after writing the UG bit, and also CNT and channel counter are cleared to 0. In the following example, ARR changes from 100 to 150, CCRx not changed, phase shift function of channel 0 is disabled, phase shift of channel 1 changes from 66 to 33, and phase shift of channel 1 changes from 33 to 66.

Waveform when writing UG bit

Registers

Memory map of timers

Type	Name	Base address	Address offset
Basic Timer	TIM0	0x4200_B000	0x000 ~ 0x1FF
Basic Timer	TIM1	0x4200_B000	0x200 ~ 0x3FF
Basic Timer	TIM2	0x4200_B000	0x400 ~ 0x5FF
Basic Timer	TIM3	0x4200_B000	0x600 ~ 0x7FF
Basic Timer	TIM4	0x4200_B000	0x800 ~ 0x9FF
Basic Timer	TIM5	0x4200_B000	0xA00 ~ 0xBFF
Basic Timer	TIM6	0x4200_B000	0xC00 ~ 0xDFF
Basic Timer	TIM7	0x4200_B000	0xE00 ~ 0xFFF
Basic Timer	TIM10	0x4100_A000	0x400 ~ 0x5FF
Basic Timer	TIM11	0x4100_A000	0x600 ~ 0x7FF
PWM Timer	TIM8	0x4100_A000	0x000 ~ 0x1FF
Capture Timer	TIM9	0x4100_A000	0x200 ~ 0x3FF

Basic Timer Registers

Name	Address offset	Access	Description
REG_TIM_EN	000h	R/W	User can configure and observe the counter operation
REG_TIM_CR	004h	R/W	Registers about the update operation
REG_TIM_DIER	008h	R/W	Interrupt enable
REG_TIM_SR	00Ch	R/W	Registers about timer interrupt and update status
REG_TIM_EGR	010h	R/W	Update generation user defined
REG_TIM_CNT	014h	R	Timer count
REG_TIM_ARR	01Ch	R/W	Auto-reload value
REG_TIM_SEC	020h	R/W	Security status
REG_TIM_BASIC_DUMMY	024h	R/W	Dummy register

REG_TIM_EN

• Name : TIM enable register

• Size : 32

• Address offset : 000h

• Read/write access : R/W

User can configure and observe the counter operation

Bit	Symbol	Access	Reset	Description
31:17	RSVD	R	-	Reserved
16	CNT_EN	R	0x0	Counter working status 0: counter is stoppped 1: counter is working
15:9	RSVD	R	-	Reserved
8	CNT_RUN	R	0x0	Counter run status 0: counter is disabled 1: counter is enabled
7:2	RSVD	R	-	Reserved
1	CNT_STOP	R/W	0x0	Disable the counter. Poll CNT_RUN to see the counter status. If CNT_RUN is 0, it means that the counter has been disabled internally.
0	CNT_START	R/W	0x0	Enable the counter. Poll CNT_RUN to see the counter status. If CNT_RUN is 1, it means that the counter has been enabled internally.

REG_TIM_CR

• Name : TIM control register

• Size : 32

• Address offset : 004h

• Read/write access : R/W

Registers about the update operation

Bit	Symbol	Access	Reset	Description
31:5	RSVD	R	-	Reserved
4	ARPE	R/W	0x0	Enable auto-reload preloading 0: TIM_ARR register is not buffered 1: TIM_ARR register is buffered
3	RSVD	R	-	Reserved
2	URS	R/W	0x0	Update request source 0: counter overflow and setting the UG bit 1: counter overflow
1	UDIS	R/W	0x0	Disable UEV. Shadow registers keep their values. Otherwise, buffered registers are then loaded with their preload values when UEV happen.
0	RSVD	R	-	Reserved

REG_TIM_DIER

• Name : TIM interupt enable register

• Size : 32

• Address offset : 008h

• Read/write access : R/W

Interrupt enable

Bit	Symbol	Access	Reset	Description
31:1	RSVD	R	-	Reserved
0	UIE	R/W	0x0	Enable update interrupt

REG_TIM_SR

• Name : TIM status register

• Size : 32

• Address offset : 00Ch

• Read/write access : R/W

Registers about timer interrupt and update status

Bit	Symbol	Access	Reset	Description
31	UG_DONE	R	0x1	UG operation status This bit is cleared by hardware when the UG bit in the TIMx_ EGR register is set. When the UG operation is done, hardware set this bit to ‘1’. So, software can poll this bit to see t he UG operation status.
30:1	RSVD	R	-	Reserved
0	UIF	R/W	0x0	Update interrupt flag

REG_TIM_EGR

• Name : TIM event generation register

• Size : 32

• Address offset : 010h

• Read/write access : R/W

Update generation user defined

Bit	Symbol	Access	Reset	Description
31:1	RSVD	R	-	Reserved
0	UG	R/W	0x0	Update generation. Re-initialize the counter and generate a n update of registers. Note that the prescaler counter is cl eared too.(anyway the prescaler ratio is not affected)

REG_TIM_CNT

• Name : TIM counter

• Size : 32

• Address offset : 014h

• Read/write access : R

Timer count

Bit	Symbol	Access	Reset	Description
31:0	CNT	R	0x0	Counter value

REG_TIM_ARR

• Name : TIM auto-reload register

• Size : 32

• Address offset : 01Ch

• Read/write access : R/W

Auto-reload value

Bit	Symbol	Access	Reset	Description
31:0	ARR	R/W	0xFFFFFFFF	The value to be loaded in the actual auto-reload register. It can be preloaded by setting ARPE bit in TIM_CR.

REG_TIM_SEC

• Name : TIM security control register

• Size : 32

• Address offset : 020h

• Read/write access : R/W

Security status

Bit	Symbol	Access	Reset	Description
31:1	RSVD	R	-	Reserved
0	SEC	R/W	0x0	Secure timer enable. 0: This is a non-secure timer. All its registers except TIMx_SEC can be accessed from both secure and non-secure address. As a result, both secure and non-secure code ca n access it. 1: This is a secure timer. All its registers can only be accessed from secure address. As a result, only secure co de can access it. Non-secure code can’t access it throug h non-secure address.

REG_TIM_BASIC_DUMMY

• Name : Timer Baisc Dummy Register

• Size : 32

• Address offset : 024h

• Read/write access : R/W

Dummy register

Bit	Symbol	Access	Reset	Description
31:0	DUMMY	R/W	ffffh	Dummy register

Capture Timer Registers

Name	Address offset	Access	Description
REG_TIM_EN	000h	R/W	User can configure and observe the counter operation
REG_TIM_CR	004h	R/W	Registers about the update operation
REG_TIM_DIER	008h	R/W	Interrupt enable
REG_TIM_SR	00Ch	R/W	Registers about timer status
REG_TIM_EGR	010h	R/W	Update generation user defined
REG_TIM_CNT	014h	R	Timer count
REG_TIM_PSC	018h	R/W	Prescaler value
REG_TIM_ARR	01Ch	R/W	Auto-reload value
REG_TIM_CCR0	024h	R/W	Input capture configuration and the data of capture
REG_TIM_PULSE_DBC	028h	R/W
REG_TIM_PULSE_DUMMY	02Ch	R/W	Dummy register

REG_TIM_EN

• Name : TIM enable register

• Size : 32

• Address offset : 000h

• Read/write access : R/W

User can configure and observe the counter operation

Bit	Symbol	Access	Reset	Description
31:17	RSVD	R	-	Reserved
16	CNT_EN	R	0x0	Counter working status 0: counter is stoppped 1: counter is working
15:9	RSVD	R	-	Reserved
8	CEN	R	0x0	Counter run status 0: counter is disabled 1: counter is enabled
7:2	RSVD	R	-	Reserved
1	CNT_STOP	R/W	0x0	Disable the counter. Poll CNT_RUN to see the counter status. If CNT_RUN is 0, it means that the counter has been disabled internally.
0	CNT_START	R/W	0x0	Enable the counter. Poll CNT_RUN to see the counter status. If CNT_RUN is 1, it means that the counter has been enabled internally.

REG_TIM_CR

• Name : TIM control register

• Size : 32

• Address offset : 004h

• Read/write access : R/W

Registers about the update operation

Bit	Symbol	Access	Reset	Description
31:5	RSVD	R	-	Reserved
4	ARPE	R/W	0x0	Enable auto-reload preloading 0: TIM_ARR register is not buffered 1: TIM_ARR register is buffered
3	RSVD	R	-	Reserved
2	URS	R/W	0x0	Update request source 0: counter overflow and setting the UG bit 1: counter overflow
1	UDIS	R/W	0x0	Disable UEV. Shadow registers keep their values. Otherwise, buffered registers are then loaded with their preload values when UEV happen.
0	RSVD	R	-	Reserved

REG_TIM_DIER

• Name : TIM interupt enable register

• Size : 32

• Address offset : 008h

• Read/write access : R/W

Interrupt enable

Bit	Symbol	Access	Reset	Description
31:2	RSVD	R	-	Reserved
1	CC0IE	R/W	0x0	Enable Capture/Compare 0 interrupt
0	UIE	R/W	0x0	Enable update interrupt

REG_TIM_SR

• Name : TIM status register

• Size : 32

• Address offset : 00Ch

• Read/write access : R/W

Registers about timer status

Bit	Symbol	Access	Reset	Description
31	UG_DONE	R	0x1	UG operation status This bit is cleared by hardware when the UG bit in the TIMx_ EGR register is set. When the UG operation is done, hardware set this bit to ‘1’. So, software can poll this bit to see t he UG operation status.
30:2	RSVD	R	-	Reserved
1	CC0IF	R/W	0x0	Capture/Compare 0 interrupt flag CC0 channel configured as pulse mode 0: This bit is set when TRGI is transferred to inactive level f rom active level. CC0 channel configured as pulse mode 1: This bit is set by hardware when the counter overflows. It i s cleared by software.
0	UIF	R/W	0x0	Update interrupt flag

REG_TIM_EGR

• Name : TIM event generation register

• Size : 32

• Address offset : 010h

• Read/write access : R/W

Update generation user defined

Bit	Symbol	Access	Reset	Description
31:2	RSVD	R	-	Reserved
1	CC0G	R/W	0x0	Capture/Compare 0 generation. This bit is set by software an d is automatically cleared by hardware. A Capture/Compare ev ent is generated on channel 0: the current value of the coun ter is captured in TIM_CCR0 register. The CC0IF flag is set, the corresponding interrupt or request is sent if enabled.
0	UG	R/W	0x0	Update generation. Re-initialize the counter and generate a n update of registers. Note that the prescaler counter is cl eared too.(anyway the prescaler ratio is not affected)

REG_TIM_CNT

• Name : TIM counter

• Size : 32

• Address offset : 014h

• Read/write access : R

Timer count

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	CNT	R	0x0	Counter value

REG_TIM_PSC

• Name : TIM prescaler register

• Size : 32

• Address offset : 018h

• Read/write access : R/W

Prescaler value

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	PSC	R/W	0x0	Prescaler value. PSC contains the value to be loaded in the actual prescaler register at each UEV(including when the cou nter is cleared through UG bit of TIM_EGR register).

REG_TIM_ARR

• Name : TIM auto-reload register

• Size : 32

• Address offset : 01Ch

• Read/write access : R/W

Auto-reload value

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	ARR	R/W	0xFFFF	The value to be loaded in the actual auto-reload register. It can be preloaded by setting ARPE bit in TIM_CR.

REG_TIM_CCR0

• Name : TIM Capture register

• Size : 32

• Address offset : 024h

• Read/write access : R/W

Input capture configuration and the data of capture

Bit	Symbol	Access	Reset	Description
31:29	RSVD	R	-	Reserved
28	CC0PM	R/W	0x0	CC0 pulse mode 0: pulse mode 0 1: pulse mode 1
27	RSVD	R	-	Reserved
26	CC0P	R/W	0x0	CC0 channel configured as output: 0: OC0 active high 1: OC0 ative low CC0 channel configured as input: 0: positive edge of TRGI is active for capture 1: negative edge of TRGI is active for capture
25	RSVD	R	-	Reserved
24	CC0E	R/W	0x0	Enable CC0
23:16	RSVD	R	-	Reserved
15:0	CCR0	R/W	0x0	Capture/Compare 0 value CC0 channel configured as pulse mode 0: the pulse width of T RGI CC0 channel configured as pulse mode 1: the pulse number of TRGI when the counter counts from 0 to ARR

REG_TIM_PULSE_DBC

• Name : Timer Pulse dbc Register

• Size : 32

• Address offset : 028h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:1	R_DBC_CYC	R/W	0x0	Dbc cycle
0	R_DBC_FEN	R/W	0x0	Enable debounce for pluse 0:disable 1: enable

REG_TIM_PULSE_DUMMY

• Name : Timer Pulse Dummy Register

• Size : 32

• Address offset : 02Ch

• Read/write access : R/W

Dummy register

Bit	Symbol	Access	Reset	Description
31:0	DUMMY	R/W	ffffh	Dummy register

PWM timer Registers

Name	Address offset	Access	Description
REG_TIM_EN	000h	R/W	User can configure and observe the counter operation
REG_TIM_CR	004h	R/W	Registers about the update operation and the work mode configuration
REG_TIM_DIER	008h	R/W	Interrupt enable
REG_TIM_SR	00Ch	R/W	Registers about timer interrupt and update status
REG_TIM_EGR	010h	R/W	Update generation user defined
REG_TIM_CNT	014h	R	Timer count
REG_TIM_PSC	018h	R/W	Prescaler value
REG_TIM_ARR	01Ch	R/W	Auto-reload value
REG_RSVD	020h	R	This is a security register for TIM0-7.
REG_TIM_CCR0	024h	R/W	Refer to register 24h
REG_TIM_CCR1	028h	R/W	Refer to register 24h
REG_TIM_CCR2	02Ch	R/W	Refer to register 24h
REG_TIM_CCR3	030h	R/W	Refer to register 24h
REG_TIM_PSYNC0	034h	R/W	Refer to register 44h
REG_TIM_PSYNC1	038h	R/W	Refer to register 44h
REG_TIM_PSYNC2	03Ch	R/W	Refer to register 44h
REG_TIM_PSYNC3	040h	R/W	Refer to register 44h
REG_TIM_PHASECNT0	044h	R	Refer to register 64h
REG_TIM_PHASECNT1	048h	R	Refer to register 64h
REG_TIM_PHASECNT2	04Ch	R	Refer to register 64h
REG_TIM_PHASECNT3	050h	R	Refer to register 64h
REG_TIM_PWM_DUMMY	054h	R/W	Dummy register

REG_TIM_EN

• Name : TIM enable register

• Size : 32

• Address offset : 000h

• Read/write access : R/W

User can configure and observe the counter operation

Bit	Symbol	Access	Reset	Description
31:17	RSVD	R	-	Reserved
16	CNT_EN	R	0x0	Counter working status 0: counter is stoppped 1: counter is working
15:9	RSVD	R	-	Reserved
8	CEN	R	0x0	Counter run status 0: counter is disabled 1: counter is enabled
7:2	RSVD	R	-	Reserved
1	CNT_STOP	R/W	0x0	Disable the counter. Poll CNT_RUN to see the counter status. If CNT_RUN is 0, it means that the counter has been disabled internally.
0	CNT_START	R/W	0x0	Enable the counter. Poll CNT_RUN to see the counter status. If CNT_RUN is 1, it means that the counter has been enabled internally.

REG_TIM_CR

• Name : TIM control register

• Size : 32

• Address offset : 004h

• Read/write access : R/W

Registers about the update operation and the work mode configuration

Bit	Symbol	Access	Reset	Description
31:10	RSVD	R	-	Reserved
9:8	ETP	R/W	0x0	External trigger polarity(TRGI) 0: positive edge is active 1: negative edge is active 2 or 3: both edge is active Note these bits are only valid in one-pulse mode.
7:5	RSVD	R	-	Reserved
4	ARPE	R/W	0x0	Enable auto-reload preloading 0: TIM_ARR register is not buffered 1: TIM_ARR register is buffered
3	OPM	R/W	0x0	One-pulse mode 0: counter is not stopped at UEV 1: counter stops counting at next UEV
2	URS	R/W	0x0	Update request source 0: counter overflow and setting the UG bit 1: counter overflow
1	UDIS	R/W	0x0	Disable UEV. Shadow registers keep their values. Otherwise, buffered registers are then loaded with their preload values when UEV happen.
0	RSVD	R	-	Reserved

REG_TIM_DIER

• Name : TIM interupt enable register

• Size : 32

• Address offset : 008h

• Read/write access : R/W

Interrupt enable

Bit	Symbol	Access	Reset	Description
31:20	RSVD	R	-	Reserved
19	UIE3	R/W	0x0	Enable channel 3 update interrupt
18	UIE2	R/W	0x0	Enable channel 2 update interrupt
17	UIE1	R/W	0x0	Enable channel 1 update interrupt
16	UIE0	R/W	0x0	Enable channel 0 update interrupt
15:5	RSVD	R	-	Reserved
4	CC3IE	R/W	0x0	Enable Capture/Compare 3 interrupt
3	CC2IE	R/W	0x0	Enable Capture/Compare 2 interrupt
2	CC1IE	R/W	0x0	Enable Capture/Compare 1 interrupt
1	CC0IE	R/W	0x0	Enable Capture/Compare 0 interrupt
0	UIE	R/W	0x0	Enable counter update interrupt

REG_TIM_SR

• Name : TIM status register

• Size : 32

• Address offset : 00Ch

• Read/write access : R/W

Registers about timer interrupt and update status

Bit	Symbol	Access	Reset	Description
31	UG_DONE	R	0x1	UG operation status This bit is cleared by hardware when the UG bit in the TIMx_ EGR register is set. When the UG operation is done, hardware set this bit to ‘1’. So, software can poll this bit to see t he UG operation status.
30:20	RSVD	R	-	Reserved
19	UIF3	R/W	0x0	Refer to UIF0 description
18	UIF2	R/W	0x0	Refer to UIF0 description
17	UIF1	R/W	0x0	Refer to UIF0 description
16	UIF0	R/W	0x0	Update interrupt flag of channel0 This flag is set by hardware when the UIE0 bit in the TIMx_E GR register is set, and update interrupt of channel0 happens .
15:5	RSVD	R	-	Reserved
4	CC3IF	R/W	0x0	Refer to CC0IF description
3	CC2IF	R/W	0x0	Refer to CC0IF description
2	CC1IF	R/W	0x0	Refer to CC0IF description
1	CC0IF	R/W	0x0	Capture/Compare 0 interrupt flag Channel CC0 configured as output: This flag is set by hardware when the counter TIM_CNT value matches the value of TIM_CCR0 register. It is cleared by sof tware. Channel CC0 configured as input: This flag is set by hardware and the counter value has been captured in CCR0 field of TIM_CCR0 register when an active e dge has been Detected. It is cleared by software.
0	UIF	R/W	0x0	Update interrupt flag

REG_TIM_EGR

• Name : TIM event generation register

• Size : 32

• Address offset : 010h

• Read/write access : R/W

Update generation user defined

Bit	Symbol	Access	Reset	Description
31:5	RSVD	R	-	Reserved
4	CC3G	R/W	0x0	Refer to CC0G description
3	CC2G	R/W	0x0	Refer to CC0G description
2	CC1G	R/W	0x0	Refer to CC0G description
1	CC0G	R/W	0x0	Capture/Compare 0 generation This bit is set by software and is automatically cleared by hardware. Channel CC0 configured as output: The CC0IF flag is set, the corresponding interrupt or reque st is sent if enabled. Channel CC0 configured as input: The current value of counter is capture in CCR0 field of TIM _CCR0 register. The CC0IF flag is set, the corresponding int errupt or request is sent if enabled.
0	UG	R/W	0x0	Update generation. Re-initialize the counter and generate a n update of registers. Note that the prescaler counter is cl eared too.(anyway the prescaler ratio is not affected)

REG_TIM_CNT

• Name : TIM counter

• Size : 32

• Address offset : 014h

• Read/write access : R

Timer count

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	CNT	R	0x0	Counter value

REG_TIM_PSC

• Name : TIM prescaler register

• Size : 32

• Address offset : 018h

• Read/write access : R/W

Prescaler value

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	PSC	R/W	0x0	Prescaler value. PSC contains the value to be loaded in the actual prescaler register at each UEV(including when the cou nter is cleared through UG bit of TIM_EGR register).

REG_TIM_ARR

• Name : TIM auto-reload register

• Size : 32

• Address offset : 01Ch

• Read/write access : R/W

Auto-reload value

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	ARR	R/W	0xFFFF	The value to be loaded in the actual auto-reload register. It can be preloaded by setting ARPE bit in TIM_CR.

REG_RSVD

• Name : Reserved register

• Size : 32

• Address offset : 020h

• Read/write access : R

This is a security register for TIM0-7.

Bit	Symbol	Access	Reset	Description
31:0	RSVD	R	-	Reserved

REG_TIM_CCR0

• Name : TIM Capture/Compare register 0

• Size : 32

• Address offset : 024h

• Read/write access : R/W

Refer to register 24h

Bit	Symbol	Access	Reset	Description
31:30	RSVD	R	-	Reserved
29	OPM_DL0	R/W	0x0	One Pulse Mode default level 0: default level is 0 1: default level is 1 This bit takes effect only in PWM output mode’s One-Pulse- Mode
28	RSVD	R	-	Reserved
27	CC0M	R/W	0x0	CC0 working mode 0: PWM mode 1: Input capture mode
26	CC0P	R/W	0x0	CC0 channel configured as output: 0: OC0 active high 1: OC0 ative low CC0 channel configured as input: 0: positive edge of TRGI is active for capture 1: negative edge of TRGI is active for capture
25	OC0PE	R/W	0x0	Enable output capture 0 preload 0: disable preload register on CCR0. CCR0 can be written at any time, the new value is taken into account immediate ly. 1: enable preload register on CCR0. Read/Write operations access the preload register. CCR0 preload value is loaded in the active Register at each UEV.
24	CC0E	R/W	0x0	Enable CC0
23:16	RSVD	R	-	Reserved
15:0	CCR0	R/W	0x0	Capture/Compare 0 value CC0 channel configured as output: CCR0 is the value to be loaded in the actual capture/compare 0 register(preload value). It is loaded permanently if the p reload feature Is not selected in the OC0PE bit.Else the preload value is c opied in the active capture/compare 0 register when an UEV o ccurs.The active Capture/compare 0 register contains the value to be compared to the counter TIM_CNT and signalled on OC0 output. CC0 channel configured as pulse mode 1: CCR0 is the counter value transferred by the last input capt ure event(TRGI)

REG_TIM_CCR1

• Name : TIM Capture/Compare register 1

• Size : 32

• Address offset : 028h

• Read/write access : R/W

Refer to register 24h

Bit	Symbol	Access	Reset	Description
31:30	RSVD	R	-	Reserved
29	OPM_DL1	R/W	0x0	One Pulse Mode default level 0: default level is 0 1: default level is 1 This bit takes effect only in PWM output mode’s One-Pulse- Mode
28	RSVD	R	-	Reserved
27	CC1M	R/W	0x0	CC1 working mode 0: PWM mode 1: Input capture mode
26	CC1P	R/W	0x0	CC1 channel configured as output: 0: OC1 active high 1: OC1 ative low CC1 channel configured as input: 0: positive edge of TRGI is active for capture 1: negative edge of TRGI is active for capture
25	OC1PE	R/W	0x0	Enable output capture 1 preload 0: disable preload register on CCR1. CCR1 can be written at any time, the new value is taken into account immediate ly. 1: enable preload register on CCR1. Read/Write operations access the preload register. CCR1 preload value is loaded in the active Register at each UEV.
24	CC1E	R/W	0x0	Enable CC1
23:16	RSVD	R	-	Reserved
15:0	CCR1	R/W	0x0	Capture/Compare 1 value CC1 channel configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register(preload value). It is loaded permanently if the p reload feature Is not selected in the OC1PE bit.Else the preload value is c opied in the active capture/compare 1 register when an UEV o ccurs.The active Capture/compare 1 register contains the value to be compared to the counter TIM_CNT and signalled on OC1 output. CC1 channel configured as pulse mode 1: CCR1 is the counter value transferred by the last input capt ure event(TRGI)

REG_TIM_CCR2

• Name : TIM Capture/Compare register 2

• Size : 32

• Address offset : 02Ch

• Read/write access : R/W

Refer to register 24h

Bit	Symbol	Access	Reset	Description
31:30	RSVD	R	-	Reserved
29	OPM_DL2	R/W	0x0	One Pulse Mode default level 0: default level is 0 1: default level is 1 This bit takes effect only in PWM output mode’s One-Pulse- Mode
28	RSVD	R	-	Reserved
27	CC2M	R/W	0x0	CC2 working mode 0: PWM mode 1: Input capture mode
26	CC2P	R/W	0x0	CC2 channel configured as output: 0: OC2 active high 1: OC2 ative low CC2 channel configured as input: 0: positive edge of TRGI is active for capture 1: negative edge of TRGI is active for capture
25	OC2PE	R/W	0x0	Enable output capture 2 preload 0: disable preload register on CCR2. CCR2 can be written at any time, the new value is taken into account immediate ly. 1: enable preload register on CCR2. Read/Write operations access the preload register. CCR2 preload value is loaded in the active Register at each UEV.
24	CC2E	R/W	0x0	Enable CC2
23:16	RSVD	R	-	Reserved
15:0	CCR2	R/W	0x0	Capture/Compare 2 value CC2 channel configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register(preload value). It is loaded permanently if the p reload feature Is not selected in the OC2PE bit.Else the preload value is c opied in the active capture/compare 2 register when an UEV o ccurs.The active Capture/compare 2 register contains the value to be compared to the counter TIM_CNT and signalled on OC2 output. CC2 channel configured as pulse mode 1: CCR2 is the counter value transferred by the last input capt ure event(TRGI)

REG_TIM_CCR3

• Name : TIM Capture/Compare register 3

• Size : 32

• Address offset : 030h

• Read/write access : R/W

Refer to register 24h

Bit	Symbol	Access	Reset	Description
31:30	RSVD	R	-	Reserved
29	OPM_DL3	R/W	0x0	One Pulse Mode default level 0: default level is 0 1: default level is 1 This bit takes effect only in PWM output mode’s One-Pulse- Mode
28	RSVD	R	-	Reserved
27	CC3M	R/W	0x0	CC3 working mode 0: PWM mode 1: Input capture mode
26	CC3P	R/W	0x0	CC3 channel configured as output: 0: OC3 active high 1: OC3 ative low CC3 channel configured as input: 0: positive edge of TRGI is active for capture 1: negative edge of TRGI is active for capture
25	OC3PE	R/W	0x0	Enable output capture 3 preload 0: disable preload register on CCR3. CCR3 can be written at any time, the new value is taken into account immediate ly. 1: enable preload register on CCR3. Read/Write operations access the preload register. CCR3 preload value is loaded in the active Register at each UEV.
24	CC3E	R/W	0x0	Enable CC3
23:16	RSVD	R	-	Reserved
15:0	CCR3	R/W	0x0	Capture/Compare 3 value CC3 channel configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register(preload value). It is loaded permanently if the p reload feature Is not selected in the OC3PE bit.Else the preload value is c opied in the active capture/compare 3 register when an UEV o ccurs.The active Capture/compare 3 register contains the value to be compared to the counter TIM_CNT and signalled on OC3 output. CC3 channel configured as pulse mode 1: CCR3 is the counter value transferred by the last input capt ure event(TRGI)

REG_TIM_PSYNC0

• Name : TIM Phase Synchronization register 0

• Size : 32

• Address offset : 034h

• Read/write access : R/W

Refer to register 44h

Bit	Symbol	Access	Reset	Description
31:28	RSVD	R	-	Reserved
27	SYNCEN0	R/W	0x0	Enable phase sync function in channel 0. Phase sync takes ef fect only in output PWM mode.
26	SYNCDIR0	R/W	0x0	Phase sync direction to the reference counter: 0:delay to the reference counter 1:ahead to the reference counter
25	SYNCPE0	R/W	0x0	Enable sync phase parameter preload 0: disable preload register on PSYNC0. PSYNC0 can be writ ten at any time, the new value is taken into account immed iately. 1: enable preload register on PSYNC0. Read/Write operatio ns access the preload register. PSYNC0 preload value is l oaded in the active Register at each UEV.
24:16	RSVD	R	-	Reserved
15:0	SYNCPHASE0	R/W	0x0	The deviation value of channel0 to the reference counter

REG_TIM_PSYNC1

• Name : TIM Phase Synchronization register 1

• Size : 32

• Address offset : 038h

• Read/write access : R/W

Refer to register 44h

Bit	Symbol	Access	Reset	Description
31:28	RSVD	R	-	Reserved
27	SYNCEN1	R/W	0x0	Enable phase sync function in channel 1. Phase sync takes ef fect only in output PWM mode.
26	SYNCDIR1	R/W	0x0	Phase sync direction to the reference counter: 0:delay to the reference counter 1:ahead to the reference counter
25	SYNCPE1	R/W	0x0	Enable sync phase parameter preload 0: disable preload register on PSYNC1. PSYNC1 can be writ ten at any time, the new value is taken into account immed iately. 1: enable preload register on PSYNC1. Read/Write operatio ns access the preload register. PSYNC1 preload value is l oaded in the active Register at each UEV.
24:16	RSVD	R	-	Reserved
15:0	SYNCPHASE1	R/W	0x0	The deviation value of channel1 to the reference counter

REG_TIM_PSYNC2

• Name : TIM Phase Synchronization register 2

• Size : 32

• Address offset : 03Ch

• Read/write access : R/W

Refer to register 44h

Bit	Symbol	Access	Reset	Description
31:28	RSVD	R	-	Reserved
27	SYNCEN2	R/W	0x0	Enable phase sync function in channel 2. Phase sync takes ef fect only in output PWM mode.
26	SYNCDIR2	R/W	0x0	Phase sync direction to the reference counter: 0:delay to the reference counter 1:ahead to the reference counter
25	SYNCPE2	R/W	0x0	Enable sync phase parameter preload 0: disable preload register on PSYNC2. PSYNC2 can be writ ten at any time, the new value is taken into account immed iately. 1: enable preload register on PSYNC2. Read/Write operatio ns access the preload register. PSYNC2 preload value is l oaded in the active Register at each UEV.
24:16	RSVD	R	-	Reserved
15:0	SYNCPHASE2	R/W	0x0	The deviation value of channel2 to the reference counter

REG_TIM_PSYNC3

• Name : TIM Phase Synchronization register 3

• Size : 32

• Address offset : 040h

• Read/write access : R/W

Refer to register 44h

Bit	Symbol	Access	Reset	Description
31:28	RSVD	R	-	Reserved
27	SYNCEN3	R/W	0x0	Enable phase sync function in channel 3. Phase sync takes ef fect only in output PWM mode.
26	SYNCDIR3	R/W	0x0	Phase sync direction to the reference counter: 0:delay to the reference counter 1:ahead to the reference counter
25	SYNCPE3	R/W	0x0	Enable sync phase parameter preload 0: disable preload register on PSYNC3. PSYNC3 can be writ ten at any time, the new value is taken into account immed iately. 1: enable preload register on PSYNC3. Read/Write operatio ns access the preload register. PSYNC3 preload value is l oaded in the active Register at each UEV.
24:16	RSVD	R	-	Reserved
15:0	SYNCPHASE3	R/W	0x0	The deviation value of channel3 to the reference counter

REG_TIM_PHASECNT0

• Name : TIM phase counter register 0

• Size : 32

• Address offset : 044h

• Read/write access : R

Refer to register 64h

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	CNT0	R	0x0	Phase counter value of channel0

REG_TIM_PHASECNT1

• Name : TIM phase counter register 1

• Size : 32

• Address offset : 048h

• Read/write access : R

Refer to register 64h

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	CNT1	R	0x0	Phase counter value of channel1

REG_TIM_PHASECNT2

• Name : TIM phase counter register 2

• Size : 32

• Address offset : 04Ch

• Read/write access : R

Refer to register 64h

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	CNT2	R	0x0	Phase counter value of channel2

REG_TIM_PHASECNT3

• Name : TIM phase counter register 3

• Size : 32

• Address offset : 050h

• Read/write access : R

Refer to register 64h

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	CNT3	R	0x0	Phase counter value of channel3

REG_TIM_PWM_DUMMY

• Name : Timer PWM Dummy Register

• Size : 32

• Address offset : 054h

• Read/write access : R/W

Dummy register

Bit	Symbol	Access	Reset	Description
31:0	DUMMY	R/W	ffffh	Dummy register