Debug timer is a common timestamp for all debug messages originating from all on-die processors and processor execution domains (application, kernel, and firmware). It also includes a lock-free increment counter.

Features

• Simple 32-bit wrap timer

• A lock-free counter

Functional Description

The debug timer has two types of clock input: XTAL and internal 32K.

• When selecting XTAL with an internal divider, XTAL can generate a fixed 1us time interval between each time increments.

• When selecting 32K clock, the counter increases 31us every 30.5us.

The counter can be enabled and disabled, by default it is enabled. The counter wraps around to zero and continues to count once it reaches 64’hFFFFFFFF_FFFFFFFF. A write to timestamp will set the current value of the timestamp, however, it must continue to increment at the base of the new setting value if the writing happens when the counter is active.

The XTAL clock may be gated in sleep mode. If you select XTAL as the clock source in sleep mode, the debug timer will stop counting, and all the registers will be maintained. The counter will resume the increment immediately after XTAL resumes. You can select 32K as the clock source in sleep mode; however, the counter itself needs 220us to do switch clock before continuing counting. In this period, writing to this IP is not allowed. All the registers will be reset to the initial values after wakeup from deepsleep mode.

The lock-free counter is a read trigger increase counter, can be used to debug timing issues in multicore SoC. Arbitration is implemented at the bus level. The counter has two read windows: read will trigger the counter increases one if reading from DBGT_ATOM_INC, and will not increase if reading from DBGT_ATOM.

The timestamp and atom should be reset to zero on the rising edge of the ENABLE bit (DBGT_CTRL [0]).

Registers

The following table lists the memory map of the debug timer registers, and the base address is 0x4081_7000.

Name	Address offset	Access	Description
REG_DBGT_CTRL	000h	R/W	This register contains the configuration of debugtimer’s clock and enable signal
REG_DBGT_CRV0	004h	R/W	Timestamp count
REG_DBGT_CRV1	008h	R/W	Timestamp count
REG_DBGT_ATOM_INC	00Ch	R	Atom count add 1
REG_DBGT_ATOM	010h	R/W	Atom count value
REG_DBGT_SCRATCH	014h	R/W	User defined register
REG_DBGTIM_DUMMY	018h	R/W	Dummy register

REG_DBGT_CTRL

• Name : debugtimer control register

• Size : 32

• Address offset : 000h

• Read/write access : R/W

This register contains the configuration of debugtimer’s clock and enable signal

Bit	Symbol	Access	Reset	Description
31:2	RSVD	R	-	Reserved
1	DBGT_CRV_SET	R/W	0h	Set dbgt_crv0/1 to dbgtcnt
0	ENABLE	R/W	1h	Debug timer enable. 1: The counter is enabled. 0: The counter is disabled.

REG_DBGT_CRV0

• Name : debugtimer count register

• Size : 32

• Address offset : 004h

• Read/write access : R/W

Timestamp count

Bit	Symbol	Access	Reset	Description
31:0	DBGT_CRV0	R/W	0h	Dbgtcnt[31:0].Continuing to count from 0 once it’s reached 3 2’Hffffffff

REG_DBGT_CRV1

• Name : debugtimer count register

• Size : 32

• Address offset : 008h

• Read/write access : R/W

Timestamp count

Bit	Symbol	Access	Reset	Description
31:0	DBGT_CRV1	R/W	0h	Dbgtcnt[63:32].Continuing to count from 0 once it’s reached 32’hFFFFFFFF

REG_DBGT_ATOM_INC

• Name : debugtimer atom read increase

• Size : 32

• Address offset : 00Ch

• Read/write access : R

Atom count add 1

Bit	Symbol	Access	Reset	Description
31:0	DBGT_ATOM_INC	R	0h	Each read will increase 1 and return to the increased value to bus.

REG_DBGT_ATOM

• Name : debugtimer atom

• Size : 32

• Address offset : 010h

• Read/write access : R/W

Atom count value

Bit	Symbol	Access	Reset	Description
31:0	DBGT_ATOM	R/W	0h	Return the last increased value of atom counter

REG_DBGT_SCRATCH

• Name : debugtimer scratch

• Size : 32

• Address offset : 014h

• Read/write access : R/W

User defined register

Bit	Symbol	Access	Reset	Description
31:0	DBGT_SCRATCH	R/W	0h	Reserved for user use

REG_DBGTIM_DUMMY

• Name : Debug TimerDummy Register

• Size : 32

• Address offset : 018h

• Read/write access : R/W

Dummy register

Bit	Symbol	Access	Reset	Description
31:0	DUMMY	R/W	ffffh	Dummy register