按键扫描

概述

作为键盘扫描设备,Key-Scan 可应用于简单按键、遥控器甚至游戏手柄。它需要准确及时地扫描按键按下和释放的操作。

该设备的主要优势在于能让 CPU 免于持续扫描按键盘。当有操作发生时,Key-Scan 会触发相应中断,及时通知 CPU。此外,大部分时间芯片可处于低功耗状态,仅在处理按键事件时快速唤醒。

功能特性

  • 支持最大 8 x 8(64 键)按键矩阵,仅需 16 个 GPIO。

  • 行数和列数可配置,适配不同大小的按键阵列。

  • 硬件消抖,支持每次扫描周期的消抖时间配置。

  • 扫描时钟频率、扫描间隔和按键释放时间均可配置。

  • 完善的中断管理功能:中断生成、屏蔽、清除和状态报告。

  • 支持多键同时检测。

  • 内置 FIFO 缓冲区(12 位宽,16 深度)存储按下和释放事件。

  • 提供两种工作模式:

    • 事件触发模式:响应按下和释放事件。

    • 常规扫描模式:高优先级连续扫描。

  • 低功耗支持:按键事件可唤醒处于休眠的 CPU。

  • 卡滞按键检测与处理。

功能描述

工作原理

Key-Scan 的模块原理框图如 Key-Scan 原理框图 所示。Key-Scan 包含六大部分:

  • 中断控制:中断的管理与控制。

  • 控制寄存器和 FIFO:Key-Scan 配置与 FIFO 管理。

  • 时钟:Key-Scan 时钟,131K 时钟用于按键卡滞检测和低功耗唤醒

  • 键盘控制:包含 Key-Scan 控制、唤醒控制、按键输入/输出控制。

  • 键盘阵列:最多 8*8,使用 16 个 GPIO。

../../_images/keyscan_block_diagram.svg

Key-Scan 原理框图

以 8*8 按键阵列为例,典型应用连接如 8 x 8 键盘,需外接按键模块。

../../_images/keyscan_array.svg

8 x 8 键盘

初始时,所有列为低电平输出,所有行为输入并开启内部上拉。

当有一个或多个按键被按下(对应列与行短接)时,相关行输入电平由高变低,从而触发内部状态机启动 Key-Scan 周期,确定按键被按下的行列坐标。状态机首先将第一列输出为低电平,其余列置于高阻态,然后扫描所有行判定按键状态,接着第二列输出低电平,如此类推至最后一列。首先扫描电路等待第一次消抖时间并执行首轮扫描,随后再次等待消抖时间进行第二次扫描。两次扫描后电路确认当前按键状态,并与内部按键状态表比对,判断按键的按下或释放。在一次完整扫描(full scan)结束后,按键按下或释放事件被存入按键事件 FIFO。每次完整扫描的消抖时间可配置,如 Key-Scan 流程 所示。

../../_images/keyscan_flow.svg

Key-Scan 流程

每次完整扫描(full scan)的扫描间隔可配置。当所有按键释放后,将启动释放定时器进行确认,随后触发全部释放中断,状态机进入空闲状态。Key-Scan 时序信息见 Key-Scan 时序

../../_images/keyscan_timing.svg

Key-Scan 时序

工作模式

Key-Scan 支持两种工作模式:

  • 事件触发模式:每次按下或释放,仅向 FIFO 存储一次事件。

  • 常规扫描模式:每次全键扫描,持续写入按下事件,直到释放(此模式下仅记录按下事件)。

不同工作模式下的 Key-Scan 所示,展示了两种模式下的区别。

../../_images/keyscan_fifo_in_diff_work_mode.svg

不同工作模式下的 Key-Scan

FIFO

Key-Scan FIFO 结构 显示了两种工作模式下按键按下与释放时 FIFO 项的区别。

../../_images/keyscan_fifo_structure.svg

Key-Scan FIFO 结构


Bit

定义

说明

[8]

Event

1:按下事件 0:释放事件

[7:4]

Row index

1-8:对应 Row0-Row7

[3:0]

Column index

1-8:对应 Column0-Column7

若 FIFO 已满仍有新事件写入,将触发溢出中断。若 FIFO 为空时被读取,则触发过读中断。

按键值分配如下表:

Row0

Row1

Row2

Row3

Row4

Row5

Row6

Row7

Col0

11

12

13

14

15

16

17

18

Col1

21

22

23

24

25

26

27

28

Col2

31

32

33

34

35

36

37

38

Col3

41

42

43

44

45

46

47

48

Col4

51

52

53

54

55

56

57

58

Col5

61

62

63

64

65

66

67

68

Col6

71

72

73

74

75

76

77

78

Col7

81

82

83

84

85

86

87

88

时钟配置

Key-Scan 设计中包含两个时钟域,如 Key-Scan 时钟 所示。

  • 绿色部分属低功耗时钟域,低功耗模式下该域的时钟不断开

  • 蓝色部分属总线时钟域(40MHz),低功耗模式下可被门控(Gating)。在总线域,有些逻辑使用分频后的 scan_clk 扫描时钟。

../../_images/keyscan_clock.svg

Key-Scan 时钟

Key-Scan 触发信号由低频(131K)时钟产生。低功耗时钟检测到按键按下后,硬件再用扫描时钟进行扫描确认按键信息。

影子键

影子键(shadow key)问题可能出现在多键同时按下的场景。需三键组合(如 Ctrl+Alt+Del )或类似组合应用时,必须确保三键在排列上不会引发影子键问题。

为避免影子键,建议三键组合选择在不同的行与列上。如 按键矩阵示例 所示的键盘布局情况:

按键矩阵示例 中,例子为 4*3 键盘矩阵,接到 Row0~Row3、Col0~Col2 上,所有行配置为上拉输入,所有列为低电平输出。当有键按下时,相应行输入被拉低,扫描电路识别有按键按下,KeyScan 开始其扫描算法。该算法依次将低电平输出赋予各列,且每次仅一列被拉低,期间 KeyScan 持续读取行输入,判断本列中哪些键按下。

../../_images/keypad_example.svg

按键矩阵示例

多键同时按下时,若有影子键,则会产生“未实际按下但被检测到按下”的误判。如 影子键示意 中按下 11、12、21 后会触发影子键问题。因 Row1 通过 11 和 12 被拉到地电位,列 1 为低电时,扫描器检测到 Row0、Row1 均为低,导致误判 key 22 被按下(黄色高亮键)。

其原理为:按键矩阵将列与行相连。列 1 拉低时,经 12 传送到 Row0;当 11 被按下时,短接列 0 到地,再经 Row1 短接到列 0。于是 Row1 也到地,产生影子键。

../../_images/keyscan_shadow_key.svg

影子键示意

合理规划布局可避免影子键。正确三键组合布局 展示一种可正确识别三键组合的布局。

../../_images/keyscan_correct_3_key.svg

正确三键组合布局

按键卡滞

在实际的使用场景中,可能出现按键卡滞(按键按下之后没有被释放)的情况。为了确保在按键卡滞的情况下,系统仍然可以进入 low power 模式,且后面可以通过 Keyscan 唤醒,用户可以使能 auto_check_key_stuck 功能。

未使能 auto_check_key_stuck 时,只要按键卡滞,状态机便会持续扫描,除非按键松开,否则状态机无法进入 IDLE 状态。在这种情况下,系统无法进入到 low power 状态。

当使能 auto_check_key_stuck 时:

  1. 持续时间超出 stuck_time_threshold 后, KS_ISR_RAW.stuck_event_raw_int_status 位置 1;如已使能按键卡滞中断, KS_ISR.stuck_event_int_status 也位置 1,软件进入中断处理。

  2. 中断处理时读取 KS_STUCK_KEY_STATUS 和 KS_STUCK_KEY_ROW_STATUS1 定位卡滞按键所在行,并通过 KS_STUCK_CFG1 的 row_default_status 设置该行的默认状态,然后清除 KS_ICR 寄存器的中断。

  3. 若 all default 中断使能,进入 all default 中断处理流程。

  4. Keyscan 的状态机下次扫描时,会检测到 stuck row 的状态和配置的相同,则认为该行状态是正常,从而进入到 IDLE 状态,系统可以顺利进入到 low power 状态。

  5. IDLE 状态下,如果 stuck key 被释放,则 Keyscan 检测到该行的状态与配置的 default 状态不同从而 wakeup 电路,触发扫描,发现并上报 stuck interrupt。如果此时所有按键都释放并且使能 release,会有 all release interrupt。

  6. stuck 中断处理函数查看 KS_STUCK_KEY_STATUS 和 KS_STUCK_KEY_ROW_STATUS 获取 row 状态,软件需要再次通过 KS_STUCK_CFG1 的 row_default_status 重设 stuck key 所在行的初始状态。

  7. 如果使能了 all default,会有 all default 中断

卡滞按键检测流程 如下:

../../_images/keyscan_stuck_flow.svg

卡滞按键检测流程

小心

由于 auto_check_key_stuck 以行为单位配置卡滞按键所在行,需注意下列特殊情况:

  • 当按键卡滞时, 同一行其它按键 按下/释放:

    • 在低功耗状态,同一行其他 key 被按下或者松开,没办法唤醒。由于 key stuck,此时该 key 所在的 row 和 column 是连接的,从而把 row 拉低。当该 row 的其他 key 也有按下松开时不会影响该 row 的电平状态,所以并不能被检测到。

    • 唤醒后,在扫描期间,如果有 stuck key 同一行的其他 key 按下松开,可以正常被检测到。如果 wakeup 之后 release timer 已经跑完,状态机进入到 idle 状态,也无法检测到。

  • 当按键卡滞时, 不同行其它按键 按下/释放:

    • 非同一个 row 的 key 被按下/松开时,会将该 key 所在的 row 的电平状态拉低/拉高,所以可以被检测到。

    • 当处于低功耗状态,也可以正常唤醒电路

低功耗管理

在实际应用中,将 Key-Scan 保持在 Active 模式会导致高功耗。为了节省功耗并优化性能,Key-Scan 可以在 Sleep 模式下运行。在此期间,只有部分唤醒电路保持活动状态,时钟源为 131KHz。 在 Sleep 模式下,CPU 进入低功耗状态以降低能耗。当按下某个按键时,CPU 被唤醒,Key-Scan 开始扫描以确定哪些按键被按下。只要按键被按住,Key-Scan 就会持续扫描。 当所有按键都被释放且没有其他事件发生时,CPU 将返回睡眠模式。

当按键卡滞时,Key-Scan 进入空闲状态,卡住的行会直接连接到对应的列,导致该行的输出电平为低。上拉电阻会导致 I/O 端口产生漏电流。此时,该行上拉电阻产生的电流会沿着两条路径流动:一部分经卡住的按键流向对应的列,另一部分直接流向行输入引脚。这会增加功耗,见 按键卡滞引发漏电流原理示意 所示。

  • 如果未启用卡滞行的周期性检测功能,Key-Scan 会持续依次扫描每一行,包括卡滞的行。在这种情况下,持续的漏电流会使功耗持续升高。。

  • 为了减少漏电时长和功耗,必须开启卡滞行的周期性检测功能。软件可以配置两个定时参数: stuckrow_detect_timestuckrow_detect_time_interval。开启周期性检测后,Key-Scan 会按照 stuckrow_detect_time_interval 指定的时间间隔检查卡滞行的状态,每次检测的持续时间为 stuckrow_detect_time 设置的时长。在检测间隔期间,卡滞行的 I/O 引脚设置为无上拉(高阻态);在检测期间,设置为带上拉的输入。如果此时系统处于低功耗模式,卡滞行检测操作将不会唤醒系统。此外,对于其他未卡滞的行,会持续监测 I/O 端口状态,以确保响应速度。

备注

按键卡滞周期性检测仅在 auto_check_key_stuck 使能时可用。

../../_images/keyscan_stuck_current.svg

按键卡滞引发漏电流原理示意

寄存器

Base Address: 0x41013000

Name

Address offset

Access

Description

REG_KS_CLK_DIV

000h

R/W

This register is for Key-Scan scan clock division.

REG_KS_TIM_CFG0

004h

R/W

This is configuration register for timers.

REG_KS_TIM_CFG1

008h

R/W

This is configuration register for timers.

REG_KS_CTRL

00Ch

R/W

This register controls Key-Scan working mode and enable.

REG_KS_FIFO_CFG

010h

R/W

REG_KS_COL_CFG

014h

R/W

This register selects which column is used.

REG_KS_ROW_CFG

018h

R/W

This register selects which row is used.

REG_KS_DATA_NUM

01Ch

R

FIFO status register

REG_KS_DATA

020h

R

User can read scan result from this register, meaning pop one scan result from FIFO.

REG_KS_IMR

024h

R/W

This register is used to mask unused interrupts.

REG_KS_ICR

028h

R/W

This register is used to clear interrupts.

REG_KS_ISR

02Ch

R

This register is about interrupt flags.

REG_KS_ISR_RAW

030h

R

The raw interupt flags do not effected by interrupt mask register.

REG_KS_DISCHARGED_CTRL

034h

R/W

REG_KS_STUCK_CFG0

03Ch

R/W

REG_KS_STUCK_CFG1

040h

R/W

REG_KS_STUCK_CFG2

044h

R/W

REG_KS_STUCK_KEY_STATUS1

048h

R

REG_KS_STUCK_KEY_STATUS2

04Ch

R

REG_KS_STUCK_KEY_ROW_STATUS1

050h

R

REG_KS_DUMMY

058h

R/W

REG_KS_CLK_DIV

  • Name : clock division register

  • Size : 32

  • Address offset : 000h

  • Read/write access : R/W

This register is for Key-Scan scan clock division.

31:12 RSVD 11:0 KS_CLK_DIV

Bit

Symbol

Access

Reset

Description

31:12

RSVD

R

-

Reserved

11:0

KS_CLK_DIV

R/W

0x0

Scan clock = bus clock/(keyscan_clk_div+1)

REG_KS_TIM_CFG0

  • Name : Key-Scan configure register 0

  • Size : 32

  • Address offset : 004h

  • Read/write access : R/W

This is configuration register for timers.

31:28 RSVD 27:24 KS_POST_GUARD_TIMER 23:20 RSVD 19:16 KS_PRE_GUARD_TIMER 15:12 RSVD 11:0 KS_DEB_TIMER

Bit

Symbol

Access

Reset

Description

31:28

RSVD

R

-

Reserved

27:24

KS_POST_GUARD_TIMER

R/W

0x3

Post guard time for key column, post guard time = scan_clk * reg_col_gt_post_sel

23:20

RSVD

R

-

Reserved

19:16

KS_PRE_GUARD_TIMER

R/W

0x3

Pre guard time for key column, pre guard time = scan_clk * r eg_col_gt_pre_sel

15:12

RSVD

R

-

Reserved

11:0

KS_DEB_TIMER

R/W

0x0

Debounce counter n*scan_clk

REG_KS_TIM_CFG1

  • Name : Key-Scan configure register 1

  • Size : 32

  • Address offset : 008h

  • Read/write access : R/W

This is configuration register for timers.

31:28 RSVD 27:16 KS_INTERVAL_TIMER 15:12 RSVD 11:0 KS_RELEASE_TIMER

Bit

Symbol

Access

Reset

Description

31:28

RSVD

R

-

Reserved

27:16

KS_INTERVAL_TIMER

R/W

0x0

Scan interval counter n*scan_clk

15:12

RSVD

R

-

Reserved

11:0

KS_RELEASE_TIMER

R/W

0x0

Release detect counter n*scan_clk

REG_KS_CTRL

  • Name : Key-Scan control register

  • Size : 32

  • Address offset : 00Ch

  • Read/write access : R/W

This register controls Key-Scan working mode and enable.

31:4 RSVD 3 KS_WORK_MODE 2 RSVD 1 KS_BUSY_STATUS 0 KS_RUN_ENABLE

Bit

Symbol

Access

Reset

Description

31:4

RSVD

R

-

Reserved

3

KS_WORK_MODE

R/W

0x0

Work mode

  • 0x1: Event Trigger Mode

  • 0x0: Regular Scan Mode

2

RSVD

R

-

Reserved

1

KS_BUSY_STATUS

R

0x0

FSM busy status

0

KS_RUN_ENABLE

R/W

0x0

Enable internal Key-Scan scan clock. The Key-Scan clock en able must be after Key-Scan configuration is done.

  • 0x1: Key-Scan clock enabled (HW FSM starts to run).

  • 0x0: Key-Scan clock disabled (HW FSM stops).

REG_KS_FIFO_CFG

  • Name : FIFO configuration register

  • Size : 32

  • Address offset : 010h

  • Read/write access : R/W

31:28 RSVD 27:24 KS_FIFO_LIMIT_LEVEL 23:20 RSVD 19:16 KS_FIFO_TH_LEVEL 15:2 RSVD 1 KS_FIFO_OV_CTRL 0 KS_FIFO_CLR

Bit

Symbol

Access

Reset

Description

31:28

RSVD

R

-

Reserved

27:24

KS_FIFO_LIMIT_LEVEL

R/W

0x0

Limit the max allowable key number be pressed at a time

  • 0x0: no limit

  • 0x1: only one scan data is allowable in each key scan

  • 0x6: Max 6 scan data is allowable in each key scan

0x7 ~ 0xf: DO NOT USE

23:20

RSVD

R

-

Reserved

19:16

KS_FIFO_TH_LEVEL

R/W

0x0

FIFO threshold setup

15:2

RSVD

R

-

Reserved

1

KS_FIFO_OV_CTRL

R/W

0x0

FIFO overflow control

  • 0x0: rejects the new scan data when FIFO is full

  • 0x1: discard the oldest scan data when FIFO is full

0

KS_FIFO_CLR

R/W

0x0

Write 1to clear FIFO data

REG_KS_COL_CFG

  • Name : column selection register

  • Size : 32

  • Address offset : 014h

  • Read/write access : R/W

This register selects which column is used.

31:8 RSVD 7:0 KS_COL_SEL

Bit

Symbol

Access

Reset

Description

31:8

RSVD

R

-

Reserved

7:0

KS_COL_SEL

R/W

0x0

The control register to define which column is used.

  • 0x0: No key column selected

  • 0x1: Key column 0 selected

  • 0x2: Key column 1 selected

  • 0x3: Key column 0 and column 1 selected

  • 0x4: Key column 2 selected

  • ...

REG_KS_ROW_CFG

  • Name : row selection register

  • Size : 32

  • Address offset : 018h

  • Read/write access : R/W

This register selects which row is used.

31:8 RSVD 7:0 KS_ROW_SEL

Bit

Symbol

Access

Reset

Description

31:8

RSVD

R

-

Reserved

7:0

KS_ROW_SEL

R/W

0x0

The control register to define which row is used.

  • 0x0: No key row selected

  • 0x1: Key row 0 selected

  • 0x2: Key row 1 selected

  • 0x3: Key row 0 and row 1 selected

  • 0x4: Key row 2 selected

  • ...

REG_KS_DATA_NUM

  • Name : FIFO status

  • Size : 32

  • Address offset : 01Ch

  • Read/write access : R

FIFO status register

31:18 RSVD 17 KS_FIFO_FULL 16 KS_FIFO_EMPTY 15:5 RSVD 4:0 KS_FIFO_DATA_LEVEL

Bit

Symbol

Access

Reset

Description

31:18

RSVD

R

-

Reserved

17

KS_FIFO_FULL

R

0x0

FIFO full status

16

KS_FIFO_EMPTY

R

0x1

FIFO empty status

15:5

RSVD

R

-

Reserved

4:0

KS_FIFO_DATA_LEVEL

R

0x0

Number of entry in FIFO

REG_KS_DATA

  • Name : Key-Scan data register

  • Size : 32

  • Address offset : 020h

  • Read/write access : R

User can read scan result from this register, meaning pop one scan result from FIFO.

31:12 RSVD 11:0 KS_DATA

Bit

Symbol

Access

Reset

Description

31:12

RSVD

R

-

Reserved

11:0

KS_DATA

R

0x0

When reading this register, these bits return the value in t he Event FIFO.

  • Bit[11:8]: press or release event - 0x0: release event - 0x1: press event

  • Bit[7:4]: row index

  • Bit[3:0]: column index

REG_KS_IMR

  • Name : interrupt mask register

  • Size : 32

  • Address offset : 024h

  • Read/write access : R/W

This register is used to mask unused interrupts.

31:9 RSVD 8 KS_ALL_DEFAULT_INT_MASK 7 KS_STUCK_EVENT_INT_MASK 6 KS_SCAN_EVENT_INT_MASK 5 KS_FIFO_LIMIT_INT_MASK 4 KS_FIFO_OV_INT_MASK 3 KS_FIFO_FULL_INT_MASK 2 KS_SCAN_FINISH_INT_MASK 1 KS_FIFO_NOTEMPTY_INT_MASK 0 KS_ALL_RELEASE_INT_MASK

Bit

Symbol

Access

Reset

Description

31:9

RSVD

R

-

Reserved

8

KS_ALL_DEFAULT_INT_MASK

R/W

0x0

  • 0x0: Mask all default interrupt

7

KS_STUCK_EVENT_INT_MASK

R/W

0x0

  • 0x0: Mask stuck event interrupt

6

KS_SCAN_EVENT_INT_MASK

R/W

0x0

  • 0x0: Mask scan event interrupt

5

KS_FIFO_LIMIT_INT_MASK

R/W

0x0

  • 0x0: Mask FIFO limit interrupt

4

KS_FIFO_OV_INT_MASK

R/W

0x0

  • 0x0: Mask FIFO overflow interrupt

3

KS_FIFO_FULL_INT_MASK

R/W

0x0

  • 0x0: Mask FIFO full interrupt

2

KS_SCAN_FINISH_INT_MASK

R/W

0x0

  • 0x0: Mask scan finish interrupt

1

KS_FIFO_NOTEMPTY_INT_MASK

R/W

0x0

  • 0x0: Mask FIFO nonempty interrupt

0

KS_ALL_RELEASE_INT_MASK

R/W

0x0

  • 0x0: Mask All Release interrupt

REG_KS_ICR

  • Name : interrupt clear register

  • Size : 32

  • Address offset : 028h

  • Read/write access : R/W

This register is used to clear interrupts.

31:9 RSVD 8 KS_ALL_DEFAULT_INT_CLR 7 KS_STUCK_INT_CLR 6 RSVD 5 KS_FIFO_LIMIT_INT_CLR 4 KS_FIFO_OV_INT_CLR 3 RSVD 2 KS_SCAN_FINISH_INT_CLR 1 RSVD 0 KS_ALL_RELEASE_INT_CLR

Bit

Symbol

Access

Reset

Description

31:9

RSVD

R

-

Reserved

8

KS_ALL_DEFAULT_INT_CLR

R/W

0x0

Clear All Default interrupt flag

Write '1' to clear

7

KS_STUCK_INT_CLR

R/W

0x0

Clear Stuck interrupt flag

Write '1' to clear

6

RSVD

R

-

Reserved

5

KS_FIFO_LIMIT_INT_CLR

R/W

0x0

Clear FIFO limit interrupt flag

Write '1' to clear

4

KS_FIFO_OV_INT_CLR

R/W

0x0

Clear FIFO overflow interrupt flag

Write '1' to clear

3

RSVD

R

-

Reserved

2

KS_SCAN_FINISH_INT_CLR

R/W

0x0

Clear scan finish interrupt flag

Write '1' to clear

1

RSVD

R

-

Reserved

0

KS_ALL_RELEASE_INT_CLR

R/W

0x0

Clear all release interrupt flag

Write '1' to clear

REG_KS_ISR

  • Name : interrupt status register

  • Size : 32

  • Address offset : 02Ch

  • Read/write access : R

This register is about interrupt flags.

31:9 RSVD 8 KS_ALL_DEFAULT_INT_STATUS 7 KS_STUCK_EVENT_INT_STATUS 6 KS_SCAN_EVENT_INT_STATUS 5 KS_FIFO_LIMIT_INT_STATUS 4 KS_FIFO_OV_INT_STATUS 3 KS_FIFO_FULL_INT_STATUS 2 KS_SCAN_FINISH_INT_STATUS 1 KS_FIFO_NOTEMPTY_INT_STATUS 0 KS_ALL_RELEASE_INT_STATUS

Bit

Symbol

Access

Reset

Description

31:9

RSVD

R

-

Reserved

8

KS_ALL_DEFAULT_INT_STATUS

R

0x0

Masked All Default interrupt status, means row status equal to ks_row_default_status

7

KS_STUCK_EVENT_INT_STATUS

R

0x0

Masked Stuck event interrupt status

6

KS_SCAN_EVENT_INT_STATUS

R

0x0

Masked Scan event interrupt status

5

KS_FIFO_LIMIT_INT_STATUS

R

0x0

Masked FIFO limit interrupt status

4

KS_FIFO_OV_INT_STATUS

R

0x0

Masked FIFO overflow interrupt status

3

KS_FIFO_FULL_INT_STATUS

R

0x0

Masked FIFO full interrupt status

2

KS_SCAN_FINISH_INT_STATUS

R

0x0

Masked Scan finish interrupt status

1

KS_FIFO_NOTEMPTY_INT_STATUS

R

0x0

Masked FIFO nonempty interrupt status

0

KS_ALL_RELEASE_INT_STATUS

R

0x0

Masked All release interrupt status

REG_KS_ISR_RAW

  • Name : raw interrupt flag register

  • Size : 32

  • Address offset : 030h

  • Read/write access : R

The raw interupt flags do not effected by interrupt mask register.

31:9 RSVD 8 KS_ALL_DEFAULT_RAW_INT_STATUS 7 KS_STUCK_EVENT_RAW_INT_STATUS 6 KS_SCAN_EVENT_RAW_INT_STATUS 5 KS_FIFO_LIMIT_RAW_INT_STATUS 4 KS_FIFO_OV_RAW_INT_STATUS 3 KS_FIFO_FULL_RAW_INT_STATUS 2 KS_SCAN_FINISH_RAW_INT_STATUS 1 KS_FIFO_NOTEMPTY_RAW_INT_STATUS 0 KS_ALL_RELEASE_RAW_INT_STATUS

Bit

Symbol

Access

Reset

Description

31:9

RSVD

R

-

Reserved

8

KS_ALL_DEFAULT_RAW_INT_STATUS

R

0x0

All default interrupt, means row status equal to ks_row_defa ult_status

7

KS_STUCK_EVENT_RAW_INT_STATUS

R

0x0

Key stuck event raw interrupt

6

KS_SCAN_EVENT_RAW_INT_STATUS

R

0x0

Scan event raw interrupt, auto clear when the item is read

5

KS_FIFO_LIMIT_RAW_INT_STATUS

R

0x0

FIFO limit raw interrupt

4

KS_FIFO_OV_RAW_INT_STATUS

R

0x0

FIFO overflow raw interrupt

3

KS_FIFO_FULL_RAW_INT_STATUS

R

0x0

FIFO full raw interrupt

2

KS_SCAN_FINISH_RAW_INT_STATUS

R

0x0

Scan finish raw interrupt

1

KS_FIFO_NOTEMPTY_RAW_INT_STATUS

R

0x0

FIFO nonempty raw interrupt

Auto clear when FIFO is empty

0

KS_ALL_RELEASE_RAW_INT_STATUS

R

0x0

All Release raw interrupt

REG_KS_DISCHARGED_CTRL

  • Name : keyboard discharged register

  • Size : 32

  • Address offset : 034h

  • Read/write access : R/W

31:2 RSVD 1 KS_DISCHARGE 0 KS_INTERVAL_POL

Bit

Symbol

Access

Reset

Description

31:2

RSVD

R

-

Reserved

1

KS_DISCHARGE

R/W

0x0

  • 1: The keyboard is discharged before scan.

0

KS_INTERVAL_POL

R/W

0x0

  • 1: The keyboard is discharged at interval (FSM!=scan idle allrelease).

REG_KS_STUCK_CFG0

  • Name : Key-Scan Stuck Configuration Register

  • Size : 32

  • Address offset : 03Ch

  • Read/write access : R/W

31 KS_AUTO_CHECK_STUCK_ENABLE 30:0 KS_STUCK_TIME_THRESHOLD

Bit

Symbol

Access

Reset

Description

31

KS_AUTO_CHECK_STUCK_ENABLE

R/W

0x0

Enable auto check stuck or not

  • 0x1: Key-Scan auto chek stuck enabled.

  • 0x0: Key-Scan auto check stuck disabled.

30:0

KS_STUCK_TIME_THRESHOLD

R/W

0x7FFFFFFF

When the threshold is exceeded, it is considered to be stuck event or release stuck key, this counter is in scan clk.

REG_KS_STUCK_CFG1

  • Name : Key-Scan Stuck Configuration Register 1

  • Size : 32

  • Address offset : 040h

  • Read/write access : R/W

31:8 RSVD 7:0 KS_ROW_DEFAULT_STATUS

Bit

Symbol

Access

Reset

Description

31:8

RSVD

R

-

Reserved

7:0

KS_ROW_DEFAULT_STATUS

R/W

0xFF

Keyboard row default status:

  • 0b11111111: No key row is stucked

  • 0b11111110: Key row 0 is stucked

  • 0b11111101: Key row 1 is stucked

  • 0b11111100: Key row 0 and column 1 are stucked

  • 0b11111011: Key row 2 is stucked

REG_KS_STUCK_CFG2

  • Name : Key-Scan Stuck Configuration Register 2

  • Size : 32

  • Address offset : 044h

  • Read/write access : R/W

31 KS_STUCKROW_DETECT_ENABLE 30:24 RSVD 23:13 KS_STUCKROW_DETECT_TIME 12 RSVD 11:0 KS_STUCKROW_DETECT_TIME_INTERVAL

Bit

Symbol

Access

Reset

Description

31

KS_STUCKROW_DETECT_ENABLE

R/W

0x0

Enable stuckrow detect function, and row gpio will be "no pu ll" state in ks_stuckrow_detect_time_interval

30:24

RSVD

R

-

Reserved

23:13

KS_STUCKROW_DETECT_TIME

R/W

0x1

Key-Scan stuckrow detect timer, this counter is in clk_131k

12

RSVD

R

-

Reserved

11:0

KS_STUCKROW_DETECT_TIME_INTERVAL

R/W

0x0

Key-Scan stuckrow detect interval timer, this counter is in clk_131k

REG_KS_STUCK_KEY_STATUS1

  • Name : Key-Scan Status Register 1

  • Size : 32

  • Address offset : 048h

  • Read/write access : R

31:0 KS_KEY_STATUS1

Bit

Symbol

Access

Reset

Description

31:0

KS_KEY_STATUS1

R

0x0

Each bit means the corresponding key's stuck state

  • 0x1: key stucked

  • 0x0: key unstucked

Corresponding:

Key_status1[7:0] - row0[7:0]

Key_status1[15:8] - row1[7:0]

Key_status1[13:16] - row2[7:0]

Key_status1[31:24] - row3[7:0]

REG_KS_STUCK_KEY_STATUS2

  • Name : Key-Scan Status Register 2

  • Size : 32

  • Address offset : 04Ch

  • Read/write access : R

31:0 KS_KEY_STATUS2

Bit

Symbol

Access

Reset

Description

31:0

KS_KEY_STATUS2

R

0x0

Each bit means the corresponding key's stuck state

  • 0x1: key stucked

  • 0x0: key unstucked

Corresponding:

Key_status2[7:0] - row4[7:0]

Key_status2[15:8] - row5[7:0]

Key_status2[13:16] - row6[7:0]

Key_status2[31:24] - row7[7:0]

REG_KS_STUCK_KEY_ROW_STATUS1

  • Name : Key-Scan Row Status Register 1

  • Size : 32

  • Address offset : 050h

  • Read/write access : R

31:8 RSVD 7:0 KS_ROW_STATUS

Bit

Symbol

Access

Reset

Description

31:8

RSVD

R

-

Reserved

7:0

KS_ROW_STATUS

R

0x0

Each bit means the corresponding key row's stuck state

  • 0x1: row stucked

  • 0x0: row unstucked

Corresponding: row_status[7:0] - row[7:0]

REG_KS_DUMMY

  • Name : Key-Scan Dummy Register

  • Size : 32

  • Address offset : 058h

  • Read/write access : R/W

31:16 RSVD 15:0 DUMMY

Bit

Symbol

Access

Reset

Description

31:16

RSVD

R

-

Reserved

15:0

DUMMY

R/W

0x0

Reserved for HW